Multi-chips module package and manufacturing method thereof
A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside but also it can save cost due to the lead frame manufactured by a simple manufacturing processes. In addition, a manufacturing method of the multi-chips module package is provided.
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1. Field of Invention
This invention relates to a multi-chips module package. More particularly, the present invention is related to a multi-chips module package for integrating wire-bonded chip and flip chip therein and a manufacturing method thereof.
2. Related Art
As we know, in the semiconductor industries, the manufacture of semiconductors mainly comprises the manufacture of wafers and the assembly of integrated circuits devices. Therein, the integrated circuits (ICs) devices are completely formed by the processes of forming integrated circuits devices on the semiconductor wafers, sawing the wafers into individual integrated circuits devices, placing the individual integrated circuits devices on the substrates, electrically connecting the integrated circuits devices to the substrates respectively and encapsulating the integrated circuits devices and substrates to form a plurality of individual assembly packages. Due to the encapsulation covering the integrated circuits devices, the integrated circuits devices are able to be protected from the damp entering therein. In addition, the individual assembly packages may further provide external terminals for connecting to printed circuit board (PCB).
However, recently, integrated circuits packaging technology is becoming a limiting factor for the development in packaging integrated circuits devices of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Due to the assembly package in miniature and the integrated circuits operation in high frequency, MCM (multi-chips module) packages are commonly used in said assembly packages and electronic devices. Usually, said MCM package mainly comprising at least two chips encapsulated therein is provided, for example a processor unit, a memory unit and related logic units, to upgrade the electrical performance of said assembly package. In addition, the electrical paths between the chips in said MCM package are short so as to reduce the signal delay and save the reading and writing time.
Generally speaking, as shown in
Accordingly, the semiconductor industries develop a stacked multi-chips package as shown in
Furthermore, as shown in
As mentioned above, the layout of the circuits arranged in the substrate applicable to such package as shown above is so complex that the cost of substrate is very expensive due to the complexity of manufacturing substrate. Moreover, the electrical traces are longer so that the impedance, the inductance and the noise will be increased to lower the electrical performance.
Moreover, a multi-chips stacked package patented in U.S. Pat. No. 5,973,403 to Lo et.al entitled “Flip Chip Type Quad Flat Non-Leaded Package” is incorporated into this application for reference. Therein, it discloses a flip chip package which mainly comprises a plurality of leads for taking as electrical terminals for electrically connecting the chip and the external electronic devices. To be noted, the leads have first surfaces and second surfaces, and the chip are bonded to the first surfaces through a plurality of bumps and the second surfaces are exposed out of the encapsulation to connect to said external electronic devices as mentioned above. However, the leads are easily separated from the encapsulation so as to be not able to well connect to external electronic devices.
Therefore, providing another multi-chips module package and manufacturing method thereof to solve the mentioned-above disadvantages is the most important task in this invention.
SUMMARY OF THE INVENTIONIn view of the above-mentioned problems, the invention is to provide a multi-chips module package for integrating wire-bonded chip and flip chip therein and a manufacturing method thereof.
To achieve the above-mentioned, a multi-chips module package is provided, wherein the multi-chips module package mainly comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. Therein, the lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads; the first chip has a first active surface, a first back surface opposite to the first active surface, bump-bonding pads formed on the first active surface, wherein the first chip is placed on the lead frame and electrically connected to the lead frame through the bumps connecting the bump-bonding pads and the chip pads and the first leads; the second chip has a second active surface, a second back surface opposite to the second active surface, wire-bonding pads formed on the second active surface, wherein the second chip is placed over the first chip and electrically connected to the lead frame through the wires connecting the wire-bonding pads to the second leads; and the encapsulation covers the first chip, the second chip, the lead frame, and the wires.
Per this invention and mentioned above, the leads of the lead frame may have recesses formed thereon or the leads may have flat surfaces. In addition, the chip pads may have recesses for locking the bumps on the chip pads securely and takes as power connections or ground connections.
In summary, this invention is related to a multi-chips module package with a lead frame therein for electrically connecting the first chip and the second chip to external electronic devices. In such a manner, it not only reduces the distance of transmitting the electrical signals from chips to the outside so as to enhance electrical performance but also it can save cost due to the lead frame manufactured by a simple manufacturing processes.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention will become more fully understood from the detailed description given herein below illustrations only, and thus are not limitative of the present invention, and wherein:
The multi-chips module package according to the preferred embodiments of this invention will be described herein below with reference to the accompanying drawings, wherein the same reference numbers refer to the same elements.
As shown in
To be noted, the lead frame 130 as mentioned above has a plurality of leads 134, chip pads 142 and tie bars 143, wherein at least one of the chip pads 142 is connected to one of the leads 134 through the corresponding tie bar 143 as shown in
Referring to FIGS. 6 to 13, which are partially enlarged cross-sectional views showing the progression of steps for forming a multi-chips module package according to the first and other preferred embodiments of this invention.
As shown in
Then, referring to
Furthermore, a second chip 120 has a second active surface 124 and a second back surface 126, and the second chip 120 is attached to the first back surface 113 of the first chip 110 via an adhesive 127, such as epoxy resin or silver paste.
Referring to
Referring to
Referring to
Referring to
Referring to
As mentioned above, in this package, the lead frame is utilized to carry the chips, accordingly, it not only reduces the distance of transmitting the electrical signals from chips to the outside so as to enhance electrical performance but also can save cost due to the lead frame manufactured by a simple manufacturing processes.
Although the invention has been described in considerable detail with reference to certain preferred embodiments, it will be appreciated and understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims
1-17. (canceled)
18. A manufacturing method of multi-chips module packages, comprising:
- providing a first chip, the chip having a first active surface, a first back surface and a plurality of bump-bonding pads formed on the first active surface;
- forming a plurality of bumps over the bump-bonding pads;
- providing a second chip, the chip having a second active surface, a second back surface and a plurality of wire-bonding pads formed on the second active surface;
- providing a lead frame strip, the lead frame strip having a plurality of lead frame and said each lead frame having first leads, second leads and a plurality of chip pads connecting to the first leads;
- placing the first chip over the chip pads and connecting the first chip and the chip pads through the bumps;
- placing the second chip over the first chip;
- providing a plurality of wires to connect the wire-bonding pads and the second leads;
- forming an encapsulation to cover the first chip, the second chip, the wires and the chip pads to form a plurality of semi-finished multi-chips module packages, wherein a portion of the first leads and the second leads are exposed out of the encapsulation; and
- singulating the lead frame strip to have the semi-finished multi-chips module packages separated into a plurality of the multi-chips module packages. The method of claim 18, further comprising steps of:
- providing a plurality of tapes attached to the portions of the first leads and the second leads; and
- removing the taps to leave the portions of the first leads and the second leads exposed out of the encapsulation after performing the step of forming an encapsulation.
19. The method of claim 18, further comprising a step of forming under bump metallurgy layers on the bump-bonding pads.
20. The method of claim 18, further comprising a step of etching the first leads and the second leads to form a plurality of reentrant portions on the first leads and the second leads.
21. The method of claim 18, further comprising a step of forming gold layers on the second leads.
22. The method of claim 18, further comprising a step of forming gold layers on the second leads.
23. The method of claim 18, further forming a recess on the chip pad.
24. The method of claim 23, further filling a solder material in the recess.
25-30. (canceled)
Type: Application
Filed: Apr 2, 2007
Publication Date: Aug 2, 2007
Applicant: Advanced Semiconductor Engineering, Inc. (Kaoshiung)
Inventors: Chian-Chi Lin (Tainan), Chih-Huang Chang (Tainan)
Application Number: 11/730,442
International Classification: H01L 23/495 (20060101);