LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
The present invention relates to the field of integrated circuits; more specifically, it relates to backside through vias and methods of fabricating backside through vias for electrical connection to elements of integrated circuits.
BACKGROUND OF THE INVENTIONThere are many integrated circuit applications where it is desirable to reduce the resistance and inductance of signal lines in circuits normally associated with frontside wire bond pad connections. For example, because of the inductance associated with wire bond pad connections to the emitter of NPN hetero-junction bipolar transistors (HBT), the maximum practical operating frequency of circuits using NPN HBTs in wire bond packages is about 3 GHz even though the transistors are capable of running at higher frequencies. Therefore, there is a need for interconnect structures and methods of fabricating interconnect structures with reduced inductance and resistance for connecting signals to circuit elements of integrated circuits.
SUMMARY OF THE INVENTIONA first aspect of the present invention is a method for forming a contact, comprising: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from the backside of the substrate to expose the through via.
A second aspect of the present invention is the first aspect, further including: forming a device contact opening in the first dielectric layer and simultaneously with the filling the trench and co-planarizing, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
A third aspect of the present invention is the first aspect, further including: before forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
A fourth aspect of the present invention is the first aspect, further including: after forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
A fifth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench and forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench; or forming said tungsten layer on said sidewalls and said bottom of said trench, said tungsten layer of sufficient thickness to fill said trench.
A sixth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench; or forming said polysilicon layer on said sidewalls and said bottom of said trench; and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
A seventh aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench; forming a conformal tungsten layer over said insulating layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal tungsten layer on said sidewalls and said bottom of said trench, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
An eighth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal polysilicon layer on said sidewalls and said bottom of said trench, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
A ninth aspect of the present invention is the first aspect, further including: forming a hetero-junction bipolar transistor in and on said substrate; forming a device contact in the first dielectric layer, the device contact in physical and electrical contact to an emitter of the hetero-junction bipolar transistor; and forming a wire in a second dielectric layer, the second dielectric layer formed over the first dielectric layer and the wire in direct physical and electrical contact with the device contact and the through via.
A tenth aspect of the present invention is the first aspect, wherein the trench extends to and contacts a buried oxide layer in the substrate and the thinning the substrate removes the buried oxide layer.
BRIEF DESCRIPTION OF DRAWINGSThe features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 3A1 through 3A5 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first variation of a third embodiment of the present invention;
FIGS. 3B1 through 3B3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second variation of the third embodiment of the present invention;
FIGS. 3C1 through 3C3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a third variation of the third embodiment of the present invention;
FIGS. 4A1 through 4A3 are cross-sectional drawings illustrating a first method of filling a through via or stud contact of the third embodiment of the present invention;
FIGS. 4B1 through 4B4 are cross-sectional drawings illustrating a second method of filling a through via or stud contact of the third embodiment of the present invention;
FIGS. 4C1 through 4C4 are cross-sectional drawings illustrating a third method of filling a through via or stud contact of the third embodiment of the present invention;
FIGS. 4D1 through 4D5 are cross-sectional drawings illustrating a fourth method of filling a through via or stud contact of the third embodiment of the present invention;
A damascene process is one in which wire trenches or via openings (via openings may also be called via trenches) are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a planarization process, such as a one or more of a chemical-mechanical-polish (CMP) process or reactive ion etch (RIE) process, is performed to remove excess conductor and make the surface of the conductor co-planer or substantially co-planer with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) are formed the process is called single-damascene. Stud contacts (which are equivalent to single damascene wires and vias and which are formed in the first dielectric layer over the semiconductor substrate) are also formed using single-damascene processes.
A dual-damascene process is one in which wire and via openings are formed in a dielectric prior to metallization. For example, via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. (Alternatively, the wire trenches may be formed first, followed by formation of the via openings.) All via openings intended to conduct electric current are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planer with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias.
Formed on top of first dielectric layer 105 is a second dielectric layer 110. Formed on top of second dielectric layer 110 is a third dielectric layer 115. Formed on top of third dielectric layer 115 is a fourth dielectric layer 120. In one example, second, third and fourth dielectric layers 110, 115 and 120 each comprising one or more layers of a low K (dielectric constant) material, hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiOx(CH3)y or SiCxOyHy or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), porous SiCOH, a high, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), plasma-enhanced silicon nitride (PSiNx) or NBLok (SiC(N,H)). A low K dielectric material has a relative permittivity of about 3 or less. Formed on top of fourth dielectric layer 120 is a insulating layer 125. In one example, insulating layer 125 comprises a layer of SiO2, Si3N4, polyimide or combinations of layers thereof. The use of four dielectric layers is exemplary and more or less dielectric layer and corresponding wires and vias may be used.
Formed partially in substrate 100 and partially in first dielectric layer 105 is an exemplary HBT 130. HBT 130, may be replaced by other devices known in the art, such as metal-oxide-silicon field effect transistor (MOSFET)s, standard bipolar transistors, diodes, thin film or diffused silicon substrate resistors and thin film capacitors. (See also
Formed in third dielectric layer 115 is a dual-damascene wire/via 155. Formed in fourth dielectric layer is a dual-damascene wirebond pad/vias 160A and 160B. In one example, dual-damascene wire/via 155 and dual-damascene wirebond pad/vias 160A and 160B comprise a core conductor of copper (Cu) surrounded by a liner on the sidewalls and bottom of the core conductor, the liner comprising Ta, TaN, tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), titanium nitride (TiN) or combinations of layers thereof. Dual-damascene wirebond pad/vias 160A and 160B may also include a layer of aluminum (Al) on the exposed top surface of the core conductor.
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Afterwards, of additional levels of an integrated circuit are performed fabricated and the exemplary HBT, MOSFET 135, stud contacts 140A, 140B and 140C and other structures illustrated in
FIGS. 3A1 through 3A5 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first variation of a third embodiment of the present invention. In
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Opening 265A is aligned over the emitter of HBT 130, openings 265B are aligned over STI 250 and opening 265C over the gate of MOSFET 135. An optional silicide layer (not shown) has been previously formed (prior to formation of dielectric layer 105) on the emitter of HBT 130 the gate of FET 265C exposed in opening 265C. An optional silicide layer (not shown) was also formed over the base and collector of HBT 130, the source and drain of MOSFET 135, contacts to substrate 100, and other structures that requiring ohmic contact. Examples of metal suicides include but is not limited to titanium, cobalt, and nickel silicide. Silicides are usually formed using a self-aligned selective process by deposition of a metal on a silicon surface, heating to between about 400° C. and about 900° C. (in one example, heating to about 600° C.) and etching away the unreacted metal; or other processes, such as polycide with lithographic patterning and RIE or wet etching, can be used.
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In one example, the resistance through vias 265C is about 0.003 ohm per 10,000 square microns. Thus, a short, low resistance and low inductance path has been created from the backside of substrate 100, through the through vias 270C, damascene wire 145 and stud contact 140A to HBT 130.
FIGS. 3B1 through 3B3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second variation of the third embodiment of the present invention. Except for the fact, that in the second variation of the third embodiment of the present invention, stud contacts are completely formed first and then through vias, the second variation of the third embodiment of the present invention is similar to the first variation.
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FIGS. 3C1 through 3C3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a third variation of the third embodiment of the present invention. Except for the fact that in the third variation of the third embodiment of the present invention stud contacts are not formed until after the through vias, the third variation of the third embodiment of the present invention is similar to the first variation.
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Again, substrate 100 may be an SOI substrate for any of the three variations of the third embodiment of the present invention.
In the following four methods of filling a through via/and or a stud contact depending upon the variation of the third embodiment of the present invention that is being practiced, only an exemplary through via will be illustrated.
FIGS. 4A1 through 4A3 are cross-sectional drawings illustrating a first method of filling a through via or stud contact of the third embodiment of the present invention. In
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FIGS. 4B1 through 4B4 are cross-sectional drawings illustrating a second method of filling a through via or stud contact of the third embodiment of the present invention. In
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FIGS. 4C1 through 4C4 are cross-sectional drawings illustrating a third method of filling a through via or stud contact of the third embodiment of the present invention. In
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FIGS. 4D1 through 4D5 are cross-sectional drawings illustrating a fourth method of filling a through via or stud contact of the third embodiment of the present invention. In
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The first (FIGS. 4A1 through 4A3) and third (FIGS. 4C1 through 4C4) fill processes described supra may be used with the first (FIGS. 3A1-3A5) variation of the third embodiment of the present invention. The first (FIGS. 4A1 through 4A3), second (FIGS. 4B1 through 4B4), third (FIGS. 4C1 through 4C4) and fourth (FIGS. 4D1 through 4D5) fill processes described supra may be used with the second (FIGS. 3B1 through 3B3) and third variations (FIGS. 3B1 through 3B3) of the third embodiment of the present invention.
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Formed in a first dielectric layer 755 is a stud contact 760 in physical and electrical contact with polysilicon emitter 750. There may be a layer of metal silicide between stud contact 760 and polysilicon emitter 750. Also formed in first dielectric layer 755 is a though via 765 extending into/through substrate 705 according to any of the various embodiments of the present invention. Formed in a second dielectric layer 770 is a damascene wire 775. Damascene wire 770 is in direct physical and electrical contact with stud contact 755 and through via 765, thus providing an electrical path from the emitter of HBT 700 to the backside of substrate 705. The connection to the emitter of HBT 700 should be considered exemplary and connections may be made to the base or collector reach throughs. A third dielectric layer 780 is formed on top of second dielectric layer 770 and wire 775. Additional dielectric layers and wiring layers may be formed as required.
Thus, the various embodiments of the present invention provide interconnect structures and methods of fabricating interconnect structures with reduced inductance and resistance for connecting signals to circuit elements of integrated circuits.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims
1. A method for forming a contact, comprising:
- forming a dielectric isolation in a substrate, said substrate having a frontside and an opposing backside;
- forming a first dielectric layer on said frontside of said substrate;
- forming a shallow trench in said first dielectric layer, said trench aligned over and within a perimeter of said trench isolation and extending to said dielectric isolation;
- extending said trench formed in said first dielectric layer through said dielectric isolation and into said substrate to a depth less than a thickness of said substrate;
- filling said trench and co-planarizing a top surface of said trench with a top surface of said first dielectric layer to form an electrically conductive through via; and
- thinning said substrate from said backside of said substrate to expose said through via.
2. The method of claim 1, further including:
- forming a device contact opening in said first dielectric layer and simultaneously with said filling said trench and co-planarizing, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
3. The method of claim 1, further including:
- before forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
4. The method of claim 1, further including:
- after forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
5. The method of claim 1, wherein said filling said trench includes:
- either forming a insulating layer on sidewalls and a bottom of said trench and forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench; or
- forming said tungsten layer on said sidewalls and said bottom of said trench, said tungsten layer of sufficient thickness to fill said trench.
6. The method of claim 1, wherein said filling said trench includes:
- either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench; or
- forming said insulating layer on said sidewalls and said bottom of said trench; and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
7. The method of claim 1, wherein said filling said trench includes:
- either forming a insulating layer on sidewalls and a bottom of said trench; forming a conformal tungsten layer over said insulating layer, and
- forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or
- forming a conformal tungsten layer on said sidewalls and said bottom of said trench, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
8. The method of claim 1, wherein said filling said trench includes:
- either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or
- forming a conformal polysilicon layer on said sidewalls and said bottom of said trench, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
9. The method of claim 1, further including:
- forming a hetero-junction bipolar transistor on an in said substrate;
- forming a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
- forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
10. The method of claim 1, wherein said trench extends to and contacts a buried oxide layer in said substrate and said thinning said substrate removes said buried oxide layer.
11. A structure, comprising:
- a dielectric isolation in a substrate, said substrate having a frontside and an opposing backside;
- a first dielectric layer on said frontside of said substrate; and
- an electrically conductive through via extending through said first dielectric layer, said dielectric isolation and said substrate exposed on said backside of said substrate.
12. The structure of claim 11, further including:
- a device contact extending through said first dielectric layer and electrically contacting a device formed in said substrate, in said first dielectric layer or both in said substrate and in said first dielectric layer.
13. The structure of claim 12, wherein said device contact and said through via both comprise layers of the same materials, said layers of the same materials layered upon each other in the same sequence.
14. The structure of claim 12, wherein said through via include a insulating layer on sidewalls of said through via, said insulating layer comprising TiN or hydrogen rich silicon.
15. The structure of claim 11, wherein said through via comprises either:
- a tungsten core and a titanium nitride liner on sidewalls and a bottom of said tungsten core; or
- said a tungsten core, a titanium nitride liner on said sidewalls and said bottom of said tungsten core and an insulating layer on said titanium nitride liner.
16. The structure of claim 11, wherein said through via comprises either:
- a tungsten core, a titanium nitride liner on sidewalls and a bottom of said tungsten core, a polysilicon layer on said titanium nitride liner; or
- said tungsten core, said titanium nitride liner on said sidewalls and said bottom of said tungsten core, said polysilicon layer on said titanium nitride liner and an insulating layer on said polysilicon layer.
17. The structure of claim 11, wherein said through via comprises either:
- an oxide core, a tungsten liner on sidewalls and a bottom of said oxide core, a titanium nitride liner on said tungsten liner; or
- said oxide core, said tungsten liner on said sidewalls and said bottom of said oxide core, said titanium nitride liner on said tungsten liner and an insulating layer on said titanium nitride liner.
18. The structure of claim 11, wherein said through via comprises either:
- an oxide core, a tungsten layer on sidewalls and a bottom of said oxide core, a polysilicon layer on said tungsten layer or;
- said oxide core, said tungsten layer on said sidewalls and said bottom of said oxide core, said polysilicon layer on said tungsten layer and an insulating layer on said polysilicon layer.
19. The structure of claim 11, further including:
- a hetero-junction bipolar transistor formed on and in said substrate;
- a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
- a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
20. A method for forming a contact, comprising:
- forming a first dielectric layer on a frontside of a substrate, said substrate having a backside opposing said frontside;
- forming an electrically conductive first stud contact in said first dielectric layer, said first stud contact extending through said first dielectric layer to said frontside of said substrate;
- thinning said substrate from said backside of said substrate to form a new backside of said substrate;
- forming a trench in said substrate, said trench extending from said new backside of said substrate to said first dielectric layer, a bottom surface of said first stud contact exposed in said trench; and
- forming a conformal electrically conductive layer on said new backside of said substrate, sidewalls of said trench, exposed surfaces of said first dielectric layer and exposed surfaces of said first stud contacts, said conductive layer not thick enough to completely fill said trench.
21. The method of claim 20, further including, removing said conductive layer from said new backside of said substrate.
22. The method of claim 20, further including:
- before said forming a conformal electrically conductive layer, forming a conformal dielectric layer on said sidewalls of said trench.
23. The method of claim 20, wherein said conformal electrically conductive layer comprises a first layer comprising copper over a second layer comprising a layer of W, a layer of Ti, a layer TiN, a layer of Ta, a layer of TaN or combinations thereof.
24. The method of claim 20, further including:
- forming a hetero-junction bipolar transistor on and in said substrate;
- forming a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
- forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said first and second stud contacts.
25. A structure, comprising:
- a first dielectric layer on a frontside of a substrate, said substrate having a backside opposing said frontside;
- an electrically conductive first stud contact in said first dielectric layer, said first stud contact extending through said first dielectric layer to said frontside of said substrate;
- a trench in said substrate, said trench extending from said backside of said substrate to said first dielectric layer, a bottom surface of said first stud contact exposed in said trench; and
- a conformal electrically conductive layer over sidewalls of said trench, and on exposed surfaces of said first dielectric layer and exposed surfaces of said first stud contacts, said conductive layer not thick enough to completely fill said trench.
26. The structure of claim 25, further including, wherein said conductive layer extends over said backside of said substrate.
27. The structure of claim 25, further including:
- a conformal dielectric layer between said on said sidewalls of said trench and said conductive layer.
28. The structure of claim 25, wherein said conformal electrically conductive layer comprises a first layer comprising copper over a second layer comprising a layer of W, a layer of Ti, a layer TiN, a layer of Ta, a layer of TaN or combinations thereof.
29. The structure of claim 20, further including:
- a hetero-junction bipolar transistor formed on and in said substrate;
- a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
- a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer, said wire in direct physical and electrical contact with said first and second stud contacts.
30. A method for forming a contact, comprising:
- performing a first ion implantation into a region of a frontside of substrate to form a first doped region in said substrate, said substrate having a backside opposing said frontside;
- growing an epitaxial layer on said frontside of said substrate;
- performing a second ion implantation into a region of a said epitaxial layer to form a second doped region in said epitaxial later, said second doped region aligned over at least a portion of said first doped region; and
- heating said substrate and epitaxial layer in order to convert said first and second doped regions into a continuous diffused through via extending from a top surface of said epitaxial layer into said substrate.
31. The method of claim 30, further including:
- between said first and second ion implantations, growing an oxide layer on said substrate and then removing said oxide layer.
32. The method of claim 30, wherein:
- said substrate is doped P-type and has a resistivity between about 10 ohm-cm and about 500 ohm-cm;
- said epitaxial layer is doped is doped P-type and has a resistivity between about 10 ohm-cm and about 500 ohm-cm; and
- said through via is doped P-type and has a resistivity between about 0.005 ohm-cm and about 0.05 ohm-cm.
33. The method of claim 30, wherein said epitaxial layer is at least about 40 microns thick.
34. The method of claim 30, further including:
- forming a hetero-junction bipolar transistor on and in said substrate;
- forming a first dielectric layer on said top surface of said epitaxial layer;
- forming a first stud contact in said first dielectric layer, said first stud contact in physical and electrical contact with said diffused through via;
- forming a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
- forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said first and second stud contacts.
35. The method of claim 30, further including:
- simultaneously with performing said first ion implantation into said region of a frontside of substrate to form said first doped region in said substrate, performing said first ion implantation into said substrate in an additional doped region of said frontside of substrate to form a second first doped region in said substrate and wherein after said growing said epitaxial layer on said frontside of said substrate, a depression is formed in a top surface of said epitaxial layer over said additional doped region.
36. The method of claim 35, further including:
- aligning a photomask to said depression.
37. A method for forming a contact, comprising:
- forming a dielectric isolation in an upper substrate, a bottom surface of said upper substrate bonded to a top surface of a lower substrate, said lower substrate doped to a first concentration and said upper substrate doped to a second concentration, said second concentration greater than said first concentration;
- forming a first dielectric layer on a top surface of said upper substrate;
- forming a trench in said first dielectric layer, said trench aligned over and within a perimeter of said dielectric isolation and extending to said dielectric isolation;
- extending said trench formed in said first dielectric layer through said dielectric isolation and into and through said upper substrate to or into said lower substrate a distance less than a first thickness of said lower substrate;
- filling said trench and co-planarizing a top surface of said trench with a top surface of said first dielectric layer to form an electrically conductive through via; and
- thinning said lower substrate from a bottom surface of said substrate.
38. The method of claim 37, further including:
- forming a device contact opening in said first dielectric layer and simultaneously with said filling said trench and co-planarizing, filling said device contact openings and co-planarizing a top surface of said filled contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
39. The method of claim 37, further including:
- before forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
40. The method of claim 37, further including:
- after forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
41. The method of claim 37, wherein said filling said trench includes:
- forming a insulating layer on sidewalls and a bottom of said trench; and
- forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench.
42. The method of claim 37, wherein said filling said trench includes:
- forming a insulating layer on sidewalls and a bottom of said trench;
- forming a conformal polysilicon layer over said insulating layer; and
- forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
43. The method of claim 37, wherein said filling said trench includes:
- forming a insulating layer on sidewalls and a bottom of said trench;
- forming a conformal tungsten layer over said insulating layer; and
- forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
44. The method of claim 37, wherein said filling said trench includes:
- forming a insulating layer on sidewalls and a bottom of said trench;
- forming a conformal polysilicon layer over said insulating layer;
- forming a conformal tungsten layer over said polysilicon layer; and
- forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
45. The method of claim 37, further including:
- forming a hetero-junction bipolar transistor on and in said upper substrate;
- forming a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
- forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
46. A structure, comprising:
- a dielectric isolation in an upper substrate, a bottom surface of said upper substrate bonded to a top surface of a lower substrate, said lower substrate doped to a first concentration and said upper substrate doped to a second concentration, said second concentration greater than said first concentration;
- a first dielectric layer on a top surface of said upper substrate; and
- an electrically conductive through via extending through said first dielectric layer, said trench isolation and said upper substrate to or into said lower substrate a distance less than a first thickness of said lower substrate.
47. The structure of claim 46, further including:
- a device contact extending through said first dielectric layer and electrically contacting a device formed in said upper substrate, in said first dielectric layer or both in said upper substrate and in said first dielectric layer.
48. The structure of claim 47, wherein said device contact and said through via both comprise layers of the same materials, said layers of the same materials layered upon each other in the same sequence.
49. The structure of claim 47, wherein said through via include a insulating layer on sidewalls of said through via, said insulating layer comprising TiN or hydrogen rich silicon.
50. The structure of claim 46, wherein said through via comprises:
- a tungsten core; and
- insulating layer on sidewalls of said core.
51. The structure of claim 46, wherein said through via comprises:
- a tungsten core;
- a polysilicon layer on sidewalls of said tungsten core; and
- a insulating layer on polysilicon layer.
52. The structure of claim 46, wherein said through via comprises:
- an oxide core;
- a tungsten layer on sidewalls of said oxide core; and
- a insulating layer on tungsten layer.
53. The structure of claim 46, wherein said through via comprises:
- a oxide core;
- a tungsten layer on sidewalls of said oxide core;
- a polysilicon layer on said tungsten layer; and
- a insulating layer on polysilicon layer.
54. The structure of claim 46, further including:
- a hetero-junction bipolar transistor formed in and on said upper substrate;
- a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
- a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
55. The structure of claim 46, wherein said upper substrate has a thickness between about 40 microns and about 100 microns and said lower substrate has a thickness between about 40 microns and about 100 microns.
Type: Application
Filed: Jan 13, 2006
Publication Date: Aug 16, 2007
Patent Grant number: 7563714
Inventors: Mete Erturk (St. Albans, VT), Robert Groves (Highland, NY), Jeffrey Johnson (Essex Junction, VT), Alvin Joseph (Williston, VT), Qizhi Liu (Essex Junction, VT), Edmund Sprogis (Underhill, VT), Anthony Stamper (Williston, VT)
Application Number: 11/275,542
International Classification: H01L 21/50 (20060101);