Semiconductor Devices and Method for Fabricating the Same
Methods for fabricating a copper interconnect of a semiconductor device are disclosed. An example method for fabricating a copper interconnect of a semiconductor device deposits a first insulating layer on a substrate having at least one predetermined structure, forms a trench and via hole through the first insulating layer by using a dual damascene process, and deposits a barrier layer along the bottom and the sidewalls of the trench and via hole. The example method forms a copper interconnect by filling the trench and via hole with copper and performing a planarization process, deposits a Ta/TaN layer over the substrate including the copper interconnect, removes some portion of the Ta/TaN layer so that the Ta/TaN layer remains only on the copper interconnect, deposits a second insulating layer over the substrate including the Ta/TaN layer, forms a via hole through the second insulating layer by removing some portion of the second insulating layer, and fills the via hole with a conductive material to complete a via.
This application is a divisional of U.S. application Ser. No. 11/026,941, filed Dec. 30, 2004, which claims the benefit of Korean Application No. 10-2003-0100705, filed on Dec. 30, 2003, which are hereby incorporated herein by reference in their entirety.
TECHNICAL FIELDThe present disclosure relates to a semiconductor device and, more particularly, to methods for fabricating a copper interconnect of a semiconductor device.
BACKGROUNDWith the high-integration of semiconductor devices, known metals such as tungsten, copper, or alloys thereof have been turned out to be unsuitable for an interconnect material of a semiconductor device because they have a high specific resistance and cause electro migration (EM) or stress migration (SM), thereby deteriorating reliability of the semiconductor device. EM is a defect due to the increase in current density within a metal interconnect. In other words, EM is created because the current density increases by high-speed operation of the semiconductor device according to a fine interconnect pattern. SM is a creep rupture (failure) mode caused by imposing tensile mechanical stress on the metal interconnect. The mechanical stress is created by the difference in thermal expansion coefficient between the metal interconnect and an insulating layer to protect the metal interconnect. The mechanical stress increases as the width of the metal interconnect becomes narrower.
To obviate the above-mentioned problems, copper has been suggested as an alternative for known interconnect materials. Copper has a low specific resistance and ensures reliability of a semiconductor device. In addition, copper alloy has high corrosion-resistance and ensures reliability of the interconnect although it has a relatively high specific resistance in comparison with copper.
A copper dual damascene process, which inlays metal in an interconnect line, has been developed as an alternative because efforts to improve a copper etching method proved to be unsuccessful. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction although it had been confronted with barriers in terms of apparatus due to completely different structures and across-the-board changes.
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However, the above-described known method of forming a copper interconnect has several problems. First, if there is an oxidized area on the surface of the copper interconnect, the adhesion between the copper interconnect and the capping layer weakens and, as a result, the SiN layer as the capping layer 13 loosens. Constantly, the copper of the interconnect is diffused into the portion in which the SiN layer gets loose. Such copper diffusion may cause a short circuit between interconnects. Second, when the via is formed to connect the upper and lower interconnects, the upper interconnect may not be connected with the lower interconnect if the SiN layer as the capping layer within the via hole is completely removed. Third, the SiN layer may raise the total dielectric constant of the upper and lower interconnects because the SiN layer itself has a high dielectric constant.
BRIEF DESCRIPTION OF THE DRAWINGS
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From the foregoing, persons of ordinary skill in the art will appreciate that by using the Ta/TaN layer as the capping layer instead of the SiN layer, the above-described methods of fabricating a copper interconnect enhance the adhesion between the capping layer and the lower copper interconnect, prevent a short circuit between interconnects, which is caused because the capping layer is not completely removed during the via formation process, and obviate increase in dielectric constant of total interconnects due to the capping layer with the high dielectric constant.
While the examples herein have been described in detail with reference to example embodiments, it is to be understood that the coverage of this patent is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the sprit and scope of the appended claims.
Claims
1. A semiconductor device comprising:
- a first insulating layer formed on a substrate having at least one predetermined structure;
- a trench and a first via hole formed through the first insulating layer;
- a barrier layer formed along the sidewalls and the bottom of the trench and first via hole;
- a copper interconnect formed by filling the trench and first via hole with copper;
- a Ta/TaN layer formed only on the copper interconnect and the barrier layer;
- a second insulating layer formed over the substrate including the Ta/TaN layer;
- a second via hole formed through the second insulating layer; and
- a via formed by filling the second via hole with a conductive material.
2. A semiconductor device as defined by claim 1, wherein the barrier layer is made of Ta/TaN.
3. A semiconductor device as defined by claim 1, wherein the copper interconnect is formed by using an electrochemical plating process.
4. A semiconductor device as defined by claim 1, wherein the Ta/TaN layer is used as a capping layer.
5. A semiconductor device as defined by claim 1, wherein a side wall of the Ta/TaN layer is contacted with the second insulating layer.
Type: Application
Filed: May 8, 2007
Publication Date: Sep 6, 2007
Inventor: In Chun (Yeoju-gun)
Application Number: 11/745,562
International Classification: H01L 23/485 (20060101);