Consisting Of Layered Constructions Comprising Conductive Layers And Insulating Layers, E.g., Planar Contacts (epo) Patents (Class 257/E23.019)
  • Patent number: 10418336
    Abstract: To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Morio Iwamizu
  • Patent number: 9041187
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9041205
    Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Patent number: 9024431
    Abstract: A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 9018742
    Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 8952538
    Abstract: A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hirohisa Matsuki
  • Patent number: 8946886
    Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 3, 2015
    Inventors: Ruben Fuentes, August Joseph Miller, Jr.
  • Patent number: 8941212
    Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 8883628
    Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chang-Chia Huang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Patent number: 8871568
    Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Szu Wei Lu, Jing-Cheng Lin
  • Patent number: 8816500
    Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Ivan Nikitin
  • Patent number: 8796686
    Abstract: An integrated circuit includes a seal ring structure disposed around a circuit that is disposed over a substrate. A first pad is electrically coupled with the seal ring structure. A leakage current test structure is disposed adjacent to the seal ring structure. A second pad electrically coupled with the leakage current test structure, wherein the leakage current test structure is configured to provide a leakage current test between the seal ring structure and the leakage current test structure.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen
  • Patent number: 8796139
    Abstract: A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Anandan Ramasamy, Yonggang Jin, Yun Liu
  • Patent number: 8791568
    Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 29, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiya Nakano, Yoshifumi Tomomatsu
  • Patent number: 8786072
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 22, 2014
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 8766452
    Abstract: A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 1, 2014
    Assignee: SK Hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 8749049
    Abstract: An electronic device is disclosed. The electronic device comprises at least one electronic chip and a package for the electronic chip. The package comprises a laminate substrate, wherein the electronic chip is attached on the laminate substrate. The laminate substrate comprises one or more conduction layers, one or more insulation layers and a plurality of pads formed in a conduction layer on the side of the laminate substrate opposite to the side connected to the electronic chip. Furthermore, the package comprises an insulation body formed around the electronic chip. Moreover, the package comprises a plurality of electrodes that extend through the insulation body. For each pad of the laminate substrate, wiring is formed in the one or more of conduction layers and in one or more vias passing through the one or more insulation layers for electrically connecting the pad with at least one of the electrodes.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: June 10, 2014
    Assignee: ST-Ericsson SA
    Inventor: Zhimin Mo
  • Patent number: 8742582
    Abstract: A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: June 3, 2014
    Assignee: Megit Acquisition Corp.
    Inventor: Mou-Shiung Lin
  • Patent number: 8736056
    Abstract: A structure for an integrated circuit with reduced contact resistance is disclosed. The structure includes a substrate, a cap layer deposited on the substrate, a dielectric layer deposited on the cap layer, and a trench embedded in the dielectric layer. The trench includes an atomic layer deposition (ALD) TaN or a chemical vapor deposition (CVD) TaN deposited on a side wall of the trench, a physical vapor deposition (PVD) Ta or a combination of the PVD Ta and a PVD TaN deposited on the ALD TaN or CVD TaN, and a Cu deposited on the PVD Ta or the combination of the PVD Ta and the PVD TaN deposited on the ALD TaN or the CVD TaN. The structure further includes a via integrated into the trench at bottom of the filled trench.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Hung-Wen Su
  • Publication number: 20140103545
    Abstract: A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Yi-Kan CHENG
  • Patent number: 8691631
    Abstract: A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: April 8, 2014
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8643184
    Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
  • Publication number: 20140027822
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Publication number: 20140021614
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Tien-I Bao
  • Patent number: 8618669
    Abstract: A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and multiple connection pads on the opposite side of the package substrate mounting pads, a resin component filling a space between the first substrate and the second substrate, and multiple component loading pads positioned to load an electronic component between the first substrate and the second substrate and formed on one of the first substrate and the second substrate. The connection pads of the second substrate are electrically connected to the connection pads of the first substrate.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: December 31, 2013
    Assignee: Ibiden Co., Ltd.
    Inventor: Toru Furuta
  • Patent number: 8598699
    Abstract: In one embodiment, there is provided a semiconductor device that includes: a substrate; a dielectric layer on the substrate; a first ground metal layer embedded in the dielectric layer and having a first DC potential, the first ground metal layer having a first hole therethrough; a first ground patch disposed in the first hole; a second ground metal layer embedded in the dielectric layer such that the dielectric layer is interposed between the first and second ground metal layers in a thickness direction of the dielectric layer, the second ground metal layer having a second DC potential and having a second hole therethrough; a second ground patch disposed in the second hole; a first via which electrically connects the first ground metal layer and the second ground patch; and a second via which electrically connects the second ground metal layer and the first ground patch.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoko Ono
  • Publication number: 20130299988
    Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Alfred Grill, James B. Hannon, Qinghuang Lin, Deborah A. Neumayer, Satoshi Oida, John A. Ott, Dirk Pfeiffer
  • Patent number: 8575754
    Abstract: A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: November 5, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Tsung-Fu Tsai, Tao-Chih Chang, Chau-Jie Zhan
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8552528
    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 8, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming Shang Chen
  • Publication number: 20130256888
    Abstract: A interconnect structure includes a first etch stop layer over a substrate, a dielectric layer over the first etch stop layer, a conductor in the dielectric layer, and a second etch stop layer over the dielectric layer. The dielectric layer contains carbon and has a top portion and a bottom potion. A difference of C content in the top portion and the bottom potion is less than 2 at %. An oxygen content in a surface of the conductor is less than about 1 at %.
    Type: Application
    Filed: May 18, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng SHIH, Hui-Chun YANG, Chih-Hung SUN, Joung-Wei LIOU
  • Patent number: 8546195
    Abstract: A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: October 1, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 8535546
    Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: September 17, 2013
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Shinnosuke Maeda
  • Patent number: 8531039
    Abstract: A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 10, 2013
    Assignee: Tessera, Inc.
    Inventors: Philip Damberg, Belgacem Haba, David B. Tuckerman, Teck-Gyu Kang
  • Patent number: 8513806
    Abstract: The laminated high melting point soldering layer includes: a laminated structure which laminated a plurality of three-layered structures, the respective three-layered structures including a low melting point metal thin film layer and a high melting point metal thin film layers disposed on a surface and a back side surface of the low melting point metal thin film layer; a first high melting point metal layer disposed on the surface of the laminated structure; and a second high melting point metal layer disposed on the back side surface of the laminated structure. The low melting point metal thin film layer and the high melting point metal thin film layer are mutually alloyed by TLP, and the laminated structure, and the first high melting point metal layer and the second high melting point metal layer are mutually alloyed by the TLP bonding.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 20, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Takukazu Otsuka, Keiji Okumura
  • Patent number: 8513778
    Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 20, 2013
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shunichi Tokitoh
  • Publication number: 20130207265
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu LIU, Yi-Shien MOR, Kuei-Shun CHEN, Yu Lun LIU, Han-Hsun CHANG, Shiao-Chian YEH
  • Publication number: 20130200521
    Abstract: Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi Ding, Jeffrey P. Gambino, Zhong-Xiang He, Alvin J. Joseph, Anthony K. Stamper, Timothy D. Sullivan
  • Patent number: 8492870
    Abstract: A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 23, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
  • Publication number: 20130175694
    Abstract: A method includes forming a dielectric layer over a substrate, forming an interconnect structure over the dielectric layer, and bonding a die to the interconnect structure. The substrate is then removed, and the dielectric layer is patterned. Connectors are formed at a surface of the dielectric layer, wherein the connectors are electrically coupled to the die.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Szu Wei Lu, Jing-Cheng Lin
  • Patent number: 8476759
    Abstract: A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chang-Chia Huang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20130140685
    Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: Infineon Technologies AG
    Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
  • Patent number: 8455992
    Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: June 4, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Woojin Chang
  • Publication number: 20130134596
    Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Kevin (Kunzhong) Hu, Chonghua Zhong, Edward Law
  • Patent number: 8450858
    Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 28, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Takuya Takahashi, Fumihiro Fuchino, Yuuichi Kohno, Masanori Miyata
  • Patent number: 8445995
    Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 21, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Cha-Hsin Lin, Tzu-Kun Ku
  • Patent number: 8446003
    Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 21, 2013
    Assignee: DENSO CORPORATION
    Inventors: Atsushi Komura, Yasuhiro Kitamura, Nozomu Akagi, Yasutomi Asai
  • Publication number: 20130105982
    Abstract: A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 2, 2013
    Applicants: STMICROELECTRONICS GRENOBLE2 SAS, STMICROELECTRONICS PTE LTD.
    Inventors: Yonggang Jin, Romain Coffy, Jerome Teysseyre
  • Publication number: 20130105979
    Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.
    Type: Application
    Filed: May 30, 2012
    Publication date: May 2, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chen Yung Ching