Semiconductor device
A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.
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This application is based upon and claims the benefits of priority from the prior Japanese Patent Application No. 2006-093275, filed on Mar. 30, 2006, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION(1) Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having a triple well structure.
(2) Description of the Related Art
With a semiconductor device in which a MOS transistor is used, variation due to noise in GND potential applied to a substrate causes variation in the back bias potential of a well region where the MOS transistor is formed. Accordingly, the threshold of the MOS transistor varies. As a result, the full performance of the semiconductor device cannot be obtained.
For example, a structure (triple well structure) where a p-type well region which is formed in a p-type semiconductor substrate and on which an n-type MOS transistor is formed is surrounded with an n-type well region is proposed as a method for reducing noise (see, for example, Japanese Patent Laid-Open Publication No. Hei3-030468). By adopting this method, noise from the semiconductor substrate can be cut off by a pn junction interface formed in the semiconductor substrate.
With a semiconductor device having a triple well structure, a structure in which a contact region for applying back bias voltage to a p-type well region is formed outside the p-type well region and an n-type well region is proposed to raise an integration level (see, for example, Japanese Patent Laid-Open Publication No. Hei10-199993). With this structure, the formation of hole-like conductive regions in the n-type well region is proposed to secure continuity between the p-type well region and the contact region.
As shown in
With the above structure, the p-type well region 2 which is shown in
With the semiconductor device having the triple well structure as shown in
As a result, paths from the contact region 5, via the substrate 4, through the conductive regions 3 to the n-type MOS transistors 1 may differ in length, depending on the positions of the n-type MOS transistors 1. For example, a path from the contact region 5, through a conductive region 3a shown in
If such a path the parasitic resistance of which is high exists in the substrate, the back bias potential of the p-type well region 2 cannot uniformly be controlled throughout by supplying back bias from the contact region 5 to the p-type well region 2 on which the n-type MOS transistors 1 are formed. As a result, the n-type MOS transistors 1a, 1b, and 1c cannot be controlled uniformly in a circuit which is made to operate with back bias potential varied. Furthermore, the influence of noise from the p-type Si substrate 4 or noise produced in the p-type well region 2 cannot be reduced significantly.
SUMMARY OF THE INVENTIONThe present invention was made under the background circumstances described above. An object of the present invention is to provide a high performance semiconductor device in which uniform control is secured and in which the influence of noise is reduced.
In order to achieve the above object, there is provided a semiconductor device comprising a semiconductor substrate of a first conduction type, a first well region of the first conduction type formed beneath a surface of the semiconductor substrate, transistors formed on the first well region, a second well region of a second conduction type formed in the semiconductor substrate to surround the first well region, and a plurality of conductive regions of the first conduction type which pierce through the second well region and which are arranged so as to make parasitic resistance from the semiconductor substrate to the transistors not extremely high, irrespective of the positions of the transistors, but approximately equal.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
Embodiments of the present invention will now be described in detail with reference to the drawings.
A first embodiment of the present invention will be described first.
With the semiconductor device shown in
An n-type well region 13 is formed in the p-type Si substrate 10 as a second well region of the second conduction type so that it surrounds the p-type well region 11. The n-type well region 13 is connected to a contact region 12. The potential of the n-type well region 13 can be controlled by applying bias (VDD) to the contact region 12.
As stated above, this semiconductor device has a triple well structure including the p-type well region 11 and the n-type well region 13 in the p-type Si substrate 10.
As shown in
The plurality of conductive regions 15 are formed at regular intervals, like a honeycomb, throughout the n-type well region 13 directly beneath the p-type well region 11.
A contact region 16 for supplying a predetermined back bias to the p-type well region 11 via the plurality of conductive regions 15 is formed on the surface of the p-type Si substrate 10. The plurality of conductive regions 15 are formed of, for example, p-type silicon. For example, when the n-type well region 13 directly beneath the p-type well region 11 is formed by implanting n-type impurity ions at high energy, the corresponding regions should be covered with a resist mask. By doing so, the plurality of conductive regions 15 can be formed.
As stated above, the conduction type of the plurality of conductive regions 15 is the same as that of the p-type well region 11 and the p-type Si substrate 10. Accordingly, electrical connection between the p-type well region 11 and the p-type Si substrate 10 is good and ohmic connection is obtained.
The plurality of conductive regions 15 are formed in the n-type well region 13 like a honeycomb. Therefore, compared with the arrangement of the conductive regions 3 shown in
The influence of the injection of minority carriers from the p-type Si substrate 10 to the n-type MOS transistors 14 can be avoided by properly adjusting the diameter, the number, the density, or the like of the plurality of conductive regions 15.
A second embodiment of the present invention will now be described.
Components in
In the semiconductor device according to the second embodiment of the present invention, a plurality of conductive regions 15 are arranged like a grid.
In the semiconductor device according to the second embodiment of the present invention, as shown in
In this case, the plurality of conductive regions 15 are also formed at regular intervals. Therefore, compared with the arrangement of the conductive regions 3 shown in
By the way, if the plurality of conductive regions 15 are arranged like a grid, edge portions (for example, edge portions in
In this case, conductive regions 15 are formed at shorter intervals in edge portions inside the dashed line P. This example is shown in
As stated above, the conductive regions 15 are formed at intervals shorter than the regular intervals in the edge portions inside the dashed line P. As a result, parasitic resistance does not become high in the outer region of the p-type well region 11.
A third embodiment of the present invention will now be described.
Components in
In the semiconductor device according to the third embodiment of the present invention, a p-type well region 11 shown in
As shown in
As stated above, even if the beltlike p-type well region 11 is formed, the plurality of conductive regions 15 are formed at the regular intervals in an n-type well region 13 directly beneath the p-type well region 11. By doing so, parasitic resistance from a contact region 16 through the plurality of conductive regions 15 to n-type MOS transistors 14 becomes low, compared with the arrangement of the conductive regions 3 shown in
As a result, when back bias is applied to the contact region 16, the back bias is uniformly supplied to the whole of the beltlike p-type well region 11. Accordingly, the back bias potential of the n-type MOS transistors 14 is uniformly controlled regardless of their positions on the beltlike p-type well region 11.
A fourth embodiment of the present invention will now be described.
Components in
In the semiconductor device according to the fourth embodiment of the present invention, a p-type well region 11 shown in
As shown in
As stated above, even if the p-type well region 11 is formed like a cross for reasons of circuit layout, the plurality of conductive regions 15 are formed at the regular intervals in an n-type well region 13 directly beneath the p-type well region 11. By doing so, parasitic resistance from a contact region 16 through the plurality of conductive regions 15 to n-type MOS transistors 14 becomes low, compared with the arrangement of the conductive regions 3 shown in
As a result, when back bias is applied to the contact region 16, the back bias is uniformly supplied to the whole of the crosslike p-type well region 11. Accordingly, the back bias potential of the n-type MOS transistors 14 is uniformly controlled regardless of their positions on the crosslike p-type well region 11.
An example in which a p-type well region 11 is formed like the letter “T” or “L” for reasons of circuit layout will now be described.
As shown in
As stated above, even if the p-type well region 11 is formed like the letter “T” or “L” for reasons of circuit layout, the plurality of conductive regions 15 are formed at the regular intervals in an n-type well region 13 directly beneath the p-type well region 11. By doing so, parasitic resistance from a contact region 16 through the plurality of conductive regions 15 to n-type MOS transistors 14 becomes low, compared with the arrangement of the conductive regions 3 shown in
As a result, when back bias is applied to the contact region 16, the back bias is uniformly supplied to the whole of the p-type well region 11 shown in
A fifth embodiment of the present invention will now be described.
Components in
In the semiconductor device according to the fifth embodiment of the present invention, the distance between a contact region 16 shown in
As shown in
As a result, when back bias is applied to the contact region 16, the back bias potential of the n-type MOS transistors 14a, 14b, and 14c is uniformly controlled regardless of the distance between the contact region 16 and the n-type MOS transistors 14a, 14b and 14c.
A sixth embodiment of the present invention will now be described.
Components in
In the semiconductor device according to the sixth embodiment of the present invention, n-type MOS transistors 14h and 14l formed on a p-type well region 11 shown in
As shown in
As a result, when back bias is applied to the contact region 16, the back bias potential of the high-speed n-type MOS transistor 14h can be controlled at a high speed. In addition, the effect of cutting off noise from a substrate is enhanced for the low-speed n-type MOS transistor 14l because the density of the conductive regions 15 is low.
In each of the semiconductor devices according to the above embodiments of the present invention, many pn junction interfaces are formed in a substrate because a plurality of conductive regions 15 are formed in an n-type well region 13. Therefore, these semiconductor devices can be used as semiconductor devices having on-chip capacitors.
In the present invention, a first well region of a first conduction type is formed in a semiconductor substrate of the first conduction type, transistors are formed on the first well region, a second well region of a second conduction type is formed to surround the first well region, and a plurality of conductive regions of the first conduction type are formed in the second well region so as to make parasitic resistance from the semiconductor substrate to the transistors not extremely high, irrespective of the positions of the transistors, but approximately equal.
As a result, a high performance semiconductor device in which back bias can be controlled uniformly in the first well region and in which the influence of noise from the substrate or the first well region can be reduced can be realized.
The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.
Claims
1. A semiconductor device comprising:
- a semiconductor substrate of a first conduction type;
- a first well region of the first conduction type formed beneath a surface of the semiconductor substrate;
- transistors formed on the first well region;
- a second well region of a second conduction type formed in the semiconductor substrate to surround the first well region; and
- a plurality of conductive regions of the first conduction type which pierce through the second well region and which are arranged so as to make parasitic resistance from the semiconductor substrate to the transistors not extremely high, irrespective of positions of the transistors, but approximately equal.
2. The semiconductor device according to claim 1, wherein the plurality of conductive regions are arranged at regular intervals.
3. The semiconductor device according to claim 2, wherein the plurality of conductive regions are arranged like a honeycomb or a grid.
4. The semiconductor device according to claim 1, wherein the plurality of conductive regions are formed densely in part or all of edge portions of the second well region, compared with a middle portion of the second well region.
5. The semiconductor device according to claim 1, wherein a shape of the first well region is like a belt, a cross, the letter “L,” or the letter “T” from a top view.
6. The semiconductor device according to claim 5, wherein if the shape of the first well region is like a cross, the letter “L,” or the letter “T” from the top view, the plurality of conductive regions are arranged at least in the second well region directly beneath a cross portion of the shape.
7. The semiconductor device according to claim 1, further comprising a contact region formed on a surface of the semiconductor substrate for supplying back bias to the first well region via the plurality of conductive regions, wherein arrangement of the plurality of conductive regions is determined on the basis of distance from the contact region to the transistors.
8. The semiconductor device according to claim 1, further comprising:
- other transistors which are formed on the first well region and which are different from the transistors; and
- other plural conductive regions of the first conduction type, in addition to the plurality of conductive regions, which pierce through the second well region and which are arranged so as to make parasitic resistance from the semiconductor substrate to the other transistors equal.
9. The semiconductor device according to claim 8, wherein the transistors differ from the other transistors in operation speed.
10. The semiconductor device according to claim 8, wherein compared with the other plural conductive regions, the plurality of conductive regions are formed densely in the second well region.
Type: Application
Filed: Aug 17, 2006
Publication Date: Oct 4, 2007
Applicant: FUJITSU LIMITED (Kawasaki)
Inventor: Takuji Tanaka (Kawasaki)
Application Number: 11/505,418
International Classification: H01L 29/94 (20060101);