FABRICATION METHODS FOR COMPRESSIVE STRAINED-SILICON AND TRANSISTORS USING THE SAME
Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the method are also provided.
This application is a Divisional of allowed application Ser. No. 10/909,403, filed on Aug. 3, 2004, which claims priority of Taiwan Application No. 93113926, filed on May 18, 2004, the entire contents of all are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. § 120.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a fabrication method for strained-silicon and, in particular, to compressive strained-silicon.
2. Brief Discussion of the Related Art
Chip operating speeds, while desirable, depend on driving current. Improving mobility of the device to increase driving current thereof has become a technique commonly used by chip manufacturers.
In recent years, research has proven that strained-silicon enhances carrier mobility significantly. As shown in
Tensile strained-silicon has been realized through several methods such that performance of the NMOS device is enhanced. However, there is no effective method to fabricate the compressive strained-silicon required to improve hole mobility and driving current of a PMOS device, a barrier to application of the strained-silicon technology to integrated circuits.
SUMMARY OF THE INVENTIONAn embodiment of a fabrication method for compressive strained-silicon comprises providing a silicon-containing substrate, implanting ions therein and converting the vicinity of the ion-containing region to strained-silicon.
An embodiment of a MOSFET fabricated by a fabrication method of compressive strained-silicon comprises a channel region in a silicon-containing substrate, source/drain regions adjacent to two ends of the channel region, a gate dielectric layer on the channel region and a gate on the gate dielectric layer. The region beneath the channel region is converted to a strain inducing layer after ion implantation and high temperature processing. Compressive strained-silicon is thereby formed in the channel region.
Another embodiment of a MOSFET fabricated by a fabrication method for compressive strained-silicon comprises a channel region in a silicon-containing substrate, source/drain regions adjacent to two ends of the channel region, a gate dielectric layer on the channel region and a gate on the gate dielectric layer. The regions beneath the source/drain regions are converted to a strain inducing layer after ion implantation and high temperature processing. Compressive strained-silicon is thereby formed in the source/drain regions and tensile strain induced in the channel region.
Embodiments of fabrication methods of compressive strained-silicon and devices fabricated thereby make use of ion implantation and high temperature processing to induce compressive strain in the vicinity of the region containing the implanted ions, such that hole mobility is increased. Furthermore, the compressive strain in the vicinity of the region containing the implanted ions can induce tensile strain in the region thereof.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, arc given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIGS. 4A˜4C show another embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation;
FIGS. 5A˜5D show another embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation; and
FIGS. 6A˜6C show another embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTSIn embodiments of fabrication methods for compressive strained-silicon and devices fabricated thereby, while hydrogen is used as an example of an ion used in implantation. Other ions that, can induce compressive strain after high temperature processing are also applicable to the disclosed embodiments.
FIGS. 4A˜4C illustrate another embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation. As shown in
FIGS. 5A˜5D illustrate yet another, embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation. As shown in
FIGS. 6A˜6C illustrate still another embodiment of fabrication methods of compressive strained-silicon using hydrogen ion implantation. As shown in
While the invention has been described by way of example and in terms of several embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
Claims
1. A transistor fabricated by a fabrication method for compressive strained-silicon, the transistor comprising:
- a strain inducing layer formed by ion implantation and high temperature processing;
- a channel region on the strain inducing layer, whereby compressive strained-silicon is formed therein;
- source/drain regions adjacent to two ends of the channel region;
- a gate dielectric layer on the channel region; and
- a gate on the gate dielectric layer.
2. The transistor as claimed in claim 1, wherein the ions implanted into the silicon-containing substrate are hydrogen.
3. The transistor as claimed in claim 2, wherein the dosage of implantation is between 1E14 cm−2 and 1E17 cm−2.
4. The transistor as claimed in claim 2, wherein implant depth is between 3 nm and 10 μm.
5. The transistor as claimed in claim 2, wherein the silicon-containing substrate is a single crystal, polycrystalline, amorphous silicon, SiGe, or silicon on insulator (SOI) substrate.
6. The transistor as claimed in claim 5, wherein the silicon-containing substrate is attached or bonded to other substrate or film.
7. The transistor as claimed in claim 2, wherein the channel region is an asymmetrical compressively strained channel.
8. The transistor as claimed in claim 2, wherein high temperature processing is performed at between 25° C. and 1200° C.
9. The transistor as claimed in claim 2, wherein the high temperature processing lasts from several seconds to hours.
10. The transistor as claimed in claim 2, wherein the source drain regions are formed using metal, silicide, SiGe.
11. The transistor as claimed in claim 2, wherein the gate dielectric layer is silicon-oxide, HfO2, Si3N4, Al2O3 or other dielectric material with a dielectric constant higher than 3.9.
12. The transistor as claimed in claim 2, wherein the gate is formed using metal, silicide, SiGe, poly-SiGe or polysilicon.
13. A transistor fabricated by a fabrication method of compressive strained-silicon, the transistor comprising:
- source/drain regions;
- strain inducing layers, formed after ion implantation and high temperature processing, under the source/drain regions;
- a channel region between the source/drain regions, whereby compressive strained-silicon is formed therein;
- a gate dielectric layer on the channel region; and
- a gate on the gate dielectric layer.
14. The transistor as claimed in claim 13, wherein the ions implanted into the silicon-containing substrate are hydrogen.
15. The transistor as claimed in claim 14, wherein the dosage of implantation is between 1E14 cm−2 and 1E17 cm−2.
16. The transistor as claimed in claim 14, wherein implant depth is between 3 nm and 10 μm.
17. The transistor as claimed in claim 14, wherein the silicon-containing substrate is a single crystal, polycrystalline, amorphous silicon, SiGe, or silicon on insulator (SOI) substrate.
18. The transistor as claimed in claim 17, wherein the silicon-containing substrate is attached or bonded to other substrate or film.
19. The transistor as claimed in claim 14, wherein the channel region is an asymmetrical compressively strained channel.
20. The transistor as claimed in claim 14, wherein high temperature processing is performed at between 25° C. and 1200° C.
21. The transistor as claimed in claim 14, wherein the high temperature processing lasts from several seconds to hours.
22. The transistor as claimed in claim 14, wherein the source drain regions are formed using metal, silicide, SiGe.
23. The transistor as claimed in claim 14, wherein the gate dielectric layer is silicon-oxide, HfO2, Si3N4, Al2O3 or other dielectric material with a dielectric constant higher than 3.9.
24. The transistor as claimed in claim 14, wherein the gate is formed using metal, silicide, SiGe, poly-SiGe or polysilicon.
Type: Application
Filed: Sep 24, 2007
Publication Date: Jan 31, 2008
Inventors: Min-Hung LEE (Taipei), Cheng-Yeh Yu (Changhua), Shing-Chii Lu (Hsinchu), Chee-Wee Liu (Taipei)
Application Number: 11/860,362
International Classification: H01L 29/78 (20060101);