TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
The present invention relates generally to sensing a signal in a two-terminal memory array. More specifically, the present invention relates to sensing a signal in a two-terminal memory array during a read operation or in preparation for a write operation.
BACKGROUND OF THE INVENTIONData storage in high-density memory devices can be accomplished using a variety of techniques. Often, the technique used depends on whether or not the stored data is volatile or non-volatile. In volatile memory devices, such as SRAM and DRAM, for example, stored data is not retained when power is removed from the memory device. On the other hand, for non-volatile memory devices, such as MRAM and Flash devices, stored data is retained when power is removed from the memory device.
Resistive state memory devices are a promising new type of non-volatile memory in which data is stored in a memory element as a plurality of resistive states. A first resistive state can represent a logic “1” and a second resistive state can represent a logic “0”. The first and second resistive states can be set by applying a write voltage of a predetermined magnitude, polarity, and duration across the memory element during a write operation. For example, voltage pulses can be used to write a logic “1” and a logic “0”, respectively.
In either case, after data has been written to the memory element, reading the value of the stored data in the memory element is typically accomplished by applying a read voltage across the memory element and sensing a read current that flows through the memory element. For example, if a logic “0” represents a high resistance and a logic “1” represents a low resistance, then for a constant read voltage, a magnitude of the read current can be indicative of the resistive state of the memory element. Therefore, based on Ohm's law, the read current will be low if the data stored is a logic “0” (e.g., high resistance) or the read current will be high if the data stored is a logic “1” (e.g., low resistance). Consequently, the value of the stored data can be determined by sensing the magnitude of the read current.
In high density memory devices, it is desirable to pack as many memory cells as possible in the smallest area possible in order to increase memory density and data storage capacity. One factor that can have a significant impact on memory density is the number of terminals that are required to access a memory element for reading or writing. As the number of terminals required to access the memory element increases, device area increases with a concomitant decrease in areal density. Most memory technologies, such as DRAM, SRAM, and some MRAM devices, require at least three terminals to access the core memory element that stores the data. However, in some memory technologies, such as certain resistance based memories, two terminals can be used to both read and write the memory element.
An array of two terminal memory elements can include a plurality of row conductors and a plurality of column conductors and each memory element can have a terminal connected with one of row conductors and the other terminal connected with one of the column conductors. The typical arrangement is a two terminal cross-point memory array where each memory element is positioned approximately at an intersection of one of the row conductors with one of the column conductors. The terminals of the memory element connect with the row and column conductors above and below it. A single memory element can be written by applying the write voltage across the row and column conductors the memory element is connected with. Similarly, the memory element can be read by applying the read voltage across the row and column conductors the memory element is connected with. The read current can be sensed (e.g., measured) flowing through the row conductor or the column conductor.
One challenge that arises from a two-terminal configuration is that memory elements that share a row or column conductor with the memory element being read will also have a potential difference across their respective row and column conductors. The adjacent memory elements can be referred to as half-selected memory elements. The potential difference across the terminals of half-selected memory elements can cause half-select currents to flow through those memory elements. The half-select currents are additive and can be considered as a leakage current that occurs during a read operation. In a high density memory device, the number of memory elements in an array can be several thousand or more. During a read operation to a selected memory element in the array, the half-select currents from half-selected memory elements in the same row or same column as the selected memory element can vastly exceed the magnitude of the read current flowing through the selected memory element. The read current can be considered to be a signal and a magnitude of that signal is indicative of a data value of the data stored in the selected memory element. On the other hand, the leakage current can be considered to be noise that masks the read current signal. Therefore, in a large array, a signal-to-noise ratio (S/N) of the read current to the leakage current is low. A low S/N ratio can make it difficult to distinguish between the read current and the leakage current. Consequently, the low S/N ratio makes it difficult to detect an accurate value for the stored data.
There are continuing efforts to improve accuracy in reading data and in increasing S/N ratios in memory arrays having leakage current.
Although the previous Drawings depict various examples of the invention, the invention is not limited by the depicted examples. Furthermore, the depictions are not necessarily to scale.
DETAILED DESCRIPTIONIn the following detailed description and in the several figures of the drawings, like elements are identified with like reference numerals. As shown in the drawings for purpose of illustration, the present invention is embodied in an apparatus for sensing current in a two-terminal memory array and in a method of sensing a signal in a two-terminal memory array.
In one embodiment, the present invention discloses an apparatus for two-cycle sensing in a two-terminal memory array having leakage current. The apparatus includes an array having a plurality of first conductive traces and a plurality of second conductive traces. An address unit receives an address, selects one of the plurality of second conductive traces during a first cycle, applies a first select voltage to the selected second conductive trace and applies a non-select voltage potential to un-selected traces. During a second cycle, the address unit selects one of the plurality of first conductive traces and applies a second select voltage to the selected first conductive trace. A sense unit senses a leakage current flowing through the selected second conductive trace during the first cycle and senses a total current flowing through the selected second conductive trace during the second cycle.
In another embodiment, the present invention discloses a method for two-cycle sensing in a two-terminal memory array having leakage current. The method includes providing an array having a plurality of first conductive traces and a plurality of second conductive traces. Receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces. A first select voltage is applied to one or more selected second conductive traces during a first cycle and during a second cycle. A non-select voltage potential is applied to the plurality of first conductive traces and unselected second conductive traces during the first cycle. During the first cycle, one or more leakage currents that flow through the one or more selected second conductive traces are sensed. During the second cycle, a second select voltage is applied to the selected first conductive trace while applying the non-select voltage potential to unselected first and second conductive traces and one or more total currents that flow through the one or more selected second conductive traces are sensed.
In the following detailed description, numerous specific details are set forth to provide a through understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known elements and process steps have not been described in depth in order to avoid unnecessarily obscuring the present invention.
In
Turning to
The array 100 includes a plurality of memory elements 10 for storing data. The memory elements 10 store data as a plurality of conductivity profiles with discrete resistances at certain voltages. Therefore, each memory element 10 is schematically depicted as a resistor. A magnitude of a resistance at a certain voltage of a specific memory element 10 is indicative of a value of stored data in the specific memory element 10. As an example, each memory element 10 can store a single bit of data as one of two distinct conductivity profiles with a first resistive state R0 at a read voltage VR indicative of a logic “0” and a second resistive state R1 at VR indicative of a logic “1”, where R0≠R1. Preferably, a change in conductivity, measured at VR, between R0 and R1, differs by at least a factor of approximately 10 (e.g., R0=1 MΩ and R1=100 kΩ). The memory elements 10 are not necessarily linear resistors and the resistance of the memory elements 10 may not be a linear function of the voltage applied across the memory elements 10. Therefore, a resistance R of the memory elements 10 can approximately be a function of the read voltage VR such that R≈f(VR).
The actual convention for determining which resistive state represents a logic “0” and a logic “1” will be application dependent and one skilled in the art will understand that the first resistive state R0 can be indicative of a logic “0” and the second resistive state R1 can be indicative of a logic “1”. Initially, memory elements 10 in the array 100 may be in a predetermined initial resistive state in which the conductivity profile of all of the memory elements 10 is indicative of the first resistive state R0 or the second resistive state R1. Subsequently, write operations to selected memory element 10′ can effectuate a change from the initial resistive state to the first resistive state R0 or the second resistive state R1. In some conventions, the first resistive state R0 (e.g., high resistance at VR) is referred to as a programmed state and the second resistive state R1 (e.g., low resistance at VR) is referred to as an erased state. Accordingly, a write operation in which a logic “1” is to be written to a programmed memory element 10 will result in the conductivity profile changing from the programmed state of R0 to the erased state of R1. One skilled in the art will appreciate that an opposite convention in which the erased state is R0 and the programmed state is R1 can also be used. Hereinafter, for the sake of clarity, the first resistive state R0 denotes a high resistance and a logic “0” and the second resistive state R1 denotes a low resistance and a logic “1”.
As another example, each memory element 10 can store multiple bits of data. Therefore, if two-bits of data are stored in each memory element 10, then there will be four distinct conductivity profiles with corresponding resistive states of R00, R01, R10, and R11, where R00>R01>R10>R11. For multi-bit data storage, it may be desirable for the highest and lowest resistive states R00 and R11 to differ by at least a factor of 100 at VR (e.g., R00≈1 MΩ and R11≈10 kΩ). Preferably, intermediate resistive states R01 and R10 have a resistance that falls between the highest and lowest resistance. For example, the intermediate resistive states R01 and R10 can have a resistance that is approximately evenly divided between the highest and lowest resistance or they may fall between the highest and lowest resistance based on a logarithmic scale. The difference between the highest and the lowest resistive states is necessary in order to distinguish between a magnitude of a read current that flows through a selected memory element 10 during a read operation. If the resistive states are spaced too closely together, then it may be difficult to sense differences between the read current for R01 and the read current for R10, for example. The ability to distinguish between the read currents for each resistive state becomes more critical in the presence of leakage currents that flow in the array 100 at the same time as the read current. The combined magnitude of the leakage currents can mask the read current, making it difficult to accurately determine the resistive state of the selected memory element 10 during the read operation.
Referring again to
In
A read operation to the selected memory element 10′ is effectuated by applying a select voltage VS having an appropriate read voltage magnitude across the selected first and second conductive traces 1′ and 2′. The select voltage VS is applied to the selected first and second conductive traces 1′ and 2′ based on the address ADDR received by the address unit 101. For example, the address ADDR can be from an address bus 125. The address unit 101 decodes the address ADDR and applies the select voltages across the appropriate pair of selected conductive traces 1′ and 2′. Furthermore, the address unit 101 applies the non-select voltage to the remaining conductive traces 1 and 2 (i.e., unselected traces 1 and 2).
Turning now to
The read voltage VR can be supplied by a single voltage source coupled with the selected first and second conductive traces 1′ and 2′ as depicted in
The selected memory element 10′ is electrically in series with the selected traces 1′ and 2′. Consequently, the read voltage VR causes a read current IR to flow through the selected memory element 10′. The magnitude of the read current IR will depend on the magnitude of the read voltage VR and a resistive state RS of the selected memory element 10′, such that IR≈VR÷RS. For a given read voltage VR, the read current IR will be lower when RS≈R0 (e.g., high resistance) and IR will be higher when RS≈R1 (e.g., low resistance). The direction of flow for the read current IR will depend on a polarity of the read voltage VR. The read voltage VR need not be a constant voltage and VR may be applied as a pulse. Preferably, VR is applied as a voltage pulse (e.g., a positive and/or negative pulse) One advantage to using a voltage pulse is that voltage pulses can have varying waveform shapes. Examples of waveform shapes include but are not limited to square waves, triangle waves, sine waves, and complex waveforms. A potential difference for the read voltage VR can be provided by separate voltage sources coupled with the selected conductive traces 1′ and 2′ such that VR=(VR1′−VR2′), where VR1′ is a first read voltage applied to the selected first conductive trace 1′ and VR2′ is a second read voltage applied to the selected second conductive trace 2′.
Half-Select CurrentDuring a read or write operation, it is preferable that unselected traces 1 and 2 not be allowed to float. Floating traces can result in voltages that disturb the resistive state in unselected memory elements 10. Accordingly, in
A write operation to the selected memory element 10′ in the array 100 is effectuated by applying a select voltage VS having an appropriate write voltage magnitude and polarity across the selected first and second conductive traces 1′ and 2′. In
The resistive state RS of the selected memory element 10′ can be changed by applying the appropriate write voltage VW to the selected traces 1′ and 2′. As one example, if the memory elements 10 are initially in the first resistive state R0 (e.g., high resistance) indicative of a logic “0”, then to overwrite the logic “0” with a logic “1”, a negative write voltage is applied to the selected second conductive trace 2′ and a positive write voltage is applied to the selected first conductive trace 1′. As a result, the selected memory element 10′ is overwritten and the first resistive state R0 is replaced by the second resistive state R1 (e.g., low resistance). As another example, to overwrite the state R1, a positive write voltage is applied to the selected second conductive trace 2′ and a negative write voltage is applied to the selected first conductive trace 1′. Consequently, the memory element 10′ is overwritten and the state R1 is replaced by the state R0.
A write current IW flows through the selected memory element 10′ during the write operation. A magnitude of the write current IW will depend on the resistive state RS (e.g., R0 or R1) of the selected memory element 10′ and a magnitude of the write voltage VW, such that IW≠VW÷RS. A direction of current flow for the write current IW will depend on a polarity of the write voltage VW. During the write operation, a half-select current flows through half-selected memory elements 10 as is depicted by a half-select current IH flowing through adjacent memory element 10 in
During a read operation, the read current IR flows through the selected memory element 10′ and the half-select current IH flows through the half-selected memory elements 10. In a memory device suitable for high-density data storage, the selected memory element 10′ will be greatly outnumbered by the half-selected memory elements 10 because in a large array 100 there can be several thousand or more half-selected memory element 10 in the same row and column as the selected memory element 10′. On an individual basis, each half-select current IH will typically be lower in magnitude than the read current IR. However, a combined magnitude of the half-select currents IH for all of the half-selected memory elements 10 can exceed that of the read current IR. Therefore, in order to accurately read the value of stored data in the selected memory element 10′, it is necessary to separate a signal representing the read current IR from a signal representing the total half-select currents IH.
Referring back to
Furthermore, it should be appreciated that this technique will typically generate data from only one memory cell. Accordingly, multiple bit block arrays are typically used in a multi-bit memory. Bit blocks arrays are typically electrically isolated from each other and are only capable of selecting a single memory cell at a time. The term bit block array describes both memories that store a single bit of data and multiple bits of data in a single memory cell (e.g., a memory cell that can store two bits of data as 00, 01, 10, and 11). The bit block arrays may be laid out next to each other in a single-layer cross-point array fabricated over a substrate in which the circuitry portions of the apparatus 150 (e.g., address unit 101, sense unit 103, and control unit 105) are fabricated, or may be stacked one upon another over a substrate in which the circuitry portions of the apparatus 150 are fabricated in a stacked cross-point memory, or some combination of both techniques. Reference is now made to
Turning now to
As was described above, the application of the select voltages VSR and VSC across the first and second conductive traces 1′ and 2′ causes the read current IR to flow through the selected memory element 10′ (denoted by a heavy dashed arrow for IR). In
Therefore, a total current IT flowing through the selected first conductive trace 1′ in row r2 is approximately: IT≈IH0+IH1+IH3+IR, where the half-select currents IH0, IH1, and IH3 represent leakage currents. A total leakage current IL flowing from the selected first conductive trace 1′ to the unselected second conductive traces 2 in columns (c0, c1, c3) is approximately: IL≈IH0+IH1+IH3. The half-select currents IH0, IH1, and IH3 can be sensed through the unselected second conductive traces 2 in columns (c0, c1, c3) because the memory elements 10 above and below the half-selected hc memory elements 10 in columns (c0, c1, c3) have the non-select voltages VNR and VNC applied across their respective terminals 11 and 12 so that the potential difference across those terminals is approximately 0 volts, assuming VNR and VNC are approximately equal to each other (i.e., VNR=VNC). Therefore, little or no current flows through those memory elements 10 and the current entering the unselected second conductive traces 2 is approximately the half-select currents IH0, IH1, and IH3.
Both the total current IT and the leakage current IL represent signals that can be processed to derive another signal that is indicative of a value of stored data in the selected memory cell 10′. Accordingly, the sense unit 103 senses the total current IT flowing in the selected first conductive trace 1′ and senses the leakage current IL flowing in the unselected second conductive traces 2 and output those currents as signals (see
Since the row and column orientation is arbitrary, one skilled in the art will appreciate that the total current IT can be sensed flowing through the selected second conductive trace 2′ and the leakage current IL can be sensed flowing through unselected first conductive traces 1. Accordingly,
Therefore, pre-reading can be an apparatus and/or a method for sensing a signal indicative of stored data in a selected memory element 10′ by distinguishing the signal represented by the read current IR from a noise signal represented by the leakage current IL. In the context of a read operation where the signal to noise ratio between the read current IR and the leakage current IL is low (i.e., IL>>IR), it is desirable for the pre-read operation to be an integral part of a read operation to the array 100 so that an accurate sensing of the read current IR can be used to accurately determine the value of the stored data.
In the context of a write operation, it is not necessary to separate the read current IR from the leakage current IL in order to accurately determine the value of the stored data. However, the optional use of the pre-read operation during a write operation may be desirable and can have several advantages, particularly when the stored data and the data to be written are approximately identical to each other (e.g., overwriting redundant data). The advantages in a redundant data scenario include but are not limited to preventing the overwriting of redundant data, reducing write operation latency by aborting the write operation when the data is redundant, and reducing memory element 10 wear out and stress by preventing unnecessary write operations to selected memory elements 10′.
Read Operation Select VoltagesThe select voltages VSR and VSC can be generated in a variety of ways. As one example, VSR can be a positive or negative voltage and VSC can be approximately at a ground potential. On the other hand, VSC can be a positive or negative voltage and VSR can be approximately at a ground potential. As another example, both VSR and VSC can be either positive or negative voltages with one of the voltages more positive or more negative than the other. Preferably, the select voltage for a read operation comprises the first read voltage VR1′ applied to the selected first conductive trace 1′ and the second read voltage VR2′ applied to the selected second conductive trace 2′. It is preferable, but not necessary, that the first read voltage VR1′ is approximately equal in magnitude and opposite in polarity to second read voltage VR2′. In
Preferably, the non-select voltages VNR and VNC are equal to each other so that no current flows through memory elements 10 that have the non-select voltages VNR and VNC applied across their respective first and second conductive traces 1 and 2. The non-select voltages VNR and VNC can be generated by the same voltage source or by different voltage sources. As an example, for a very large array 100, the non-select voltages VNR and VNC can be generated by separate voltage sources. If separate voltage sources are used, then it is desirable for the voltages supplied be equal voltages (e.g., VNR=VNC) to eliminate half-select current flow through unselected memory elements 10. The non-select voltages VNR and VNC can be the same for read and write operations. Preferably, the voltage potentials for the non-select voltages VNR and VNC are approximately half-way between the select voltages VSR and VSC for read and write operations, such that VNR=VNC=½(|VSR|−|VSC|). Alternatively, VNR=VNC=½(|VSC|−|VSR|). The non-select voltages VNR and VNC can be positive or negative voltage potentials. As one example, for a read operation, the non-select voltages are VNR=VNC=½(|VR1′|−|VR2′|). As a second example, for a write operation, the non-select voltages are VNR=VNC=½(|VW1′|−|VW2′|). TABLE 1 and TABLE 2 below list examples of the non-select voltages VNR and VNC for read and write operations respectively, where VNR=VNC=½(|VSR|−|VSC|). The read and write voltages can be uni-polar or bi-polar. Furthermore, the read and write voltages can be applied as voltage pulses.
One skilled in the art will appreciate that the non-select voltages VNR and VNC may not be exactly equal to each other due to process variations, voltage drops due to variations in the as-routed length of interconnect structures, just to name a few. As a result, when VNR and VNC are not exactly equal to each other, (e.g., VNR=VNC) there will be some current flow through unselected memory elements 10.
Write Operation Select VoltagesAs was described above, the appropriate select voltages can be applied to the selected first and second conductive traces 1′ and 2′ during a read or a write operation. The select voltages VSR and VSC used for write operations can be generated in a variety of ways. As one example, VSR can be a positive or negative voltage and VSC can be approximately at a ground potential, or VSC can be a positive or negative voltage and VSR can be approximately at a ground potential. As another example, both VSR and VSC can be either positive or negative voltages with one of the voltages more positive or more negative than the other. Preferably, the select voltage for the write operation comprises the first write voltage VW1′ applied to the selected first conductive trace 1′ and the second write voltage VW2′ applied to the selected second conductive trace 2′. It is preferable, but not necessary, that the first write and second write voltages VW1′ and VW2′ be approximately equal in magnitude but opposite in polarity to each other. In
In
The memory element 10 is electrically in series with the first and second terminals 11 and 12. The configuration depicted in
One method of creating memory elements 10 that store data as a plurality of distinct resistive states is described in “Memory Using Mixed Valence Conductive Oxides,” U.S. application Ser. No. 11/095,026, filed Mar. 30, 2005, which is incorporated herein by reference in its entirety and for all purposes. The application describes a two terminal memory element that changes conductivity when exposed to an appropriate voltage drop across the two terminals. The memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide. A voltage drop across the electrolytic tunnel barrier causes an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier. When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen perovskites-PCMO and lanthanum-nickel-oxygen perovskites-LNO) change valence, their conductivity changes. Additionally, oxygen accumulation in certain electrolytic tunnel barriers (e.g., yttrium stabilized zirconia—YSZ) can also change conductivity. If a portion of the mixed valence conductive oxide near the electrolytic tunnel barrier becomes less conductive, the tunnel barrier width effectively increases. If the electrolytic tunnel barrier becomes less conductive, the tunnel barrier height effectively increases. Both mechanisms are reversible if the excess oxygen from the electrolytic tunnel barrier flows back into the mixed valence conductive oxide. A memory can be designed to exploit tunnel barrier height modification, tunnel barrier width modification, or both. One skilled in the art will recognize that some aspects of the present invention are not limited to a particular choice of memory elements.
In
In
In the embodiments depicted in
Furthermore, the embodiments depicted in
In
The application of the read voltage VR causes the total and leakage currents (IT, IL) to flow. The data unit 1130 combines the total current IT, the leakage current IL, and a reference signal RSIG to generate a data signal RDATA that is indicative of the value of stored data in the selected memory element 10′. For example, if the selected memory element 10′ is in the first resistive state R0 (i.e., high resistance), such that the read current IR is low, then RDATA will have a value indicative of the stored data being approximately a logic “0”. Conversely, if the selected memory element 10′ is in the second resistive state R1 (i.e., low resistance), such that the read current IR is high, then RDATA will have a value indicative of the stored data being approximately logic a “1”. Communication and control between the control unit 105 and the data unit 1130 can be effectuated by at least one signal 1109. One skilled in the art will appreciate that other units in the apparatus 150 may also communicate with and/or control operation of the data unit 1130. The reference signal RSIG can be generated by a reference generator 1140. The reference signal RSIG can be a voltage or a current. The reference generator 1140 can be in communication with and/or controlled by the address unit 101 and/or the control unit 105 as indicated by the dashed lines 1117, and 1111 respectively, or the reference generator 1140 can be part of the array 100 as described in “Two terminal memory array having reference cells”, U.S. application Ser. No. 10/895,218, filed on Jul. 20, 2004, which is incorporated herein by reference in its entirety and for all purposes, or can exist as memory elements positioned outside of the array 100.
Turning to
In
It may be desirable to perform the adding, subtracting, and comparing functions on voltages rather than currents. Accordingly, the leakage current IL, the total current IT, and optionally the reference signal RSIG may be processed as voltages by using an I/V converter to convert signals in the current domain to signals in the voltage domain or by sensing the voltages directly. Therefore, in
Optionally, the value of RDATA can be stored for later use by the apparatus 150 or by another system in communication with the apparatus 150. In
In
Referring to
Turning to
However, if RDATA≠DIN, then the write operation can be consummated, that is, DIN overwrites the current value of the stored data. Consequently, the value of DIN is written to the selected memory element 10′ by applying the appropriate write voltage VW across the selected first and second conductive traces 1′ and 2′. As was described above, the write voltage VW can be the combination of the first and second write voltages VW1′ and VW2′. For example, the address unit 101 can receive the write data DIN as an input and the value of the write data DIN can be used by the address unit 101 to determine the polarity and/or magnitude of the write voltage VW to be applied across the selected first and second conductive traces 1′ and 2′. For example, the write voltages can be +VW1′ and −VW2′ to write a logic “0” and −VW1′ and +VW2′ to write a logic “1”. One skilled in the art will appreciate that the write data DIN need not be coupled with the address unit 101 and that a signal from another unit in the apparatus 150 (e.g., the control unit 105) can be used to communicate the value of the write data DIN to the address unit 101.
During a write operation, before write data DIN is written to the selected memory element 10′, the pre-reading operation may be initiated to pre-read the stored data in the selected memory element 10′. Therefore, the select voltage applied across the selected first and second conductive traces 1′ and 2′ is initially the read voltage VR as was described above (e.g., VR1′ and VR2′). The data unit 1130 combines the write data DIN, the total current IT, the leakage current IL, and optionally the reference signal RSIG to generate the data signal RDATA as was described above in reference to
A signal Result can be generated based on the comparison between DIN and RDATA. A variety of means can be used to generate the signal Result, including but not limited to analog circuitry, digital circuitry, or a combination of analog and digital circuitry. Depending on the value of the signal Result, the write operation is either consummated or aborted. In
In
On the other hand, in row 2, RDATA=0 and DIN=1, and in row 3, RDATA=1 and DIN=0. Therefore, in rows 2 and 3 where RDATA≠DIN, Result=1 and the write operation is consummated because the stored data and the data to be written are different from each other (i.e., they are not redundant). Consequently, the stored data is overwritten with the value of DIN by applying the appropriate write voltages (VW1′, VW2′) across the selected conductive traces (1′, 2′).
Consummating the Write OperationIn
Initially, the select voltages VSR and VSC are read voltages so that the stored data in the selected memory element 10′ can be read to determine whether or not to abort or consummate the writer operation. A maximum positive range and a maximum negative range for the select voltages are denoted by the dashed lines “+” and “−” for VSR and VSC respectively. The write voltages can be applied at or near their positive and negative maximums; however, the read voltages are applied below the positive and negative maximums to prevent overwriting the stored data during the pre-reading. Accordingly, at this stage of the write operation, stored data in the selected memory element 10′ is being pre-read to determine if RDATA≠DIN. A low-to-high transition on Result can be used to indicate that RDATA≠DIN. The low-to-high transition on Result causes the select voltages VSR and VSC to change (i.e., increase in magnitude) from the lower magnitude read voltages to the higher magnitude write voltages so that the stored data is overwritten by the write data DIN. The polarities of the write voltages will depend on the value of the write data DIN. For example, if the write data DIN is a logic “0” and RDATA is a logic “1”, then the polarities of the select voltages can be +VSR and −VSC to overwrite the logic “1” with the logic “0”. Conversely, if the write data DIN is a logic “1” and RDATA is a logic “0”, then the polarities of the select voltages can be −VSR and +VSC to overwrite the logic “0” with the logic “1”. In
In
Write operations to the array 100 can be accomplished by applying the select voltages VSR and VSC at a write voltage magnitude to the selected first and second conductive traces 1′ and 2′ selected by the ADDR received by the address unit 101 such that the write voltage is applied across the terminals 11 and 12 of the selected memory element 10′. Therefore, the aforementioned pre-read operation is not necessary for write operations to the array 100 and may optionally be used, particularly when some of the aforementioned advantages to pre-reading are necessary for a specific application.
Equalizing Charge on InputsIn the comparators depicted in
In
As another example, in
In
For a read operation to a selected memory element 10′, the row voltage switch 2255 selects one of the read voltages (+VR1 or −VR1) and outputs the selected voltage as the row select voltage VSR. The row select voltage VSR is an input to the row decoder 2251. Based on the row address 2203, the row decoder 2251 applies the row select voltage VSR to the selected first conductive trace 1′ in the appropriate row in the array 100. Similarly, the column voltage switch 2257 selects one of the read voltages (+VR2 or −VR2) and outputs the selected voltage as the column select voltage VSC. The column select voltage VSC is an input to the column decoder 2253. Based on the column address 2205, the column decoder 2253 applies the column select voltage VSC to the selected second conductive trace 2′ in the appropriate column in the array 100. As a result, the memory element 10 positioned at the intersection of the selected first and second conductive traces (1′, 2′) becomes the selected memory element 10′ for the read operation.
Similarly, for a write operation to a selected memory element 10′, the row voltage switch 2255 selects one of the write voltages (+VW1 or −VW1) and outputs the selected write voltage to the row decoder 2251 as the row select voltage VSR. Based on the row address 2203, the row decoder 2251 applies the row select voltage VSR to the selected first conductive trace 1′. Furthermore, the column voltage switch 2257 selects one of the write voltages (+VW2 or −VW2) and outputs the selected write voltage to the column decoder 2253 as the column select voltage VSC. Based on the column address 2205, the column decoder 2253 applies the column select voltage VSC to the selected second conductive trace 2′.
The non-select voltages VNR and VNC for the rows and columns can be connected with their respective switches 2255 and 2257. The switches 2255 and 2257 pass those voltages through to their respective decoders 2251 and 2253 as depicted in
Turning now to
In
Optionally, a signal DIR can be used to select a polarity for the read voltages during a valid read operation. For example, when DIR=0, the row voltage switch 2255 selects −VR1 for the row select voltage VSR and the column voltage switch 2257 selects +VR2 for the column select voltage VSC. On the other hand, when DIR=1, the row voltage switch 2255 selects +VR1 for the row select voltage VSR and the column voltage switch 2257 selects −VR2 for the column select voltage VSC. The advantages of alternating read voltage polarity will be discussed in greater detail below.
Address DecodingThe address unit 101 receives and decodes the address ADDR from the address bus 125 and applies the appropriate select voltages and non-select voltages to the conductive traces 1 and 2 in the array 100. Referring again to
Turning to
A truth table in
Therefore, in the truth table in
In
A truth table in
Therefore, in the truth table in
Accordingly, with the select voltages VSR and VSC applied to the selected first and second conductive traces 1′ and 2′ and the non-select voltages VNR and VNC applied to unselected traces 1 and 2, the memory element 10′ in row r2 and column c2 is uniquely selected for a read or a write operation. In a similar manner, the other memory elements 10 in the array 100 can be selected for a read or a write operation by providing appropriate row and column addresses 2203 and 2205.
Sensing Total and Leakage CurrentsAfter the select voltages VSR and VSC have been applied across the selected conductive traces 1′ and 2′, the total current IT and the leakage current IL are sensed by the sense unit 103. Referring again to
One means for sensing the total current IT and/or the leakage current IL is to monitor the current flowing through the power source that supplies the select voltages VSR and VSC and non-select voltages VNR and VNC. The following examples describe how monitoring current flow can be used to sense IT and/or IL. As a first example, in
In that the row and column orientation is arbitrary, the total current IT flowing through the selected second conductive trace 2′ can be sensed by monitoring current flow through a power source and the leakage current IL flowing through the unselected first conductive traces 1 can be sensed by monitoring current flow through another power source.
Therefore, as a second example, in
As was described above in reference to
One advantage to toggling DIR is that the polarity of the read voltages applied to selected memory cells 10′ is not always of the same polarity. Alternating read voltage polarity during a pre-read can reduce or eliminate data corruption caused by read disturbs in certain types of memory elements 10. A read disturb is caused by multiple read operations to a memory element 10 using a read voltage of unchanging polarity (e.g., +VR1 and −VR2). After several thousand or more read operations to the same memory element 10, the resistive state of the memory element 10 can be slowly degraded such that an accurate reading of the resistive state is not possible.
For example, if the memory element 10 is in the first resistive state of R0=1 MΩ, then after one-million read operations to that memory element 10 using the same read voltage (e.g., +VR1 and −VR2), the read disturb may result in a gradual degradation in R0 from 1 MΩ to 0.8 MΩ. Consequently, during subsequent read operations to the same memory element 10, it may not be possible to accurately determine whether or not the stored data in the memory element 10 is a logic “0” or a logic “1”. By alternating read voltage polarity, the average read disturb over time is approximately zero because approximately fifty-percent of the read operations apply read voltages of +VR1 and −VR2 and approximately fifty-percent of the read operations apply read voltages of −VR1 and +VR2.
Although the above example illustrates the toggling of DIR in conjunction with a read operation, one skilled in the art will appreciate that alternating read voltages can be accomplished using signals other than DIR or using other signals in conjunction with DIR. For example, in that pre-reading can occur for a read operation or a write operation (i.e., to prevent the writing of redundant data), the pre-read signal PR can be used to effectuate the toggling of DIR. Moreover, for write operation where WE=1 and RE=0, the PR signal can be used to initiate a pre-read of the selected memory element 10′ to determine whether or not to abort or consummate the write operation. The pre-read signal PR can also initiate the toggling of DIR so that pre-reads during a write operation use alternating read voltages for the reasons set forth above.
Reference is now made to
The signals that represent the leakage current IL and the total current IT can be sensed in two-cycles. During both cycles, the currents IL and IT are sensed flowing through the same selected conductive trace (i.e., 1′ or 2′). Each of the currents IL and IT can be stored after being sensed so that the leakage current IL and the total current IT can be compared to each other. Preferably, the currents IL and IT are converted to voltages and then stored. Subsequently, a comparator can be used to compare a voltage equivalent of IL with a voltage equivalent of IT. For example, the comparator can subtract the voltage equivalent of IL from voltage equivalent of IT to generate a signal indicative of the read current IR and that signal can be compared with RSIG to generate the data signal RDATA. As another example, as was described above, a property of a device (e.g., logic threshold voltage or a trip point of a logic gate) combined with a signal can be used to generate the data signal RDATA.
First Cycle Current SensingTurning to
In the embodiment depicted in
Turning now to
In
Reference is now made to
Similarly, during the second cycle, the signal PR2 goes active (e.g., is a logic 1) turning on FET 2813 and the signal PR1 goes inactive (e.g., is a logic 0) turning off FET 2811 thereby preserving charge in the capacitor 2815 and the voltage applied to the first terminal 2802. Therefore, when the FET 2813 is on, the voltage V2 charges a capacitor 2817 that is connected with an output terminal of the FET 2813. The signal PR2 is held active long enough for capacitor 2817 to charge to a level of the voltage V2. Accordingly, a voltage equivalent to the total current IT is applied to a second terminal 2804 of the operation block 2805.
The operation block 2805 operates on voltage equivalents of the total current IT and leakage current IL, and optionally, other signals (e.g., RSIG), to generate the data signal RDATA on an output node 2806. Generation of the data signal RDATA by the operation block 2805 will be application specific and will depend on which signals in addition to those on the terminals 2802 and 2804 are coupled with the operation block 2805. As one example, the operation block 2805 can subtract the voltages at first and second the terminals 2802 and 2804 from each other to generate the data signal RDATA. The output signal 706 can be connected with an input terminal of the storage unit 1150 as was described above.
Preferably, before the first cycle begins, a signal DIS is asserted to discharge the capacitors 2815 and 2817 to an approximately equal potential so that voltages on the first and second terminals 2802 and 2804 are equalized (e.g., are approximately 0 Volts or approximately equal voltages). The DIS signal is connected to the gate terminals of FET 2819 and FET 2821. The input terminals of FET 2819 and FET 2821 are connected to a ground potential and the output terminals of FET 2819 and FET 2821 are connected with the first and second terminals 2802 and 2804 of the operation block 2805, respectively. Therefore, when the signal DIS goes active (e.g., is a logic 1), the capacitors 2815 and 2817 discharge prior to the start of the first cycle. Additionally, the nodes 2802 and 2804 can also be equalized by an FET while the DIS signal is active, to ensure that these two nodes are at the same value before the beginning of the two read cycles.
Optionally, the operation block 2805 can receive the reference signal RSIG and the voltages at the first and second terminals 2802 and 2804 can be used in conjunction with the reference signal RSIG to derive the data signal RDATA. As one example, the voltages at the first and second terminals 2802 and 2804 can be subtracted from each other to generate a difference signal that is compared with the reference signal RSIG to generate the data signal RDATA. As another example, the voltage at the first terminal 2802 and the reference signal RSIG can be added to each other and the sum compared with the voltage at the second terminal to generate the data signal RDATA. Preferably, the signals received by the operation block 2805 are in the voltage domain.
Those skilled in the art can appreciate that the apparatus 150 may include arrays 100 that are configured into one or more memory banks. A memory bank can provide read/write access to one bit of data or multiple bits of data. If one bit of data is accessed, the memory bank can be referred to as a bit block. Turning now to
An exemplary means for sensing the currents IT and IL is to use a current mirror circuit. Referring back to
Turning now to
Column voltage switch 2257 selects the read voltage −VR2 and the column decoder 2253 applies the read voltage −VR2 to the selected second conductive trace 2′. The column decoder 2253 also applies the non-select voltage VNC to the unselected second conductive traces 2. The column current mirror 2263 is electrically in series with the column voltage switch 2257 and the column decoder 2253 so that the current flowing from the power source 2507 (see
The reference signal RSIG can be generated by a reference generator 1140 that outputs the reference signal RSIG as a current or a voltage. One means of generating the reference signal RSIG is to use a constant current source or a constant voltage source. If RSIG is a current, then an I/V converter (e.g., 1401 in
Alternatively, in
In
Programming the desired value for the reference resistance RR can be accomplished by applying an appropriate programming voltage across the first and second conductive traces 1r and 2r of the reference memory element 10r. A magnitude and polarity of the programming voltage can be selected to set the desired value for the reference resistance RR. For example, the programming voltage can be two separate voltages VPX and VPY. Programming voltages VPX and VPY can be internally generated in the apparatus 150 or they can be supplied by an external voltage source connected with the apparatus 150 by input pads, for example. Moreover, the programming of the reference resistance RR can occur during a manufacturing process for the apparatus 150 or a system that includes the apparatus 150. As one example, automatic test equipment (ATE) can be used to apply test vectors to the apparatus 150 and voltage sources coupled with the ATE can be used to supply the programming voltages VPX and VPY to pads on the apparatus 150 to program the desired value for the reference resistance RR. For example, when the apparatus 150 is in a test mode or a programming mode, the program signal PGM can be active high (i.e., PGM=1) and based on the truth table in
A current mirror can also be used to sense the reference current ISIG and to generate the reference signal RSIG. For example, in
A value for the reference resistance RR for the reference memory element 10r can be selected to fall between the values for the first resistive state R0 and the second resistance state R1. As a first example, if R0≈1 MΩ and R1≈100 kΩ, then the reference resistance RR can be selected to be about half-way in between the values for R0 and R1 (e.g., RR=550 kΩ). As a second example, the reference resistance RR can be selected to be approximately half-way on a logarithmic scale such that RR≈300 kΩ. As a third example, another method for selecting the value for the reference resistance RR can be based on selecting desired magnitudes for the read current IR and the half-select currents IH. For example, in
Alternatively,
The sensing of the total current IT and the leakage current IL can be accomplished using hardware, software, or a combination of hardware and software. Software for sensing the currents can be implemented in a computer readable media including but not limited to RAM, ROM, optical disc, magnetic disc, magnetic tape, firmware, communicated over a network electrically, optically, or wirelessly (e.g., a LAN), volatile memory, and non-volatile memory, just to name a few. The software can be code running on a computer such as a PC or a microprocessor, for example.
Referring now to
In
The method 3300 may optionally include an adding step as depicted in
The method 3300 may optionally include a subtracting step as depicted in
Turning now to
At a stage 3411, a second select voltage VSR is applied to the selected first conductive trace 1′ during the second cycle. Furthermore, during the second cycle, the non-select voltage (e.g., VNR and VNC) are applied to the un-selected first and second conductive traces 1 and 2. Therefore, during the second cycle, the second select voltage VSR is applied only to one of the plurality of first conductive traces (i.e., selected conductive trace 1′). A remaining portion of the plurality of first conductive traces 1 are un-selected traces, and the non-select voltage VNR is applied to those un-selected traces. Also during the second cycle, the first select voltage VSC is applied only to the one or more selected second conductive traces 2′. A remaining portion of the plurality of second conductive traces 2 are un-selected traces and the non-select voltage VNC is applied to those un-selected second conductive traces 2 (see
In
Referring now to
Reference is now made to
Although several embodiments of an apparatus and a method of the present invention have been disclosed and illustrated herein, the invention is not limited to the specific forms or arrangements of parts so described and illustrated. The invention is only limited by the claims.
Claims
1. An apparatus for sensing current in a two-terminal memory array, comprising:
- an array including a plurality of first conductive traces and a plurality of second conductive traces;
- an address unit operative to receive an address, to select one of the plurality of second conductive traces during a first cycle, to apply a first select voltage to the selected second conductive trace and to apply a non-select voltage potential to un-selected traces,
- to select one of the plurality of first conductive traces during a second cycle, to apply a second select voltage to the selected first conductive trace; and
- a sense unit operative to sense a leakage current flowing through the selected second conductive trace during the first cycle and to sense a total current flowing through the selected second conductive trace during the second cycle.
2. The apparatus as set forth in claim 1 and further comprising:
- a first terminal in communication with the selected first conductive trace and a second terminal in communication with the selected second conductive trace; and
- a memory element electrically in series with the first and second terminals and operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the first and second terminals, the memory element including a conductive metal oxide material.
3. The apparatus as set forth in claim 2, wherein the conductive metal oxide material is a perovskite.
4. The apparatus as set forth in claim 3, wherein the perovskite is PCMO or LNO.
5. The apparatus as set forth in claim 2, wherein the memory element includes a layer of an electronic insulator material in contact with and electrically in series with the conductive metal oxide material.
6. The apparatus as set forth in claim 2, wherein the data is non- volatile in the absence of a voltage applied across the first and second terminals.
7. The apparatus as set forth in claim 1 and further comprising:
- a current mirror circuit electrically in series with the selected second conductive trace and operative to output a mirrored current that is approximately equal in magnitude to the leakage current during the first cycle and is approximately equal in magnitude to the total current during the second cycle.
8. The apparatus as set forth in claim 7 and further comprising:
- a current-to-voltage converter coupled with the sense unit and operative to convert current flowing through the selected second conductive trace to an equivalent voltage during the first and second cycles, and
- wherein during the first cycle the equivalent voltage is indicative of a magnitude of the leakage current and during the second cycle the equivalent voltage is indicative of a magnitude of the total current.
9. The apparatus as set forth in claim 7 and further comprising:
- a storage circuit coupled with the current-to-voltage converter and operative to store the equivalent voltage in a first storage element during the first cycle and operative to store the equivalent voltage in a second storage element during the second cycle.
10. The apparatus as set forth in claim 9, wherein the first storage element comprises a first capacitor and the second storage element comprises a second capacitor.
11. The apparatus as set forth in claim 1 and further comprising:
- a compare unit operative to combine the leakage current the total current, and a reference signal to generate a data signal indicative of stored data.
12. (canceled)
13. (canceled)
14. The apparatus as set forth in claim 11, wherein receiving the address occurs during a read operation to the array, the select voltage comprises a read voltage applied across the selected first and second conductive traces, the read voltage generates a read current that is a component of the total current, and wherein a magnitude of the read current is indicative of the stored data.
15. The apparatus as set forth in claim 14, wherein the read voltage is non-destructive to the stored data.
16. The apparatus as set forth in claim 11, wherein the compare unit further comprises:
- an add unit operative to add the reference signal to the leakage current and generate a sum signal: and
- a comparator operative to compare the sum signal with the total current and generate the data signal.
17. The apparatus as set forth in claim 11, wherein the compare unit further comprises:
- a subtract unit operative to subtract the leakage current from the total current and generate a difference signal; and
- a comparator operative to compare the difference signal with the reference signal and generate the data signal.
18. The apparatus as set forth in claim 11, wherein receiving the address occurs during a write operation with write data to be written to the address, the select voltage initially comprises a read voltage applied across the selected first and second conductive traces, and
- the compare unit is operative to compare the data signal with the write data and to generate a result signal, and based on a value of the result signal, either aborting the write operation or consummating the write operation.
19. The apparatus as set forth in claim 18, wherein aborting the write operation occurs when the value of the result signal is indicative of the stored data at the address being approximately equal to the write data.
20. The apparatus as set forth in claim 19, wherein the aborting results in the select voltage decreasing to a magnitude that is lower than a magnitude of the read voltage such that the stored data is not overwritten by the write data.
21. The apparatus as set forth in claim 18, wherein consummating the write operation occurs when the value of the result signal is indicative of the stored data at the address not being approximately equal to the write data.
22. The apparatus as set forth in claim 21, wherein the consummating results in the select voltage increasing from the read voltage to a write voltage applied across the selected first and second conductive traces and the write voltage is operative to overwrite the stored data with the write data.
23. The apparatus as set forth in claim 22, wherein a magnitude of the write voltage is greater than a magnitude of the read voltage.
24. (canceled)
25. (canceled)
26. The apparatus as set forth in claim 1, wherein the array comprises a two-terminal cross-point array.
27. The apparatus as set forth in claim 1, wherein the non-select voltage potential is approximately half-way between the first select voltage and the second select voltage.
28. An apparatus for sensing current in a two-terminal memory array, comprising:
- a plurality of bit block arrays, each bit block array including a plurality of first conductive traces and a plurality of second conductive traces, an address unit operative to receive an address, to select at least one of the plurality of second conductive traces during a first cycle, to apply a first select voltage to the selected second conductive traces and to apply a non-select voltage potential to un- selected first and second conductive traces during the first cycle, to select one of the plurality of first conductive traces during a second cycle, to apply a second select voltage to the selected first conductive trace during; and a sense unit operative to sense a leakage current flowing through the selected second conductive traces during the first cycle and to sense a total current flowing through the selected second conductive traces during the second cycle.
29. The apparatus as set forth in claim 28, wherein each bit block array comprises a two-terminal cross-point army.
30. A method of sensing current in a two-terminal memory, comprising:
- providing an army including a plurality of first conductive traces and a plurality of second conductive traces;
- receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces;
- applying a first select voltage to one or more selected second conductive traces during a first cycle and during a second cycle;
- applying a non-select voltage potential to the plurality of first conductive traces and unselected second conductive traces during the first cycle;
- sensing one or more leakage currents flowing through the one or more selected second conductive traces during the first cycle;
- applying a second select voltage to the selected first conductive trace during the second cycle while applying the non-select voltage potential to unselected first and second conductive traces: and
- sensing one or more total currents flowing through the one or more selected second conductive traces during the second cycle.
31. The method as set forth in claim 30, wherein the non-select voltage potential is approximately half-way between the first select voltage and the second select voltage.
32. The method as set forth in claim 30, wherein sensing a selected one or both of the one or more total currents or the one or more leakage currents is accomplished by sensing a voltage.
33. The method as set forth in claim 30, wherein applying the first select voltage comprises applying a first voltage pulse to the one or more selected second conductive traces and wherein applying the second select voltage comprises applying a second voltage pulse to the selected first conductive trace.
34. The method as set forth in claim 30 and further comprising:
- storing one or more first values indicative of each of the one or more leakage currents in a first circuit during the first cycle; and
- storing one or more second values indicative of each of the one or more total currents in a second circuit during the second cycle.
35. The method as set forth in claim 34 and further comprising:
- combining the one or more first values, the one or more second values, and at least one reference signal to generate one or more data signals indicative of stored data.
36. The method as set forth in claim 35, wherein the combining occurs in a voltage domain.
37. The method as set forth in claim 35, wherein the stored data is non-volatile.
38. The method as set forth In claim 35, wherein the address is a read address and receiving the address occurs during a read operation to the array, the first and second select voltages comprise a read voltage applied across the one or more selected second conductive traces and the selected first conductive trace during the second cycle, the read voltage generates one or more read currents that are a component of the one or more total currents, and wherein a magnitude of each of the one or more read currents is indicative of the stored data.
39. The method as set forth in claim 38, wherein applying the read voltage is non-destructive to the stored data.
40. The method as set forth in claim 38, wherein the combining further comprises:
- adding the at least one reference signal to each of the one or more first values to obtain one or more sum signals; and
- comparing the one or more sum signals with each of the one or more second values to generate the one or more data signals.
41. The method as set forth in claim 38, wherein the combining further comprises:
- subtracting each of the one or more first values from each of the one or more second values to generate one or more difference signals; and
- comparing the one or more difference signals with the at least one reference signal to generate the one or more data signals.
42. The method as set forth in claim 35, wherein the address is a write address and receiving the address occurs during a read-before-write operation to the array.
43. The method as set forth in claim 35 and further comprising:
- combining at least one reference signal, the one or more first values, the one or more second values, and write data to generate one or more result signals, wherein the address is a write address and receiving the address occurs during a write operation, the first and second select voltages initially comprise a read voltage applied across the selected first conductive trace and the one or more selected second conductive traces during the second cycle, and based on each of the one or more result signals, either aborting or consummating the write operation for each of the one or more selected second conductive traces.
44. The method as set forth in claim 43, wherein the one or more result signals are indicative of write data that is not approximately equal to the stored data at the address and the consummating further comprises changing the read voltage to a write voltage applied across the selected first conductive trace and only those selected second conductive traces for which the result signal is indicative of write data that is not approximately equal to the stored data, the write voltage operative to overwrite the stored data with the write data.
45. The method as set forth in claim 44, wherein a magnitude of the write voltage is greater than a magnitude of the read voltage.
46. The method as set forth in claim 43, wherein the one or more result signals are indicative of stored data that is approximately equal to the write data to be written to the address, the aborting further comprises terminating the write operation by reducing a magnitude of the first and second select voltages.
47. The method as set forth in claim 43, wherein the combining comprises adding the one or more reference signals to the one or more first values to obtain one or more sum signals, comparing the one or more sum signals with the one or more second values to generate one or more data signals, and comparing the write data to the one or more data signals to generate the one or more result signals.
48. The method as set forth in claim 43, wherein the combining comprises subtracting the one or more first values from the one or more second values to obtain one or more difference signals, comparing the one or more difference signals with the one or more reference signals to generate one or more data signals, and comparing the write data with the one or more data signals to generate the one or more result signals.
49. The method as set forth in claim 35 and further comprising:
- providing one or more reference memory elements, each reference memory element electrically in series with a first terminal and a second terminal;
- applying a reference voltage across the first and second terminals of the one or more reference memory elements so that one or more reference currents flow through the one or more reference memory elements; and
- sensing the one or more reference currents to generate the one or more reference signals, wherein the one or more reference signals are indicative of stored reference data in the one or more reference memory elements.
50. The method as set forth in claim 49 and further comprising: programming the one or more reference memory elements so that the stored reference data is indicative of a reference resistive state that is intermediate to a plurality of conductivity profiles.
51. The method as set forth in claim 50, wherein the programming further comprises applying a programming voltage across the first terminal and the second terminal of the one or more reference memory elements.
52. The method as set forth in claim 51, wherein a magnitude and a polarity of the programming voltage determines the reference resistive state.
53. The method as set forth in claim 30, wherein the array comprises a two-terminal cross-point array.
54. A method of sensing current in a two-terminal memory, comprising:
- providing a plurality of bit block arrays, each bit block array including a plurality of first conductive traces and a plurality of second conductive traces;
- receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces;
- applying a first select voltage to one or more selected second conductive traces during a first cycle and during a second cycle;
- applying a non-select voltage to the plurality of first conductive traces and unselected second conductive traces during the first cycle;
- sensing one or more leakage currents flowing through the one or more selected second conductive traces during the first cycle;
- applying a second select voltage to the selected first conductive trace during the second cycle while applying the non-select voltage to unselected first and second conductive traces; and
- sensing one or more total currents flowing through the one or more selected second conductive traces during the second cycle.
55. The method as set forth in claim 54, wherein each bit block array comprises a two-terminal cross-point array.
Type: Application
Filed: Oct 19, 2006
Publication Date: Apr 24, 2008
Inventors: Darrell Rinerson (Cupertino, CA), Christophe Chevallier (Palo Alto, CA), Chang Hua Siau (San Jose, CA)
Application Number: 11/583,676
International Classification: G11C 11/00 (20060101); G11C 7/02 (20060101);