Semiconductors Patents (Class 365/208)
  • Patent number: 10665595
    Abstract: In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Hsin Chiu, Meng-Han Lin, Wei Cheng Wu
  • Patent number: 10606743
    Abstract: The present disclosure includes apparatuses and methods related to data movement operations in non-volatile memory. An example apparatus can comprise an array of non-volatile memory cells including a plurality of sections each with a plurality of rows and a controller configured to move data stored in a first portion of the array from a first row of a first section to a second row of the first section and move data stored in a second portion of the array from a second section to the first to create an open row in the second section in response to data from a particular number of portions of memory cells in the first section being moved within the first section.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James S. Rehmeyer, Timothy B. Cowles
  • Patent number: 10529392
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shuichi Tsukada
  • Patent number: 10460769
    Abstract: A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-pil Son
  • Patent number: 10176884
    Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 8, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Duk Ju Jeong
  • Patent number: 10163906
    Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 9552850
    Abstract: An embodiment relates to a sense amplifier driving device for stabilizing bit line precharge power when a post-overdriving operation is performed. The sense amplifier driving device includes a power driving unit configured to supply a first pull-up voltage and a pull-down voltage to a pull-up power line and a pull-down power line during a post-overdriving period and a driving signal generation unit configured to generate a pull-up driving signal and a pull-down driving signal activated during the post-overdriving period in order to control the driving of the power driving unit. The driving signal generation unit controls a point of time at which the pull-down driving signal shifts in response to a post-overdriving enable signal.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 24, 2017
    Assignee: SK HYNIX INC.
    Inventor: Young Geun Choi
  • Patent number: 9368192
    Abstract: A semiconductor device includes a voltage supply unit suitable for providing a first voltage as a source voltage during a standby mode, and a second voltage as the source voltage during an active mode, and a precharge unit suitable for precharging a pair of input/output lines with the source voltage during the standby mode and the active mode.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: June 14, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung-Ho Kim
  • Patent number: 9240226
    Abstract: A memory includes a first and second cell storing first data and second or reference-data. A first and second bit-lines connected to the first and second cells respectively correspond to a first and second sense-nodes. A first transfer-gate is inserted/connected between the first bit-line and the first sense-node. A second transfer-gate is inserted/connected between the second bit-line and the second sense-node. A sense-amplifier is inserted or connected between the first and second sense-nodes. A preamplifier includes a first and second common-transistors. The first common-transistor applies a first power-supply voltage to either the first or the second sense-node according to the first and second data or according to the first and reference-data during a data-read-operation. The second common-transistor applies a second power-supply voltage to the other sense-node out of the first and second sense-nodes according to the first and second data or according to the first and reference data.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 9142284
    Abstract: A memory system includes first memory cells and second memory cells. Each of the first memory cells includes first and second pass gates including NMOS transistors. Each of the second memory cells include first and second pass gates including PMOS transistors. The first memory cells are pre-charged by one polarity of a voltage supply. The second memory cells are pre-charged by an opposite polarity of the voltage supply.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 22, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Winston Lee, Peter Lee
  • Patent number: 9105351
    Abstract: In a conventional DRAM, a decrease in the capacitance of a capacitor causes an error in reading data. A plurality of memory blocks MB is connected to one bit line BL_m. Each memory block MB includes a sub bit line SBL, a plurality of memory cells, and a precharge transistor. The drain of a transistor of the memory cell is connected one of the bit line BL_m and the sub bit line SBL, whereas a capacitor of the memory cell is connected to the other one of the bit line BL_m and the sub bit line SBL. The capacitance of the sub bit line SBL is sufficiently low; thus, a potential change due to electric charges of the capacitor of the memory cell can be amplified by an amplifier circuit AMP without an error and the amplified signal can be output to the bit line.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9087604
    Abstract: A pre-charging method applied in DRAM which includes steps of: enabling wordlines in an active array and an reference array; disabling the wordlines in the active array; equilibrating digital lines in the active array and the reference array to half of a power supply voltage; storing the half of the power supply voltage in reference cells of the reference array; disabling the wordlines in the reference array; pre-charging the digital lines in the active array and the reference array to the power supply voltage; and enabling the wordlines in the active array and the reference array at the same time.
    Type: Grant
    Filed: April 13, 2014
    Date of Patent: July 21, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Scott Derner, Charles Ingalls, Howard Kirsch, Tae Kim
  • Patent number: 9058171
    Abstract: A data processing method, a data processing system, and relevant devices are provided, which are used to reduce system power consumption. The method in embodiments of the present invention includes: performing sampling on an analog signal to obtain an analog sample value; performing analog-to-digital conversion on the analog sample value to obtain a digital signal; dividing bits forming the digital signal into at least two bit groups; and turning off output of bits in at least one bit group if a preset turnoff condition is satisfied. A data processing system and relevant devices are further provided.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: June 16, 2015
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yong Wang, Xiaoming Shi, Gang Li, Zhufa Shao
  • Patent number: 9053806
    Abstract: In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant current source for offset compensation is connected to the first or second node. Accordingly, the offset voltage of the sense amplifier can be compensated for with a simple configuration.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 9, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Kono
  • Patent number: 9030900
    Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 12, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sin-Hyun Jin, Sang-Jin Byeon
  • Patent number: 9013940
    Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Atul Katoch, Mayank Tayal, Cormac Michael O'Connell
  • Patent number: 9013933
    Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Michael E. Runas
  • Patent number: 9001596
    Abstract: A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data. The voltage generation unit is configured to compare a level of the bias voltage with a voltage level of a sensing node and drive the sensing node at voltage having a constant level based on a result of the comparison. The memory cell coupled with the sensing node and configured to receive the voltage having the constant level.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 7, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chul Hyun Park
  • Patent number: 9001588
    Abstract: A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui-Seung Kim, Ji-Sung Kim, SeEun O
  • Patent number: 9001562
    Abstract: A semiconductor memory device includes a memory array including a plurality of element blocks; the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 7, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kazuhisa Ukai
  • Patent number: 9003255
    Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics International N.V.
    Inventor: Nishu Kohli
  • Patent number: 9001556
    Abstract: A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Kobayashi, Takeshi Yamaguchi
  • Publication number: 20150085593
    Abstract: A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.
    Type: Application
    Filed: September 23, 2013
    Publication date: March 26, 2015
    Inventors: FUCHEN MU, Chen He, Yanzhuo Wang
  • Patent number: 8988960
    Abstract: A static random-access memory (SRAM) module includes a column select (RSEL) driver coupled to an input/output (I/O) circuit by an RSEL line. The I/O circuit is configured to read bit line signals from a bit cell within the SRAM module. During a read operation, the RSEL driver pulls the RSEL line to zero in order to cause p-type metal-oxide-semiconductors (PMOSs) within the I/O circuit to sample the bit line signals output by the bit cell. In response, an aggressor driver drives the RSEL line to a negative voltage, thereby reducing the resistance of the PMOSs within the I/O circuit.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: March 24, 2015
    Assignee: NVIDIA Corporation
    Inventors: Yongchang Huang, Jiping Ma, Demi Shen
  • Patent number: 8982636
    Abstract: A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-Yi Chou, Ming-Feng Zhou, Chung-Yi Li, Zong-Qi Zhou
  • Patent number: 8976582
    Abstract: A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Patent number: 8971142
    Abstract: A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 3, 2015
    Assignee: SK Hynix Inc.
    Inventor: Woong-Ju Jang
  • Patent number: 8964439
    Abstract: A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: February 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kyoichi Nagata
  • Patent number: 8964494
    Abstract: A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are connected to an end array with an open digit architecture such that each sense amplifier corresponds to a group of four digit lines. Two digit lines of the group connect to two open digit sense amplifiers and the other two digit lines connect to the corresponding folded digit sense amplifier. A repair method can be performed on memories including the end arrays with folded digit sense amplifiers. A row in a core array including a replaceable IO is activated and a row in an end array is activated. The repair cells in the end array can be sensed by the folded digit sense amplifiers to generate a replacement IO, which is selected rather than the replaceable IO.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Michael S. Lane, Michael A. Shore
  • Patent number: 8964496
    Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 8958255
    Abstract: A semiconductor storage apparatus according to the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of pairs of bit lines, a plurality of sense amplifiers, a pair of common data lines, a data-to-be-written output circuit configured to, in writing data, set voltages of the common data lines forming the pair, a column selection signal output unit configured to output a plurality of column selection signals, and a plurality of column selection gates, in which in writing the data, the column selection signal output unit selectively turns on one of the column selection gates by setting each of voltages of the column selection signals to one of a level of a higher-potential power supply voltage and a level of a lower-potential power supply voltage, before activating the sense amplifiers.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Takahashi, Masahiro Yoshida
  • Patent number: 8953364
    Abstract: Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual voltage rail noise can be compared to an expected amount of noise for analysis and validation of simulation models. Such assessment can be used to validate simulation models used to refine a design of an integrated circuit or as part of built-in self test.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 8947924
    Abstract: A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: February 3, 2015
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xi Li, Houpeng Chen, Zhitang Song, Daolin Cai
  • Patent number: 8941412
    Abstract: A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Robert H. Dennard
  • Publication number: 20150009771
    Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 8, 2015
    Inventor: Duk Su CHUN
  • Patent number: 8908458
    Abstract: A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 9, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Yong Seop Lee
  • Patent number: 8879303
    Abstract: In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: November 4, 2014
    Assignee: LSI Corporation
    Inventors: Kamal Chandwani, Vikash, Rahul Sahu
  • Patent number: 8873314
    Abstract: A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Publication number: 20140313834
    Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 23, 2014
    Applicant: Invensas Corporation
    Inventor: Invensas Corporation
  • Patent number: 8854909
    Abstract: A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Suk Min Kim
  • Publication number: 20140269131
    Abstract: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Inventors: Ravindraraj Ramaraju, George P. Hoekstra, Andrew C. Russell
  • Publication number: 20140247642
    Abstract: A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit (700) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.
    Type: Application
    Filed: October 25, 2013
    Publication date: September 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudhir Madhan, Hugh McAdams
  • Publication number: 20140241078
    Abstract: A sense amplifier circuit is divided into a plurality of sense amplifier groups. The plurality of sense amplifier groups are each further divided into a plurality of sense units. A sense amplifier control circuit is configured to sequentially select the plurality of sense amplifier groups according to a physical address, and to sequentially select the plurality of sense units included in a selected sense amplifier group. The sense amplifier control circuit is configured to, when there is a defect related to a selected sense unit in a selected first sense amplifier group, select, in place of the first sense amplifier group, a sense unit included in a second sense amplifier group selected following after the first sense amplifier group.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiromitsu Komai
  • Publication number: 20140241087
    Abstract: A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second end, and a third end. The first end is configured to receive a first supply voltage. The second end is coupled with a first terminal of the capacitive device and a first terminal of the first transistor. The third end is coupled with a second terminal of the capacitive device and a first terminal of the second transistor. A second terminal of the first transistor and a second terminal of the second transistor are coupled together and are configured to receive a first control signal. A third terminal of the first transistor and a third terminal of the second transistor are coupled together and are configured to receive a second supply voltage different from the first supply voltage.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20140241088
    Abstract: Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: PS4 LUXCO S.A.R.L.
    Inventor: Kazuhiko KAJIGAYA
  • Patent number: 8792293
    Abstract: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 29, 2014
    Assignee: LSI Corporation
    Inventors: Sahilpreet Singh, Disha Singh
  • Publication number: 20140198596
    Abstract: Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may also include: a floating circuit for floating the sense amplifier driving signal line in a set operating mode; and a controller connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line, for controlling a level of the sense amplifier driving signal line in the set operating mode.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 17, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Hun SEO, Chul-Sung PARK, Young-Dae LEE
  • Patent number: 8780650
    Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 15, 2014
    Assignee: Apple Inc.
    Inventors: Michael R. Seningen, Michael E. Runas
  • Patent number: 8767496
    Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David J. McElroy, Stephen L. Casper
  • Patent number: 8743639
    Abstract: A semiconductor memory device includes a switching unit coupled between a local sense amplifier and a bit line sense amplifier and configured to be turned on in response to a switching signal which is enabled in synchronization with an enable signal for enabling the local sense amplifier and disabled at a time point where a preset period passes after a first power for enabling the bit line sense amplifier is precharged.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: June 3, 2014
    Assignee: SK Hynix Inc.
    Inventors: Woong Ju Jang, Kyu Nam Lim