Resistive Patents (Class 365/148)
  • Patent number: 12040019
    Abstract: Methods for programming memory cells of a resistive memory device include applying a voltage pulse sequence to a memory cell to set a logic state of the memory cell. An initial set sequence of voltage pulses may be applied to the memory cell, followed by a reform voltage pulse having an amplitude greater than the amplitudes of the initial set sequence, and within ±5% of the amplitude of a voltage pulse used in an initial forming process. Additional voltage pulses having amplitudes that are less than the amplitude of the reform voltage pulse may be subsequently applied. By applying a reform voltage pulse in the middle of, or at the end of, a memory set sequence including multiple voltage pulses, a resistive memory device may have a larger memory window and improved data retention relative to resistive memory devices programmed using conventional programming methods.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fu-Chen Chang, Chu-Jie Huang, Nai-Chao Su, Kuo-Chi Tu, Wen-Ting Chu
  • Patent number: 12039174
    Abstract: Provided herein may be a memory controller and a method of operating the same. The method of operating a memory controller may include determining whether a reset request received from a host is valid, based on boot workload information related to a plurality of boot stages of the host, and performing a reset operation on a memory device depending on whether the reset request is valid.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: July 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Kyoung Ku Cho
  • Patent number: 12033697
    Abstract: A memory device includes a current source and a memory array. The current source is configured to provide a current to a first node. The memory array is coupled to the current source at the first node. The memory array includes memory cells. First terminals of the memory cells are coupled to the first node. Each of the memory cells has a first resistance in response to having a first data value, and has a second resistance in response to having a second data value. The second data value is N times the first data value. The second resistance is approximately one-Nth of the first resistance, for N being a positive integer larger than one. A method of operating a memory device is also disclosed herein.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: July 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Yen-Cheng Chiu, Win-San Khwa, Meng-Fan Chang
  • Patent number: 12026400
    Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyun Sub Kim, Ie Ryung Park, Dong Sop Lee, Sung Yeob Cho
  • Patent number: 12027206
    Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: July 2, 2024
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Brent Haukness, Gary Bronner
  • Patent number: 12027201
    Abstract: A column select signal cell circuit, a bit line sense circuit and a memory are disclosed. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: July 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sungsoo Chi, Jia Wang, Ying Wang, Shuyan Jin, Fengqin Zhang
  • Patent number: 12014776
    Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
  • Patent number: 12004435
    Abstract: A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 4, 2024
    Assignee: International Business Machines Corporation
    Inventors: Min Gyu Sung, Soon-Cheon Seo, Chanro Park
  • Patent number: 12002510
    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Ghetti, Andrea Martinelli, Efrem Bolandrina, Ferdinando Bedeschi, Paolo Fantini
  • Patent number: 11996149
    Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 28, 2024
    Inventors: Jason M. Brown, Vijayakrishna J. Vankayala
  • Patent number: 11988702
    Abstract: The present invention relates to a film quality inspection method and system for providing a stress evaluation scheme for inspection of film quality of a magnetic tunnel junction (MTJ) cell of spin-transfer torque magnetic random access memory (STT-MRAM), wherein a bipolar signal and a unipolar signal including a unipolar hole (positive polarity) and a unipolar electron (negative polarity) are simultaneously applied to the same MTJ cell, and then according to a result of a comparison of a cycling gap, the quality of a thin film having a thickness of about 1 nm may be inspected.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 21, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun Heub Song
  • Patent number: 11990183
    Abstract: A method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. The programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. A memory device and a system are also disclosed herein.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Meng-Sheng Chang
  • Patent number: 11978529
    Abstract: A memory circuit includes: a memory array unit including a plurality of memory cells-MG and a word line for connecting the plurality of memory cells-MG to each other and applying a drive voltage for driving the memory cells; a drive voltage control unit that generates a drive voltage in which a pre-pulse is set at a timing corresponding to the rising or falling of a voltage signal that changes by a predetermined voltage value in a stepwise manner, applies the drive voltage to a terminal of the word line, and performs control to variably set the time width or the peak value of the pre-pulse in the drive voltage based on address information designating the memory cell at an access destination received from the outside; and a sense amplifier unit that accesses the memory cell-MG designated by the address information.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: May 7, 2024
    Assignee: National University Corporation Shizuoka University
    Inventor: Toru Tanzawa
  • Patent number: 11978509
    Abstract: A memory device includes a plurality of resistive random access memory (RRAM) cells commonly connected between a bit line (BL) and a source line (SL). Each of the RRAM cells includes a resistor, a first transistor, and a second transistor coupled to each other in series, with the resistor connected to the BL and the second transistor connected to the SL. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage, the first threshold voltage being less than the second threshold voltage.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yih Wang
  • Patent number: 11972799
    Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: April 30, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Ping-Kun Wang, Chia-Hung Lin, Jun-Yao Huang
  • Patent number: 11972826
    Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Huei Lee, Pei-Chun Liao, Jian-Hong Lin, Dawei Heh, WenHsien Kuo
  • Patent number: 11960810
    Abstract: A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Lien-Hsiang Sung
  • Patent number: 11948631
    Abstract: A memory device includes a memory cell array including a plurality of memory cells, each of the plurality of memory cells having a switch element, and a data storage element connected to the switch element and containing a phis change material; and a memory controller for obtaining first read voltages from the plurality of memory cells, inputting a first write current to the plurality of memory cells, and then, obtaining second read voltages from the plurality of memory cells, wherein the memory controller compares the first read voltage of a first memory cell of the plurality of memory cells to the second read voltage of the first memory cell to determine a state of the first memory cell.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Hui Na, Mu Hui Park, Kwang Jin Lee, Yong Jun Lee
  • Patent number: 11948633
    Abstract: A resistive memory device includes: conductive layers and interlayer insulating layers, which are alternatively stacked; a vertical hole vertically penetrating the conductive layers and the interlayer insulating layers; a gate insulating layer disposed over an inner wall of the vertical hole; a charge trap layer disposed over an inner wall of the gate insulating layer; a channel layer disposed over an inner wall of the charge trap layer; and a variable resistance layer disposed over an inner wall of the channel layer.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventor: Jae Hyun Han
  • Patent number: 11942177
    Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Ta Yu, Chia-En Huang, Sai-Hooi Yeong, Yih Wang, Yi-Ching Liu
  • Patent number: 11935590
    Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ghazi Sarwat Syed, Manuel Le Gallo-Bourdeau, Abu Sebastian
  • Patent number: 11935591
    Abstract: According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 19, 2024
    Assignee: Kioxia Corporation
    Inventors: Masahiro Takahashi, Hiroshi Ito, Ryousuke Takizawa
  • Patent number: 11917818
    Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: February 27, 2024
    Assignee: SK HYNIX INC.
    Inventors: Sung Lae Oh, Sang Woo Park, Dong Hyuk Chae, Ki Soo Kim
  • Patent number: 11915749
    Abstract: A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 27, 2024
    Assignee: eMemory Technology Inc.
    Inventor: I-Lang Lin
  • Patent number: 11915754
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 11908517
    Abstract: A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 20, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Chiang Hung
  • Patent number: 11908502
    Abstract: A method for reducing noise in a read signal due attributable to read element asymmetry provides for transmitting a write signal through a write precompensation circuit that shifts rising edges and falling edges of each of pulse in the write signal by a select magnitude and in opposite directions. After the write signal is encoded on a media, a corresponding read signal is read, with a read element, from the media. The method further provides for transmitting the read signal through a magnetoresistive asymmetry compensation (MRAC) block that is tuned to correct second-order non-linearities characterized by a particular set of distortion signatures. The select magnitude of the waveform shift applied by the write precompensation circuit introduces a non-linear signal characteristic that combines with non-linear signal characteristics introduced by the read element to generate one of the particular distortion signatures that is correctable by the MRAC block.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Walter R. Eppler, Drew Michael Mader
  • Patent number: 11910733
    Abstract: A method includes forming a bottom electrode, forming a dielectric layer, forming a Phase-Change Random Access Memory (PCRAM) region in contact with the dielectric layer, and forming a top electrode. The dielectric layer and the PCRAM region are between the bottom electrode and the top electrode. A filament is formed in the dielectric layer. The filament is in contact with the dielectric layer.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sheng-Chih Lai
  • Patent number: 11908518
    Abstract: A memory system according to an embodiment includes a first wiring, a second wiring, a memory cell between the first wiring and the second wiring and a controller. The memory cell includes a variable resistance element and a switching element. The variable resistance element is switchable between a first low-resistance state and a first high-resistance state. The switching element is switchable between a second low-resistance state and a second high-resistance state in accordance with a supplied voltage. The controller is configured to supply the first wiring with a first voltage switching the switching element to the second low-resistance state, supply the first wiring with a second voltage switching the switching element from the second low-resistance state to the second high-resistance state after the first voltage is supplied, and detect a first target voltage of the second wiring after the second voltage is supplied.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Akira Katayama
  • Patent number: 11907831
    Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: February 20, 2024
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Md Raqibul Hasan, Tarek M. Taha
  • Patent number: 11900987
    Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: February 13, 2024
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Mohit Gupta, Manu Komalan Perumkunnil
  • Patent number: 11901030
    Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hung-Chang Yu
  • Patent number: 11887665
    Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11881253
    Abstract: The present disclosure includes apparatuses, methods, and systems for using an average reference voltage for sensing memory. An embodiment includes a memory having a plurality of memory cells coupled to a common node driver, where a group of the memory cells are coupled to an access line and each respective memory cell of the group is coupled to a different respective sense line, sense circuitry coupled to the different respective sense lines, and circuitry configured to apply an average reference voltage from the common node driver to the sense circuitry during a sense operation being performed on the group of memory cells coupled to the access line.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Pierguido Garofalo
  • Patent number: 11880463
    Abstract: In some embodiments, the present disclosure provides systems and methods for detecting malware, including receiving thermal images of an integrated circuit, and generating a power density profile using at least one of the thermal images. The present disclosure further includes comparing the power density profile to an expected power density profile of the integrated circuit, and determining, based on the comparison, if the integrated circuit is in an abnormal operating state.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: January 23, 2024
    Assignees: Trustees of Tufts College, Drexel University
    Inventors: Mark Hempstead, David Werner, Eric Miller, Kyle Juretus, Ioannis Savadis
  • Patent number: 11875866
    Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Takafumi Kunihiro
  • Patent number: 11864474
    Abstract: A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Franco Stellari, Guy M. Cohen, Nanbo Gong
  • Patent number: 11861781
    Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 2, 2024
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Sreekanth Godey, Ashkan Hosseinzadeh Namin, Seunghun Jin, Teik-Chung Tan
  • Patent number: 11864393
    Abstract: A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Sai-Hooi Yeong, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Patent number: 11853846
    Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 26, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, John Paul Strachan, Sergey Serebryakov
  • Patent number: 11848051
    Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Patent number: 11823741
    Abstract: In some embodiments, the present disclosure relates a phase change random access memory device that includes a phase change material (PCM) layer disposed between bottom and top electrodes. A controller circuit is coupled to the bottom and top electrodes and is configured to perform a first reset operation by applying a signal at a first amplitude across the PCM layer for a first time period and decreasing the signal from the first amplitude to a second amplitude for a second time period; and to perform a second reset operation by applying the signal at a third amplitude across the PCM layer for a third time period and decreasing the signal from the third amplitude to a fourth amplitude for a fourth time period greater than the second time period. After the fourth time period, the PCM layer has a percent crystallinity greater than the PCM layer after the second time period.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jau-Yi Wu
  • Patent number: 11823737
    Abstract: Devices, systems and methods for adaptively controlling a reset current of a memory cell are described. A system comprises: a mirror circuit with one branch coupled with a top electrode of the memory cell and the other branch coupled with one end of a resistive reference, and wherein a bottom electrode of the memory cell is coupled to a reference potential, the other end of the resistive reference is provided with a first electric potential; a control circuit; and a feedback circuit for feeding an electric potential to the top electrode of the memory cell.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Umberto Di Vincenzo
  • Patent number: 11818899
    Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wooyoung Yang, Bonwon Koo, Chungman Kim, Kwangmin Park, Hajun Sung, Dongho Ahn, Changseung Lee, Minwoo Choi
  • Patent number: 11810854
    Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, a plurality of conductive vertical interconnects extending perpendicular to the first level, and one or more programmable vertical interconnects that extend perpendicular to the first level and include a programmable material having a modifiable resistivity in that the one or more programmable vertical interconnects change between being conductive and being non-conductive according to a current pattern.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 7, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford, Anton J. deVilliers
  • Patent number: 11812676
    Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Mathew Philip, Lawrence A. Clevenger, Kevin W. Brew
  • Patent number: 11810618
    Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Allan Porterfield
  • Patent number: 11804265
    Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventor: In Ku Kang
  • Patent number: 11804263
    Abstract: A semiconductor device may include a word line, a bit line crossing the word line, and a memory cell coupled to the word line and the bit line to receive an electrical signal to control the memory cell and including a switching material layer and an oxidation-reduction reversible material layer that is in contact with the switching material layer to allow for either oxidation reaction or reduction reaction to occur in response to different amplitudes and different polarities of the electrical signal, wherein the oxidation-reduction reversible material layer and the switching material layer responds to a first threshold voltage and a first polarity of the electrical signal to generate an oxidation interface between the switching material layer and the oxidation-reduction reversible material layer, and responds to a second threshold voltage and a second polarity of the electrical signal to reduce the generation of the oxidation interface.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: October 31, 2023
    Assignee: SK HYNIX INC.
    Inventor: Tae Jung Ha
  • Patent number: 11798623
    Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: October 24, 2023
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin