Resistive Patents (Class 365/148)
  • Patent number: 11362088
    Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 14, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 11355186
    Abstract: A memory device includes a plurality of bit lines extending in a first direction, a plurality of lower memory cells below the bit lines and connected to the plurality of bit lines, and a plurality of upper memory cells above the plurality of bit lines and connected to the plurality of bit lines. The memory device comprises a plurality of cell array regions and a plurality of bit line contact regions alternately stacked in the first direction, the plurality of upper memory cells and the plurality of lower memory cells are located in the cell array regions, and only one of either the plurality of upper memory cells or the plurality of lower memory cells are arranged in at least one of the bit line contact regions.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yongjin Kwon
  • Patent number: 11355191
    Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 7, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti
  • Patent number: 11355172
    Abstract: A magnetic random access memory cell and a method for forming a magnetic random access memory are provided. The memory cell includes a substrate including a plurality of active regions and a plurality of isolation regions each between adjacent active regions. The memory cell also includes a gate structure over each active region, and a word line structure over each isolation region. In addition, the memory cell includes a source region and a drain region in the substrate on both sides of the gate structure, and a dielectric structure over the substrate. The gate structure and the word line structure are located in the dielectric structure. Further, the memory cell includes a source line structure located in the dielectric structure and electrically connected to the source region over each active region. The word line structure, the gate structure, and the source line structure are parallel to each other.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 7, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Xiaohua Li, Yu Li
  • Patent number: 11355187
    Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.
    Type: Grant
    Filed: January 2, 2021
    Date of Patent: June 7, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Victor Nguyen, Fethi Dhaoui, John L McCollum, Fengliang Xue
  • Patent number: 11348638
    Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
  • Patent number: 11347254
    Abstract: Subject matter disclosed herein may relate to generation of programmable voltage references.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 31, 2022
    Assignee: ARM, Ltd.
    Inventors: Bal S. Sandhu, George McNeil Lattimore, Robert Campbell Aitken
  • Patent number: 11348652
    Abstract: The disclosed embodiments provide neural network inference accelerator based on one-time-programmable (OTP) memory arrays with one-way selectors. In some embodiments, a memory array may comprise: a plurality of one-time-programmable memory cells each comprising: a one-time-programmable memory element; a top electrode having an upper surface in contact with the one-time-programmable memory element; a dielectric layer in contact with a lower surface of the top electrode; a bottom electrode; and a dense layer having an upper surface in contact with the dielectric layer, and a lower surface in contact with the bottom electrode, wherein the dense layer comprises Al2O3 or MgO.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 31, 2022
    Assignee: Hefei Reliance Memory Limited
    Inventor: Liang Zhao
  • Patent number: 11349071
    Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: May 31, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan, Steven Soss
  • Patent number: 11348637
    Abstract: Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11342036
    Abstract: A memory device includes: a cell array including a memory cell and a reference cell; a sense amplifier configured to sense a difference between a first current flowing through the memory cell and a second current flowing through the reference cell, based on an activated sense enable signal; a controller configured to inactivate the sense enable signal in a program interval and activate the sense enable signal in a verify interval subsequent to the program interval, during a write operation; and a voltage driver configured to provide a write voltage to the memory cell in the program interval and the verify interval during the write operation, and to provide a read voltage to the memory cell during a read operation.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Artur Antonyan
  • Patent number: 11342499
    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Timothy E. Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka
  • Patent number: 11328772
    Abstract: Methods of using large output resistance with adjusted conductance mapping value to reduce the current in crossbar array circuit are disclosed. An example method of simulating a crossbar array circuit having a crossbar array, includes steps of: S1. testing the crossbar array; S2. calibrating a simulation model; S3. simulating the crossbar array with the simulation model, wherein a simulation result is generated after the S3; S4. determining a fixed ratio of ideal current from the simulation result; S5. adjusting conductance mapping value to let the crossbar array pass the fixed ratio of ideal current and generating a conductance matrix; S6. programming the conductance matrix to the crossbar array; S7. passing an input signal to the crossbar array and generating a computing result; and S8. checking the quality of computing results.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 10, 2022
    Assignee: TetraMem, Inc.
    Inventors: Miao Hu, Ning Ge
  • Patent number: 11328752
    Abstract: A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Massimiliano Frulio
  • Patent number: 11329102
    Abstract: Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: May 10, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Masaru Yano
  • Patent number: 11329101
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A first access transistor is arranged on the first semiconductor material layer, where the first access transistor has a pair of first source/drain regions having a first doping type. A second access transistor is arranged on the first semiconductor material layer, where the second access transistor has a pair of second source/drain regions having a second doping type opposite the first doping type. A resistive memory cell having a bottom electrode and an upper electrode is disposed over the semiconductor substrate, where one of the first source/drain regions and one of the second source/drain regions are electrically coupled to the bottom electrode.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 11322545
    Abstract: Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 3, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Martin Foltin
  • Patent number: 11315009
    Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 26, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Miao Hu, John Paul Strachan
  • Patent number: 11315617
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11309021
    Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin
  • Patent number: 11309024
    Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hari Giduturi
  • Patent number: 11302390
    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Robustelli, Fabio Pellizzer, Innocenzo Tortorelli, Agostino Pirovano
  • Patent number: 11302393
    Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11295811
    Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to apply, prior to sensing a data state of a memory cell of the plurality of memory cells, a voltage to an access line to which the memory cell is coupled, determine whether an amount of current on the access line in response to the applied voltage meets or exceeds a threshold amount of current, and determine whether to increase a magnitude of a current used to sense the data state of the memory cell based on whether the amount of current on the access line in response to the applied voltage meets or exceeds the threshold amount of current.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhongyuan Lu, Robert J. Gleixner, Karthik Sarpatwari
  • Patent number: 11289144
    Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 29, 2022
    Assignee: NXP USA, Inc.
    Inventors: Jon Scott Choy, Karthik Ramanan, Padmaraj Sanjeevarao, Jacob T. Williams
  • Patent number: 11289159
    Abstract: A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 29, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Florian Longnos, Engin Ipek, Shihai Xiao
  • Patent number: 11288570
    Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 29, 2022
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kyu Choi, Jae Hur
  • Patent number: 11289136
    Abstract: An access method for a memory device is provided. The access method includes receiving external data; reading a plurality of first memory cells of the memory device according to a write address to obtain first original data; comparing the external data and the first original data to determine whether the number of specific cells among the first memory cells is higher than a predetermined value, wherein the value of each of the specific cells would be changed from a first value to a second value in response to the external data being written into the first memory cells; and reversing the external data to generate reversed data and writing the reversed data into the first memory cells to replace the first original data in response to the number of specific cells being higher than the predetermined value.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 29, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Po-Yuan Tang, Jian-Yuan Hsiao
  • Patent number: 11282573
    Abstract: A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 22, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Davide Manfre′, Laura Capecchi, Marcella Carissimi, Marco Pasotti
  • Patent number: 11270774
    Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
  • Patent number: 11271152
    Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Kenichi Murooka
  • Patent number: 11264290
    Abstract: A TMR element includes a reference layer, a magnetization free layer, a tunnel barrier layer between the reference layer and the magnetization free layer, and a perpendicular magnetization inducing layer and a leakage layer stacked on a side of the magnetization free layer opposite to the tunnel barrier layer side. A magnetization direction of the reference layer is fixed along a stack direction. The perpendicular magnetization inducing layer imparts magnetic anisotropy along the stack direction to the magnetization free layer. The leakage layer is disposed on an end portion region in an in-plane direction of the magnetization free layer. The perpendicular magnetization inducing layer is disposed on at least a central region in the in-plane direction of the magnetization free layer. A resistance value of the leakage layer along the stack direction per unit area in plane is less than that of the perpendicular magnetization inducing layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: March 1, 2022
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 11264094
    Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Bruce Querbach, Christopher Connor
  • Patent number: 11250898
    Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: February 15, 2022
    Assignee: NXP USA, INC.
    Inventors: Padmaraj Sanjeevarao, Jacob T. Williams, Karthik Ramanan, Jon Scott Choy
  • Patent number: 11251302
    Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Patent number: 11244721
    Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dojeon Lee, Dueung Kim, Jin-Young Kim
  • Patent number: 11239156
    Abstract: Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Elijah Karpov, Manish Chandhok, Nafees Kabir
  • Patent number: 11232836
    Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Fu Lee, Yu-Der Chih
  • Patent number: 11226763
    Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 18, 2022
    Assignees: International Business Machines Corporation, ETH ZURICH (EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH)
    Inventors: Manuel Le Gallo-Bourdeau, Kumudu Geethan Karunaratne, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi, Luca Benini
  • Patent number: 11227990
    Abstract: A magnetic memory structure is provided. The magnetic memory structure includes a magnetic tunneling junction (MTJ) layer and a heavy-metal layer. The MTJ layer includes a pinned-layer, a barrier-layer formed under the pinned-layer and a free-layer formed under the barrier-layer. The heavy-metal layer is formed under the free-layer. The barrier-layer has a first upper surface, the pinned-layer has a lower surface, and area of the first upper surface is larger than area of the lower surface.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 18, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ziaur Rahaman Shakh, I-Jung Wang, Jeng-Hua Wei
  • Patent number: 11227654
    Abstract: A semiconductor device includes memory devices respectively comprising a selector transistor in series with a control transistor and a memory cell, wherein the control transistor is connected to the memory cell. Control lines of the semiconductor device extend along a first direction, and a first control line is connected to a first memory device control transistor and a second memory device control transistor. Word lines extend in the first direction, and a first word line is connected to a first memory device selector transistor and a second memory device selector transistor. Bitlines extend in a second direction, with a first bitline connected to a first memory device memory cell and a second bitline is connected to a second memory device memory cell. Source lines extend in the second direction, and a first source line is connected to the first memory device selector transistor and the second memory device selector transistor.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Crossbar, Inc.
    Inventor: Hagop Nazarian
  • Patent number: 11222923
    Abstract: The disclosure provides a resistance variable memory that can realize high integration. The resistance variable memory of the disclosure includes a plurality of transistors formed on a surface of a substrate, and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction. One electrode of each of the variable resistance elements is commonly electrically connected to one electrode of one transistor, and another electrode of each of the variable resistance elements is respectively electrically connected to a bit line, and another electrode of each of the transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 11, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Yasuhiro Tomita
  • Patent number: 11222970
    Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 11, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 11222704
    Abstract: A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises detecting a transition associated with the memory device from a first power state to a second power state, responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency, and performing one or more block family calibration operations.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: January 11, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Vamsi Pavan Rayaprolu
  • Patent number: 11217306
    Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato
  • Patent number: 11217309
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Jung Hyuk Yoon
  • Patent number: 11217281
    Abstract: A differential sensing device includes two reference cells, four path selectors, and four sample circuits. The first path selector is coupled to a first sensing node, the second reference cell, and a first memory cell. The second path selector is coupled to a second sensing node, the first reference cell, and the first memory cell. The third path selector is coupled to a third sensing node, the first reference cell, and a second memory cell. The fourth path selector is coupled to a fourth sensing node, the second reference cell, and the second memory cell. During a sample operation, the first sample circuit samples a first cell current, the second sample circuit samples the first reference current, the third sample circuit samples a second cell current, and the fourth sample circuit samples the second reference current.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 4, 2022
    Assignee: eMemory Technology Inc.
    Inventors: Cheng-Te Yang, Cheng-Heng Chung
  • Patent number: 11216728
    Abstract: Provided are a weight matrix circuit and a weight matrix input circuit. The weight matrix circuit includes a memory array including n input lines, m output lines, and n×m resistive memory devices each connected to the n input lines and the m output lines and each having a non-linear current-voltage characteristic, an input circuit connected to each of the input lines, and an output circuit connected to each of the output lines. The input circuit is connected to the resistive memory devices such that the weight matrix circuit has a linear current-voltage characteristic.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 4, 2022
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae-Joon Kim, Taesu Kim, Hyungjun Kim
  • Patent number: 11211134
    Abstract: An IC structure includes a first FinFET including a first plurality of gate structures overlying a first plurality of fin structures, a second FinFET including a second plurality of gate structures overlying a second plurality of fin structures, and an eFuse including a conductive element positioned between the first and second pluralities of gate structures. The conductive element of the eFuse includes a first contact region electrically connected to each of the first and second pluralities of fin structures.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang
  • Patent number: 11211125
    Abstract: A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: December 28, 2021
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja