Resistive Patents (Class 365/148)
  • Patent number: 10855287
    Abstract: Various embodiments include providing a MTJ-based LUT and adding a system that short circuits or causes dielectric layer breakdown of selected MTJ junctions to permanently finalize a desired logic state configuration of selected MTJs that is read out by the LUT. Additional embodiments disable dielectric layer breakdown or short circuit control circuits to prevent further alterations to MTJ that have not had their dielectric layers broken down or shorted out. A control system then alters reading out the MTJ-based LUT to sense original higher and lower resistance values of un-shorted/altered MTJs as a higher resistance state and a shorted or dielectric layer that has been broken down as a lower resistance state. This combines the flexibility of a multiple-time programmable LUT-based FPGA with the security and reliability of a one-time programmable LUT-based FPGA which has characteristics of a fixed logic non-programmable integrated circuit or application specific integrated circuit (ASIC).
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 1, 2020
    Assignee: United States of America, as Represented by the Secretary of the Navy
    Inventors: Matthew James Kay, Matthew John Gadladge, Adam Ray Duncan, Brett J. Hamilton, Andrew Mark Howard
  • Patent number: 10854253
    Abstract: A magnetic storage device includes a memory cell including a magnetoresistive effect element. The megnetoresistive effect element includes a storage layer and a reference layer. The magnetic storage device also includes a first line electrically coupled to a first terminal of the magnetoresistive effect element, a second line electrically coupled to a second terminal of the magnetoresistive effect element, and a write driver. The write driver supplies a first voltage to the first line in a first write operation in which a first resistance value of the magnetoresistive effect element is changed to a second resistance value smaller than the first resistance value, and supplies a second voltage different from the first voltage to the second line in a second write operation in which the second resistance value of the magnetoresistive effect element is changed to the first resistance value.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: December 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsuneo Inaba
  • Patent number: 10854812
    Abstract: Systems and methods of use and fabrication are described for a non-volatile resistive random access memory (RRAM) multi-terminal device including a first electrode, a second electrode, a metal oxide disposed between the first electrode and the second electrode, and an at least first gate configured to apply a voltage bias to change a resistive state in the metal oxide.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: December 1, 2020
    Assignee: University of Cincinnati
    Inventors: Rashmi Jha, Andrew Rush, Eric Herrmann
  • Patent number: 10847220
    Abstract: The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 10847223
    Abstract: A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va>Vd>Vb and Va>Vd>Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoki Kusunoki, Toshiyuki Enda, Hiroki Tokuhira, Takayuki Miyazaki
  • Patent number: 10847717
    Abstract: A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: 4DS MEMORY, LIMITED
    Inventor: Seshubabu Desu
  • Patent number: 10839903
    Abstract: A resistive memory device includes a memory cell array including a memory cell connected between a first signal line and a second signal line, an instance of control circuitry configured to generate a write control signal to control a data writing operation performed on the memory cell and a read control signal to control a data reading operation of reading data stored in the memory cell, a write circuit configured to supply a write current to support the data writing operation, a read circuit configured to supply a read current to support the data reading operation, a column decoder circuit configured to electrically connect the write circuit to the first signal line, based on the write control signal; and a row decoder circuit configured to electrically connect the read circuit to the second signal line, based on the read control signal.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyun-Kook Park
  • Patent number: 10840299
    Abstract: An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chia-Ming Liu, Ting-Ying Shen, Ming-Che Lin
  • Patent number: 10839872
    Abstract: A random bit cell includes a latch, a voltage selector, a first non-volatile storage element, and a second non-volatile storage element. The latch has a first terminal coupled to a first local bit line, and a second terminal coupled to a second local bit line. The first non-volatile storage element has a first terminal coupled to the first local bit line, and a second terminal coupled to the voltage selector. The second non-volatile storage element has a first terminal coupled to the second local bit line, and a second terminal coupled to the voltage selector. During an initial operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element are floating. During an enroll operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element receive a program voltage from the voltage selector.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 17, 2020
    Assignee: eMemory Technology Inc.
    Inventor: Ching-Hsiang Hsu
  • Patent number: 10839897
    Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero
  • Patent number: 10839901
    Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Dong Lee, Tae Hoon Kim
  • Patent number: 10832772
    Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Iason Giannopoulos, Abu Sebastian, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Vara Sudananda Prasad Jonnalagadda
  • Patent number: 10832773
    Abstract: A system includes an analog memory architecture for performing differential reading. The analog memory architecture includes a weight array including first cross-point devices located at intersections of a first set of conductive column wires and a first set of conductive row wires, and a reference array operatively coupled to the weight array and including second cross-point devices located at intersections of a second set of conductive column wires and a second set of conductive row wires. The second cross-point devices include differential unipolar switching memory devices configured to enable zero-value shifting of the outputs of the first cross-point devices.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Tayfun Gokmen, Nanbo Gong, Wanki Kim
  • Patent number: 10833271
    Abstract: Disclosed is a method for the fabrication of a correlated electron material (CEM) switching device, the method comprising: forming a layer of a conductive substrate; forming a layer of a correlated electron material on the conductive substrate; forming a layer of a conductive overlay on the layer of correlated electron material; and patterning the layers whereby to form a stack comprising a conductive substrate, a CEM layer and a conductive overlay, wherein the patterning comprises the following steps: forming a hard mask on the layer of the conductive overlay; dry etching the layer of conductive overlay and the layer of correlated electron material whereby to form a partially formed stack; depositing a coating of a protective polymer over at least sidewalls of the partially formed stack; and dry etching the layer of conductive substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 10, 2020
    Assignee: ARM Ltd.
    Inventors: Ming He, Paul Raymond Besser
  • Patent number: 10832911
    Abstract: An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 ?m to 1.6 ?m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 10, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Toru Oka, Yukihisa Ueno, Kota Yasunishi
  • Patent number: 10832751
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Patent number: 10833125
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 10, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Patent number: 10825518
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 3, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 10825862
    Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, You-Jin Jung, Masayuki Terai, Jinchan Yun
  • Patent number: 10825515
    Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Keun Kim
  • Patent number: 10825987
    Abstract: Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Pengyuan Zheng, Yongjun J. Hu, Yao Jin, Hongqi Li, Andrea Gotti
  • Patent number: 10818352
    Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-gyu Lee, Yong-jun Lee, Bilal Ahmad Janjua, Chea-ouk Lim, Makoto Hirano
  • Patent number: 10818363
    Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technolgy, Inc.
    Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
  • Patent number: 10811092
    Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chi-Shun Lin, Chuen-Der Lien, Douk-Hyoun Ryu, Ming-Huei Shieh, Seow Fong Lim
  • Patent number: 10812076
    Abstract: A logic integrated circuit includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 20, 2020
    Assignee: NEC CORPORATION
    Inventors: Ryusuke Nebashi, Toshitsugu Sakamoto, Makoto Miyamura, Yukihide Tsuji, Ayuka Tada, Xu Bai
  • Patent number: 10804351
    Abstract: An organic light-emitting diode (OLED) display panel and a display device are provided. An array substrate in the OLED display panel is provided with a first retaining wall surrounding a display region of the array substrate, and a second retaining wall surrounding the first retaining wall. Multiple outer electrode lines are exposed in a gap region between the first retaining wall and the second retaining wall on the array substrate. At least one of the multiple outer electrode lines is provided with at least one outer blocking portion at an edge region on at least one side of the outer electrode line, and the outer blocking portion breaks an edge line on the side of the outer electrode line in an extending direction of the outer electrode line and in contact with the outer electrode line.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 13, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventor: Peng Zhang
  • Patent number: 10803938
    Abstract: Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Alessio Spessot, Paolo Fantini, Massimo Ferro
  • Patent number: 10797106
    Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
  • Patent number: 10796744
    Abstract: Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Roy E. Meade
  • Patent number: 10796759
    Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Patent number: 10796751
    Abstract: A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 6, 2020
    Assignee: CROSSBAR, INC.
    Inventors: Sang Nguyen, Hagop Nazarian, Tianhong Yan
  • Patent number: 10796758
    Abstract: Described herein is a non-volatile memory device in which it is possible to switch between different reading modes. In particular, the memory device includes a plurality of memory cells and implements, alternatively, a reading of a differential type and a reading of a single-ended type. Further described herein is a method for reading the memory device.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 6, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Antonino Conte
  • Patent number: 10790020
    Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 10790019
    Abstract: To provide a novel and improved semiconductor storage device which is capable of implementing a large capacity by enabling normal reading of a value from a storage element. A semiconductor storage device is provided, the semiconductor storage device including: a memory element; a reference element in a first resistance state for generating a reference potential for identifying a value held in the memory element; and a reference element in a second resistance state in which a resistance value of the reference element is higher than that in the first resistance state for generating the reference potential, in which when generating the reference potential, the number of reference elements in the first resistance state is larger than the number of reference elements in the second resistance state.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 29, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Masami Kuroda
  • Patent number: 10790031
    Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 29, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Piyush Sagdeo, Chris Yip, Sourabh Sankule, Pitamber Shukla, Anubhav Khandelwal, Mohan Dunga, Niles Yang
  • Patent number: 10783946
    Abstract: According to an embodiment, a semiconductor memory device includes: memory cell arrays; word lines respectively connected to rows of each of the memory cell arrays; bit lines respectively connected to columns of each of the memory cell arrays; row selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the word lines; and column selection circuits provided so as to respectively correspond to the memory cell arrays and connected to the bit lines. When an identical row address is received, the row selection circuits perform selection operations of word lines so that word line lengths from selected memory cells to the row selection circuits vary.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Miyakawa, Katsuhiko Hoya
  • Patent number: 10783964
    Abstract: A memory device includes an array of resistive memory cells wherein each pair of resistive memory cells includes a first switching element electrically coupled in series to a first resistive memory element and a second switching element electrically coupled in series to a second resistive memory element. A source of the first switching element and a source of the second switching element receive a common source line signal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: September 22, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis
  • Patent number: 10777273
    Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: September 15, 2020
    Assignee: Arm LTD
    Inventors: Shidhartha Das, James Edward Myers, Seng Oon Toh
  • Patent number: 10777272
    Abstract: The disclosure provides a semiconductor memory device that improves the reliability of data reading and achieves good area efficiency. A variable resistance memory of the disclosure includes a memory array, a row decoder, a column decoder, a writing part, and a reading part. The memory array includes a plurality of memory cells. The row decoder selects the memory cells in a row direction. The column decoder selects the memory cells in a column direction. The writing part writes identical data to a pair of memory cells that is selected. The reading part reads the data stored in the pair of memory cells that is selected. The reading part includes a sense amplifier that compares a total of the currents respectively flowing through the pair of memory cells with a reference value.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 15, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Hajime Aoki
  • Patent number: 10777233
    Abstract: A nonvolatile memory device includes a first memory block including a plurality of cell transistors interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines, which are stacked in a direction perpendicular to a substrate, a block selecting circuit that is connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and provides corresponding driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines in response to a block selection signal, respectively, and a block unselecting circuit that is connected only with specific string selection lines of the plurality of string selection lines, and provides an off-voltage only to the specific string selection lines in response to a block un-selection signal.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 15, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Euihyun Cheon, Byungjun Min
  • Patent number: 10777270
    Abstract: A memory controller may control a resistive memory device including memory cells may control the resistive memory device to program the memory cells into a first resistance state, control the resistive memory device to read data from the memory cells that are programmed, receive bit error rates (BER) of the memory cells, occurring in a read operation, from the resistive memory device, may determine the number of program operations on the memory cells corresponding to the BER and may, based on the number of program operations that is determined, control the memory cells to be programmed into the first resistance state by using a write current having a current level higher than that of a minimum write current required for the memory cells to be changed into the first resistance state.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-you Baek, Han-sung Joo, Ki-sung Kim
  • Patent number: 10777562
    Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John A. Smythe
  • Patent number: 10777607
    Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating such structures. A field-effect transistor of the bitcell includes a gate having gate electrodes that are arranged in a four contacted (poly) pitch layout. An interconnect structure is arranged over the field-effect transistor, and a memory element arranged in the interconnect structure. The memory element is connected by the interconnect structure with the field-effect transistor.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Bipul C. Paul, Anuj Gupta
  • Patent number: 10770167
    Abstract: A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 8, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Chien-Min Wu, He-Hsuan Chao, Chih-Cheng Fu, Shao-Ching Liao
  • Patent number: 10770139
    Abstract: There are provided a variable resistance memory device and an operating method thereof. In a method for operating a variable resistance memory device, the method includes programming multi-bit data in a multi-bit variable resistance memory cell of the variable resistance memory device, wherein the programming includes: generating sequentially increased program voltage pulses, based on the multi-bit data; and applying the program voltage pulses to the multi-bit variable resistance memory cell, wherein a current-voltage curve of the multi-bit variable resistance memory cell exhibits a self-compliance characteristic, wherein the program voltage pulses are included in a voltage section having the self-compliance characteristic.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 8, 2020
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Gun Hwan Kim, Young Kuk Lee, Taek Mo Chung, Bo Keun Park, Jeong Hwan Han, Ji Woon Choi
  • Patent number: 10763433
    Abstract: Subject matter disclosed herein may relate to correlated electron switches that are capable of asymmetric set or reset operations.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Lucian Shifren, Greg Yeric
  • Patent number: 10763432
    Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Mario Allegra
  • Patent number: 10762868
    Abstract: A memory-in-pixel circuit and a driving method thereof, a liquid crystal display panel and a wearable device are disclosed. The memory-in-pixel circuit includes a latch circuit, a switch circuit and a selection circuit, all transistors included in the latch circuit are first type transistors, and the latch circuit is configured to latch a data voltage and generate a first latch signal and a second latch signal; the switch circuit is configured to provide the data voltage to the latch circuit when the switch circuit is turned on; the selection circuit is configured to apply the first selection signal or the second selection signal to a pixel under control of the first latch signal and the second latch signal, and to continue to apply the first selection signal or the second selection signal to the pixel when the switch circuit is turned off to achieve automatic update of the pixel.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 1, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yimin Chen, Xianjie Shao, Zhangmeng Wang
  • Patent number: 10755779
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 25, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Patent number: 10755781
    Abstract: Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’).
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mattia Robustelli