Pedestal pocket tray containment system for integrated circuit chips
A stacking tray for electrical components, such as integrated circuit chips, particularly those of the ball grid array (BGA) type is disclosed. The tray is stackable and includes an upper side and a lower side. An array of storage pockets is formed between the upper side of a lower tray and the lower side of an upper tray. The storage pockets are separated by complementary support elements and further include a segmented pedestal arising from the center of the storage pocket, on the upper side of the trays. The segmented pedestal supports the integrated circuit chip, without interfering with the spherical balls. Moreover, the tray allows for variation of the dimensions of the integrated circuit chip while adequately stabilizing the chip.
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1. Field of the Invention
The present invention pertains to a tray for the storage and transportation of integrated circuit chips, particularly ball grid array (BGA) chips.
2. Description of the Prior Art
The need for mechanical and electrostatic protection of integrated circuit chips during storage and transportation is firmly established in the prior art. The use of stacking trays for the storage and transportation of integrated circuit chips, as well as for providing the trays in an unstacked configuration for subsequent pick-and-place operations, is well developed and is particularly well adapted for its intended purposes. However, the wide variety of dimensions and configurations (which may be as subtle as edge clearance, ball pitch or device thickness) of integrated circuit chips makes it difficult to assure that a properly sized tray will be available for the many different integrated circuit chips which may need to be stored or transported from a given location, particularly if the trays are configured to hold the chips by their edges within pockets of the trays. This can be a particular concern for ball grid array (BGA) chips which include spherical protrusions which must be accommodated without compromising the mechanical or electrostatic protection.
Some examples of the prior art stackable trays can be found in U.S. Pat. No. 5,400,904 entitled “Tray for Ball Terminal Integrated Circuits”, issued to Maston et al. on Mar. 28, 1995; U.S. Pat. No. 5,103,976 entitled “Tray for Integrated Circuits with Supporting Ribs”, issued to Murphy on Apr. 14, 1992; U.S. Pat. No. 5,080,228 entitled “Integral Carrier and System for Electrical Components”, issued to Maston et al. on Jan. 14, 1992; U.S. Pat. No. 5,000,697 entitled “Carrier System for PGA Electrical Components”, issued to Murphy on Mar. 19, 1991; U.S. Pat. No. 4,765,471 entitled “Electrical Component Carrier”, issued to Murphy on Aug. 23, 1988.
Additional examples can be found in commonly owned U.S. patent application Ser. No. 10/414,617, filed on Apr. 16, 2003 entitled “Stackable Tray for Integrated Circuits with Corner Support Elements and Lateral Support Elements Forming Matrix Tray Capture System” and commonly owned U.S. patent application Ser. No. 11/057,343, filed on Feb. 14, 2005, entitled “Stackable Tray for Integrated Circuit Chips”.
OBJECTS AND SUMMARY OF THE INVENTIONIt is therefore an object of the present invention to provide an apparatus and method for the storage of integrated circuit chips, particularly ball grid array (BGA) chips.
It is therefore a further object of the present invention to provide an apparatus and method for the storage and shipment of integrated circuit chips of different dimensions within a single device.
These and other objects are attained by providing stacking trays with storage pockets formed on the upper and lower surfaces. Successive trays may be stacked so that the storage pockets on the upper surface of a storage tray align with the storage pockets on the lower surface of an upwardly adjacent tray to form storage pockets to retain the integrated circuit chips. The storage pocket on an upper surface of the trays contains a central segmented pedestal. The pedestal stabilizes and supports the integrated circuit chip from underneath so that the integrated circuit chip, particularly a BGA chip, is supported in an area that is not populated with the device spherical interconnecting balls. The segmented pedestal lifts the integrated circuit chip from the floor of the tray to not allow contact of the integrated circuit chips spheres to other portions of the tray when the trays are tilted. The pedestal is typically segmented to allow for variations in the integrated circuit chip, particularly domes which may form on the lower surface of a BGA integrated circuit chip. Additionally, the segments typically further include ears or protrusions to further stabilize the integrated circuit chip supported by the pedestal. These ears are configured and arranged so to not interfere with the sphere array of the supported device.
The tray conforms to JEDEC standards which sets the tray outline, storage pocket locations, outer rail height and stacking configuration which permits an integrated circuit chip seated in a full storage pocket defined by a lower tray storage pocket and an upper tray storage pocket to be restrained and stabilized.
Further objects and advantages of the invention will become apparent from the following description and claims, and from the accompanying drawings, wherein:
Referring now to the drawings in detail wherein like numerals refer to like elements throughout the several views, one sees that
Corner 30 is formed at the intersection of sides 12, 14. Corner 32 is formed at the intersection of sides 14, 16. Corner 34 is formed at the intersection of sides 16, 18. Corner 36 is formed at the intersection of sides 12, 18. L-shaped support elements 40 are formed on the upper surface or side (
As shown in
X-shaped support elements 70 are formed from four segments 71, 72, 73, 74 at successive right angles to each other, joining at center 75. The interior of each four segments 71, 72, 73, 74 is removed thereby forming slots in order to form a seat to receive the corresponding X-shaped element 46 from an upper surface of a downwardly successive tray 10. Additionally, the inner portion of segments 71, 72, 73, 74 have a reduced height, and ledge 77 of this reduced height is formed along both sides of segments 71, 72, 73, 74. Typically, ledges 59, 69 and 77 are of equal height.
Support elements 52, 60, 70 typically include beveled upper (in the configuration or orientation of
As shown in
As shown in
Thus the several aforementioned objects and advantages are most effectively attained. Although preferred embodiments of the invention have been disclosed and described in detail herein, it should be understood that this invention is in no sense limited thereby and its scope is to be determined by that of the appended claims.
Claims
1. A tray for integrated circuit chips comprising:
- a plurality of storage pockets, said storage pockets being bounded at corners thereof by support elements;
- said storage pockets further including a pedestal for supporting an integrated chip thereon.
2. The tray for integrated circuit chips of claim 1 wherein said pedestal is spaced from said support elements thereby allowing storage of integrated chips in said storage pockets free of contact with ball grid elements formed on the integrated circuit chips.
3. The tray for integrated circuit chips of claim 1 wherein the tray is stackable with sequential like trays.
4. The tray for integrated circuit chips of claim 3 including an upper side and a lower side, wherein an upper side of a tray joins with a lower side of a successively upper tray thereby aligning respective storage pockets to store integrated chips therebetween.
5. The tray for integrated circuit chips of claim 4 wherein said pedestal is formed on said upper side of the tray.
6. The tray for integrated circuit chips of claim 5 wherein said support elements are formed on said upper side and said lower side and when a lower tray is stacked and aligned with an upper tray, support elements of the upper side of the lower tray seat with support elements of the lower side of the upper tray.
7. The tray for integrated circuit chips of claim 6 wherein at least a portion of said support elements includes slots for providing seats for receiving corresponding support elements.
8. The tray for integrated circuit chips of claim 7 wherein said at least a portion of said support elements including slots further include ledges formed at a height lower than a height of said support elements.
9. The tray for integrated circuit chips of claim 6 wherein said pedestal is formed from a plurality of segments.
10. The tray for integrated circuit chips of claim 9 wherein said segments include protrusions extending toward corners of said storage pockets.
11. The tray for integrated circuit chips of claim 6 wherein said pedestal is rotationally segmented.
12. The tray for integrated circuit chips of claim 6 wherein chips stored between an upper and a lower tray are at least partially engaged between said support elements of the upper and lower trays thereby stabilizing the chips in a direction perpendicular to the tray.
13. The tray for integrated circuit chips of claim 12 wherein said support elements on said upper side are directly above said support elements on said lower side.
14. The tray for integrated circuit chips of claim 13 wherein X-shaped support elements are formed at an intersection of four storage pockets, T-shaped support elements are formed at an intersection of two storage pockets along sides of the tray and L-shaped support elements are formed at outward corners of corner storage pockets.
15. The tray for integrated circuit chips of claim 14 wherein the tray is rectangular with rows and columns of storage pockets.
16. The tray for integrated circuit chips of claim 15 including a planar floor for supporting said support elements and said pedestals.
17. The tray for integrated circuit chips of claim 16 wherein said planar floor is solid through at least a portion of said storage pockets thereby forming vacuum storage pockets to permit vacuum operated equipment to couple to the tray.
18. The tray for integrated circuit chips of claim 17 wherein said planar floor includes apertures in at least a portion of said storage pockets.
19. The tray for integrated circuit chips of claim 18 wherein said apertures are octant-oriented within said storage pockets.
20. The tray for integrated circuit chips of claim 18 wherein said segments span at least a portion of said apertures.
Type: Application
Filed: Jan 23, 2007
Publication Date: Jul 24, 2008
Applicant:
Inventor: Valoris L. Forsyth (Lewisville, TX)
Application Number: 11/656,657
International Classification: B65D 85/90 (20060101);