Semiconductor memory with conductive carbon
A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.
The present invention relates to a semiconductor device, and more specifically, to novel device structure with conductive carbon.
BACKGROUND OF THE INVENTIONThe EEPROM is widely used in the field of semiconductor industry and has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device and the higher speed of operation. The nonvolatile memories include various types of devices. Different types of devices have been developed for specific applications requirements in each of these segments. Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge in and removing the charges from the floating gate. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid-state camera and PC cards. It is because that the nonvolatile memories exhibit many advantages, such as fast access time, low power dissipation, and robustness. The data program method of a non-volatile memory device includes a method using Fowler-Nordheim (FN) tunneling or a method using hot electron injection. In FN tunneling, a high voltage is applied to a control gate to induce a high electric field in a tunnel oxide layer, and electrons of a semiconductor substrate pass the tunnel oxide layer and are injected into a floating gate. During the mode of erasing, the bias may apply on the source to discharge the electron from the floating gate to the source of a memory device.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Flash memory needs the charges to be hold in the floating gate for a long period of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high quality in insulation and good durability in writing.
As known in the art, the tunneling effect is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate have to be scaled down due to the supply voltage is reduced. The memory cell consists of a source region, a drain region, a floating gate (FG), a control gate (CG) and insulation films. A plurality of sectors are arranged in the two-dimensional manner on a semiconductor substrate of the flash memory. When writing a new data or rewriting a data stored in the flash memory, the stored data in memory cells are erased on the sector basis immediately before the writing. The device is called flash due to the data is erased sector by sector.
However, when the device is scaled down into nanometer range, the carriers characteristics is unlikely to be controlled due to the optical and quantum effects are significantly than ever.
SUMMARY OF THE INVENTIONThe object of the present invention is to disclose a flash device with multi-bits cell capable of storing multi binary information bits. The further object of the present invention is to provide the structure with conductive carbon to improve the operation speed and scaled down the device.
A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation layer formed between the first and second gates; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.
The dual gate structure is a stacked configuration or a split gate configuration. Field oxide structure is formed between the dual gate structure. The gate dielectric layer is high dielectric constant material. The gate dielectric layer includes (SiO2), (HfO2), (ZrO2), (TiO2), (HfTiO), (HfAIO), (La2O3) or (LaAIO). The conductive carbon includes nano carbon tube. The memory further comprises suicide material formed over the doped regions. The silicide material includes TiSi2, CoSi2 or NiSi.
A non-volatile memory capable of storing binary information on a semiconductor substrate comprising: a dual gate structure formed over the semiconductor substrate, wherein the dual gate structure including a gate dielectric layer formed over the semiconductor substrate, and first and second gates formed over the gate dielectric layer, an isolation L-shape structure formed between the first and second gates, wherein a vertical portion of the L-shape structure attached on sidewall of the first gate, and a lateral portion where tunneling will be occurred is formed over the substrate; spacers formed on the L-shape structure to act as a second gate; a conductive carbon material with nano-scale formed under the gate dielectric layer; and a doped regions formed adjacent to the conductive carbon material.
The present invention also discloses a memory comprising: pluralities of bit lines formed over a semiconductor substrate; pluralities of word lines formed over the semiconductor substrate and perpendicular to the pluralities of bit lines forming with intercrossing areas and non-intercrossing areas; at least one conductive carbon located at one of the non-intercrossing areas to define digital status. The memory further comprises gate dielectric layer under the pluralities of word lines. The gate dielectric layer includes (SiO2), (HfO2), (ZrO2), (TiO2), (HfTiO), (HfAIO), (La2O3) or (LaAIO). The conductive carbon includes nano carbon tube.
The spacers represent a first binary status by injecting and storing electrical charge in the spacers or to represent a second binary status by not injecting electrical charge into the spacer. A first and a second fringing field induced channels are under the first and the second spacers, wherein the first and the second fringing field induced channels are located between the main gate-induced channel. The first and the second doped regions sit adjacent to the first and the second fringing field induced channels, respectively. The fringing field induced channels are referred to the hot carrier injection channel under the spacers.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The present invention proposes a novel method to fabricate a memory. In the method, the operation speed for storing data can be increased by the cell structure. The detail description will be seen as follows. A semiconductor substrate is provided for the present invention. In a preferred embodiment, as shown in the
Next, the stacked gate is used as mask to perform the ion implantation for forming the source/drain 30 adjacent to the gate, as shown in
At least one conductive carbon 32, for instance nano-cabon tube (CNT) 32 is located under the gate dielectric 22 of the dual-gates structure. Namely, the conductive carbon 32 connects the S/D 30. The CNT may be formed with at least one to fifty layers structure. The diameters of the CNT maybe 1-2 nanometers and the length is 10-100 nano-meters or shorter. The S/D 30 can be formed by deposition, sputter instead of implantation in order to form the CNT. Alternatively, the CNT 22 maybe keeps a distance with the oxide 22. The embodiment may be includes spacers such as
The formation of CNT is to heat the organic compound having carbon to generate the carbon atoms. One example is to input the reaction gas such as CH4 to the reaction chamber, and the carbon atoms will be separated from the gas when the reaction gas contacts the high temperature substrate. The carbon will be growth. Another method is to drive the C—H compound with CH4 through the nanometers substrate. The conductive carbon has the characteristics of semiconductor property to improve the performance of the device and scaled down the size. During the operation, the carrier of the memory will flow through the tube. The method of forming the CNT may refer to the articles . . . .
A sectional view of a two-bit nonvolatile memory cell in accordance with the present invention is shown in
The memory cell is capable of storing two bits of data, a right bit and a left bit. The two bit memory cell is a symmetrical device. The left junction serves as the source terminal and the right junction serves as the drain terminal for the right bit programming. Similarly, for the left bit programming, the right junction serves as the source terminal and the left junction serves as the drain terminal. The operating mode of the present invention for the right bit is to offer a bias Vgp is applied on the suicide over the gate structure for writing, the source node has 1 nA-1 mA current Isp. Channel hot carrier current is generated in the substrate 20 under the spacer 25 between the gate structure and the drain. The channel hot carrier current will injects into the spacer 25 via the lateral portion of the L-shape structure adjacent to the drain side due to the source, drain keep a distance from the channel under the gate. Electrons are trapped in the portion of nitride spacer near but above and self-aligned with the drain region because the strongest electric field forms there. The carriers are therefore stored in the nitride spacer 25 that functions as the floating gate of the nonvolatile memory. The nitride spacer 25 on the drain side is defined as “digital one”, while the spacer without carrier therein on the drain side is referred to “digital zero”. Hence, a set of memory unit “XY” is written as “X1” or “X0”. It should be understood that the source and drain terminals for the second bit are reversed compared to the source and drain terminals for the first bit. Therefore, the data status can be programmed or defined as “00”, “01”, “10” or “11” by applying the drain-write voltage Vdp and source current Isp depending on the right bit cell or left bit cell. If the two-bits are desired to be programmed as “11”, the drain-write voltage Vdp and source current Isp are introduced on the left bit and right bit, respectively. The cell is operated based upon “forward program and reverse read” scheme. The read current in the channel is reverse compared to the one of programming. The cell shows totally different channel sections, source/drain and SiN spacer arrangement. One of the key features is that the source/drain regions keep a distance to the channel under the gate. Under such arrangement, the present invention is capable of storing 4-bits information rather than two bits. Similarly, the digital data can be erased. In
Another embodiment is illustrated in
As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention is illustrative of the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modification will now suggest itself to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.
Claims
1. A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:
- a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation layer formed between said first and second gates;
- a conductive carbon material with nano-scale formed under said gate dielectric layer; and
- a doped regions formed adjacent to said conductive carbon material.
2. The memory of claim 1, wherein said dual gate structure is a stacked configuration.
3. The memory of claim 1, wherein said dual gate structure is a split gate configuration.
4. The memory of claim 3, wherein a field oxide structure formed between said dual gate structure.
5. The memory of claim 1, wherein said gate dielectric layer is high dielectric constant material.
6. The memory of claim 5, wherein said gate dielectric layer includes (SiO2), (HfO2), (ZrO2), (TiO2), (HfTiO), (HfAIO), (La2O3) or (LaAIO).
7. The memory of claim 1, wherein said conductive carbon includes nano carbon tube.
8. The memory of claim 1, further comprising silicide material formed over said doped regions.
9. The memory of claim 8, wherein said silicide material includes TiSi2, CoSi2 or NiSi.
10. A non-volatile memory capable of storing binary information on a semiconductor substrate comprising:
- a dual gate structure formed over said semiconductor substrate, wherein said dual gate structure including a gate dielectric layer formed over said semiconductor substrate, and first and second gates formed over said gate dielectric layer, an isolation L-shape structure formed between said first and second gates, wherein a vertical portion of said L-shape structure attached on sidewall of said first gate, and a lateral portion where tunneling will be occurred is formed over said substrate; spacers formed on said L-shape structure to act as a second gate;
- a conductive carbon material with nano-scale formed under said gate dielectric layer; and
- a doped regions formed adjacent to said conductive carbon material.
11. The memory of claim 10, wherein said gate dielectric layer is high dielectric constant material.
12. The memory of claim 11, wherein said gate dielectric layer includes (SiO2), (HfO2), (ZrO2), (TiO2), (HfTiO), (HfAIO) ‘ (La2O3) or (LaAIO).
13. The memory of claim 11, wherein said conductive carbon includes nano carbon tube.
14. A memory comprising:
- pluralities of bit lines formed over a semiconductor substrate;
- pluralities of word lines formed over said semiconductor substrate and perpendicular to said pluralities of bit lines forming with intercrossing areas and non-intercrossing areas;
- at least one conductive carbon located at one of said non-intercrossing areas to define digital status.
15. The memory of claim 14, wherein further comprising gate dielectric layer under said pluralities of word lines.
16. The memory of claim 15, wherein said gate dielectric layer includes (SiO2), (HfO2), (ZrO2), (TiO2), (HfTiO), (HfAIO) ‘ (La2O3) or (LaAIO).
17. The memory of claim 14, wherein said conductive carbon includes nano carbon tube.
Type: Application
Filed: Mar 25, 2008
Publication Date: Oct 2, 2008
Inventor: Kuo-Ching Chiang (Linkou Township)
Application Number: 12/076,928
International Classification: H01L 29/00 (20060101);