With Floating Gate Electrode Patents (Class 257/315)
  • Patent number: 11991880
    Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 21, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Yu Ru Huang, Qian Tao, Yushi Hu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Yongna Li, Lidong Song
  • Patent number: 11985827
    Abstract: A novel semiconductor device is provided. A memory string, which extends in the Z direction and includes a conductor and an oxide semiconductor, intersects with a plurality of wirings CG extending in the Y direction. The conductor is placed along a center axis of the memory string, and the oxide semiconductor is concentrically placed outside the conductor. The conductor is electrically connected to the oxide semiconductor. An intersection portion of the memory string and the wiring CG functions as a transistor. In addition, the intersection portion functions as a memory cell.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 14, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hitoshi Kunitake, Kazuki Tsuda
  • Patent number: 11978772
    Abstract: A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: May 7, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 11943915
    Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11935584
    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Mamoru Nishizaki
  • Patent number: 11937437
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 19, 2024
    Assignee: Kioxia Corporation
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Patent number: 11901425
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate having an active region, a source region, a drain region, and a floating gate. The source region and the drain region may be arranged in the active region, the drain region may be arranged adjacent to the source region. The source region and the drain region may define a channel region therebetween. The floating gate may be arranged over the active region, and may include a first section over the channel region, a plurality of second sections over the drain region, and a connecting section arranged between the first section and the plurality of second sections.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 13, 2024
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Xinshu Cai, Eng Huat Toh
  • Patent number: 11853856
    Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: December 26, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
  • Patent number: 11856769
    Abstract: A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 26, 2023
    Assignee: KEY FOUNDRY CO., LTD.
    Inventor: Su Jin Kim
  • Patent number: 11825651
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 11817449
    Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 14, 2023
    Assignee: Macronix International Co., Ltd.
    Inventors: Jung Chuan Ting, Shih-Yu Wang, Shao-Chi Chen
  • Patent number: 11769832
    Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: September 26, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Jin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
  • Patent number: 11765893
    Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate, and crosses over the trench isolation lines.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh
  • Patent number: 11765903
    Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 11755480
    Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventor: Michael R. Seningen
  • Patent number: 11751376
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11723197
    Abstract: The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 8, 2023
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Lei Zhang, Tao Hu, Xiaochuan Wang, Zhi Tian, Qiwei Wang, Haoyu Chen
  • Patent number: 11721727
    Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 8, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11705189
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11699484
    Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: July 11, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 11688586
    Abstract: In an embodiment, a plasma processing system includes a vacuum chamber, a substrate holder configured to hold a substrate to be processed where the substrate holder is disposed in the vacuum chamber. The system further includes an electron source disposed above a peripheral region of the substrate holder, the electron source being configured to generate an electron beam towards the peripheral region of the substrate holder.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 27, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter Ventzek, Alok Ranjan
  • Patent number: 11676642
    Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: June 13, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Fengqin Zhang, Kangling Ji, Kai Tian, Xianjun Wu
  • Patent number: 11658155
    Abstract: A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 23, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Masashi Yamaoka, Kazuhiro Tomishige, Naoki Yamamoto
  • Patent number: 11652148
    Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin
  • Patent number: 11646075
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: May 9, 2023
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11636906
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells, and a peripheral circuit configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a program operation, wherein, during a verify operation included in the program operation, the peripheral circuit may be configured to allow a selected word line, among the plurality of word lines, to float, and may decrease a potential of the selected word line to a pre-level by decreasing potentials of adjacent word lines to the selected word line.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 25, 2023
    Assignee: SK hynix Inc.
    Inventor: Soo Yeol Chai
  • Patent number: 11631615
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, another stack structure vertically overlying the stack structure and comprising alternating levels of other conductive structures and other insulative structures, the other stack structure comprising pillars vertically overlying the strings of memory cells, each pillar comprising an other channel material in electrical communication with the channel material of the strings of memory cells, and conductive contact structures vertically overlying the other stack structure, each conductive contact structure comprising an electrically conductive contact at least partially extending into the pillars and
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Kar Wui Thong
  • Patent number: 11626414
    Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 11, 2023
    Inventors: Sunggil Kim, Sungjin Kim, Seulye Kim, Jung-Hwan Kim, Chan-Hyoung Kim
  • Patent number: 11586901
    Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Borna J. Obradovic, Titash Rakshit, Mark S. Rodder
  • Patent number: 11581336
    Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Ming Lin, Chun-Chieh Lu, Bo-Feng Young, Han-Jong Chia, Chenchen Jacob Wang, Sai-Hooi Yeong
  • Patent number: 11581329
    Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Ryosuke Sawabe, Yasuhiro Uchiyama, Hiroshi Itokawa
  • Patent number: 11569266
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Patent number: 11557599
    Abstract: A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongha Shin, Yohan Lee
  • Patent number: 11538825
    Abstract: Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is selectively removed. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is selectively removed.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 27, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Xiaofen Zheng, Hongbin Zhu, Lixun Gu, Hanwei Yi
  • Patent number: 11532716
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Patent number: 11527493
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 13, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tzu-Ching Tsai
  • Patent number: 11521850
    Abstract: A method for manufacturing a semiconductor device according to an, exemplary embodiment of the present disclosure includes: forming a semiconductor layer on a substrate in a chamber; and forming a semiconductor layer on a substrate in a chamber. Forming the insulation layer includes: (a) injecting precursors that include a metal into a surface of the semiconductor layer; (b) removing precursors that are not adsorbed; (c) injecting reactants onto the surface of the semiconductor layer; and (d) removing residual reactants. The semiconductor layer includes a semiconductor material that has a layered structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Hyung Lim, Hyung Jun Kim, Sun Hee Lee, Seung Gi Seo, Whang Je Woo
  • Patent number: 11522052
    Abstract: A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 11495282
    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Mamoru Nishizaki
  • Patent number: 11488958
    Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 1, 2022
    Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
  • Patent number: 11488665
    Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 1, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11488975
    Abstract: A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Totoki, Fumitaka Amano
  • Patent number: 11488970
    Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: November 1, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Boolean Fan, Nhan Do
  • Patent number: 11476276
    Abstract: A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: October 18, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Guan-Ru Lee
  • Patent number: 11424340
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Patent number: 11424254
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 23, 2022
    Assignee: WInbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai
  • Patent number: 11423979
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 23, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
  • Patent number: 11384428
    Abstract: Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Mang-Mang Ling, Thomas Kwon, Jong Mun Kim, Chentsau Chris Ying
  • Patent number: 11387246
    Abstract: A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yonghoon Son
  • Patent number: 11380699
    Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Guangyu Huang, Haitao Liu