With Floating Gate Electrode Patents (Class 257/315)
  • Patent number: 10439032
    Abstract: To provide a semiconductor device having improved reliability by relaxing the unevenness of the injection distribution of electrons and holes into a charge accumulation film attributable to the shape of the fin of a MONOS memory comprised of a fin transistor. Of a memory gate electrode configuring a memory cell formed above a fin, a portion contiguous to an ONO film that covers the upper surface of the fin and a portion contiguous to the ONO film that covers the side surface of the fin are made of electrode materials different in work function, respectively, and the boundary surface between them is located below the upper surface of the fin.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: October 8, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Yoshitomi, Yoshiyuki Kawashima
  • Patent number: 10418272
    Abstract: At least one method, apparatus and system providing semiconductor devices with relatively short gate heights but without a relatively high risk of contact-to-gate shorts. In embodiments, the method, apparatus, and system may provide contact formation by way of self-aligned contact processes.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Garo Jacques Derderian, Hui Zang, John Zhang, Haigou Huang, Jinping Liu
  • Patent number: 10396275
    Abstract: A magnetic tunnel junction pattern includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a non-magnetic capping layer that are sequentially stacked on a substrate. A top electrode is disposed on the magnetic tunnel junction pattern. A bit line is disposed on the top electrode. The top electrode comprises a metal nitride pattern in contact with the non-magnetic capping layer and a metal pattern disposed on the metal nitride pattern.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghoon Bak, Hong Hyun Kim
  • Patent number: 10388378
    Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: August 20, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10381503
    Abstract: An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 13, 2019
    Assignee: EMBERION OY
    Inventors: Stefano Borini, Alan Colli
  • Patent number: 10381370
    Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
  • Patent number: 10381371
    Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Yuki Mizutani
  • Patent number: 10374100
    Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Doug Weiser, Jack G. Qian
  • Patent number: 10373958
    Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10367009
    Abstract: Provided is an active-matrix substrate in which the line resistance is decreased. The active-matrix substrate includes a substrate 31, a plurality of gate lines Gj disposed on the substrate 31 and extending in a first direction, a plurality of source lines Si disposed on the substrate 31 and extending in a second direction different from the first direction, a transistor 2 disposed correspondingly to each of intersection points of the gate lines and the source lines Si and connected to a corresponding one of the gate lines Gj and a corresponding one of the source lines Si, an insulating layer, and extended conductive films 51, 52, and 61. At least ones of the gate lines Gj and the source lines Si each have a layered structure with connection to the extended conductive film via a contact hole provided in the insulating layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: July 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Fumiki Nakano
  • Patent number: 10355134
    Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device and techniques for fabricating a semiconductor device. In certain aspects, the semiconductor device includes a fin, a first non-insulative region disposed adjacent to a first side of the fin, and a second non-insulative region disposed adjacent to a second side of the fin. In certain aspects, the first non-insulative region and the second non-insulative region are separated by a trench, at least a portion of the trench being filled with a dielectric material disposed around the fin.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Narasimhulu Kanike, Qingqing Liang, Fabio Alessio Marino, Francesco Carobolante
  • Patent number: 10355005
    Abstract: Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Daniel H. Morris, Ian A. Young, Stephen M. Ramey
  • Patent number: 10332819
    Abstract: A semiconductor device includes at least one first fin, a first contact plug, a first via, at least one second fin, at least one contact plug, and a second via. The first fin extends along a direction. The first contact plug overlaps the first fin and has a first width measured along the direction. The first via overlaps the first contact plug and has a first top surface. The second fin extends along the direction. The second contact plug overlaps the second fin and has a second width measured along the direction, in which the second width is greater than the first width. The second via overlaps the second contact plug and has a second top surface, in which an area the second top surface is greater than an area of the first top surface.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 25, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10332908
    Abstract: A semiconductor device includes a first channel layer and a second channel layer, each extending from an upper portion to a lower portion; and word lines stacked toward the upper portion from the lower portion, the word lines spaced apart from each other, the word lines each extending to surround the first channel layer and the second layer; a first lower select group surrounding a portion of the first channel layer that further protrudes toward the lower portion than the word lines; and a second lower select group surrounding a portion of the second channel layer that further protrudes toward the lower portion than the word lines.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10325899
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Patent number: 10312246
    Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
  • Patent number: 10311943
    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 4, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shiro Kamohara, Yasushi Yamagata, Takumi Hasegawa, Nobuyuki Sugii
  • Patent number: 10312335
    Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 4, 2019
    Assignee: Efficient Power Conversion Corporation
    Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
  • Patent number: 10312377
    Abstract: Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 4, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10312167
    Abstract: One or more additional sense terminals are added to discrete semiconductor packages, assemblies and semiconductor modules, including power semiconductor modules, to sense accurately the voltage between the gate and emitter/source of voltage-controlled chips, inside the package, assembly or module.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventor: Reinhold Bayerer
  • Patent number: 10304823
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10304968
    Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 28, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
  • Patent number: 10294420
    Abstract: A luminescent component comprises a first film comprising a first solid polymer composition and a second film comprising a second solid polymer composition. The first solid polymer composition comprises first luminescent crystals. The second solid polymer composition comprises second luminescent crystals. The first luminescent crystals are of size between 3 nm and 3000 nm, and emit red light in response to excitation by light with a shorter wavelength. The second luminescent crystals are of size between 3 nm and 3000 nm, and emit green light in response to excitation by light with a shorter wavelength. Said luminescent component is particularly suited for the application in LCD-backlight color conversion.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 21, 2019
    Assignee: AVANTAMA AG
    Inventors: Norman Albert Luchinger, Ines Weber, Stefan Loher, Marek Oszajca, Benjamin Hartmeier
  • Patent number: 10297578
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 21, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 10283511
    Abstract: A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: May 7, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Yi-Hung Li, Ming-Shan Lo, Cheng-Da Huang
  • Patent number: 10276458
    Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chia-Lin Liang, Chih-Ren Hsieh
  • Patent number: 10269985
    Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: April 23, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
  • Patent number: 10269814
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
  • Patent number: 10262746
    Abstract: A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 16, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Ying-Je Chen, Wei-Ren Chen, Wein-Town Sun
  • Patent number: 10263080
    Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Junjing Bao, Bin Yang, Lixin Ge, Yun Yue
  • Patent number: 10256160
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first gate structure on the first region and a second gate structure on the second region; forming a first spacer around the first gate structure; forming a first epitaxial layer adjacent to two sides of the first spacer; forming a buffer layer on the first gate structure; and forming a contact etch stop layer (CESL) on the buffer layer on the first region and the second gate structure on the second region.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10255980
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 9, 2019
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Wen-Hao Ching, Chen-Hao Po
  • Patent number: 10256150
    Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Liyang Song, Xinhui Wang, Qintao Zhang
  • Patent number: 10242998
    Abstract: A plurality of semiconductor layers have longitudinally a first direction, have a peripheral area surrounded by the plurality of control gate electrodes, and are arranged in a plurality of rows within the laminated body. A controller controls a voltage applied to the control gate electrodes and bit lines. The controller, during a writing operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first row closer to the insulation separating layer, and applies a second voltage larger than the first voltage to a second bit line connected to the semiconductor layer positioned in a second row positioned further from the insulation separating layer with respect to the first row, among the plurality of rows.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuhiro Shimura
  • Patent number: 10236284
    Abstract: A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well is formed in a surface portion of the semiconductor layer to isolate the element formation region. A field insulating film is formed on a surface of the semiconductor layer. The field insulating film surrounds the element formation region in an annular shape when viewed from a top. An interlayer insulating film is formed on the semiconductor layer. A wiring is formed on the interlayer insulating film. A conductive film is formed on the field insulating film.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: March 19, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Shusaku Fujie
  • Patent number: 10224323
    Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Johan Camiel Julia Janssens, Jaroslav Pjencak, Thierry Yao, Mark Griswold, Weize Chen
  • Patent number: 10222998
    Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10222997
    Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10211223
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 19, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Pieter Blomme
  • Patent number: 10211218
    Abstract: A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: February 19, 2019
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 10199279
    Abstract: A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junggun You, Sukhoon Jeong
  • Patent number: 10199390
    Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunwoo Lee, Sangwoo Lee, Changwon Lee, Jeonggil Lee
  • Patent number: 10192927
    Abstract: A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 29, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Mark Harold Clark, Natividad Vasquez, Steven Maxwell
  • Patent number: 10170196
    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu, Toru Tanzawa, Shigekazu Yamada, Koji Sakui
  • Patent number: 10163921
    Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10163641
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lee, Chiang-Ming Chuang, Kun-Tsang Chuang, Yung-Lung Hsu, Hsin-Chi Chen
  • Patent number: 10153359
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Shen-De Wang
  • Patent number: 10153296
    Abstract: A memory device includes a substrate and a stacked body arranged along a first direction. The stacked body includes electrode films. A configuration of an end portion in a second direction of the stacked body is a staircase configuration. Steps corresponding to the electrode films are formed in the staircase configuration. A first distance between a first step and an end edge of the stacked body in the second direction is shorter than a second distance between a second step and the end edge in the second direction. The first step is positioned at an end portion in a third direction of the stacked body. The second step is positioned at a central portion in the third direction of the stacked body. The first and second steps correspond to two of the electrode films positioned at the same level when counting along the first direction from the substrate side.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: December 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Naoyuki Iida, Hideki Inokuma, Naoki Yamamoto, Yoshihiro Yanai
  • Patent number: 10141327
    Abstract: According to an embodiment, a semiconductor memory device comprises: an insulating layer disposed on a semiconductor substrate; a plurality of memory cell arrays being arranged three-dimensionally on the insulating layer and including a plurality of conductive layers stacked in a first direction that intersects a surface of the semiconductor substrate; and a block insulating layer covering a side surface of one of the plurality of conductive layers. A high permittivity layer is provided between the insulating layer and a lowermost layer of the plurality of conductive layers. A permittivity of the high permittivity layer is much higher than that of the insulating layer.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Sonehara, Masaru Kito
  • Patent number: 10141322
    Abstract: A 3D NAND memory structure having improved process margin and enhanced performance is provided. Such a memory structure can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, a metal layer disposed between the control gate material and the floating gate material, an interpoly dielectric (IPD) layer disposed between the metal layer and the control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material coupled to the floating gate material opposite the control gate material.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Fatma A. Simsek-Ege, Nirmal Ramaswamy