With Floating Gate Electrode Patents (Class 257/315)
  • Patent number: 10811423
    Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
  • Patent number: 10794705
    Abstract: A system, computer-readable medium, and a method to operate a vehicle in a manner that minimizes a cost to travel from an origin to a destination that includes finding the input to a flight control system that minimizes direct operating cost. The approach described herein employs an energy state approximation (ESA).
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 6, 2020
    Assignee: General Electric Company
    Inventors: Reza Ghaemi, Eric Richard Westervelt, Mark Lawrence Darnell, David Lax
  • Patent number: 10797143
    Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Lee, Jeong Gil Lee, Do Hyung Kim, Ki Hyun Yoon, Hyun Seok Lim
  • Patent number: 10797064
    Abstract: A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: October 6, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chia-Jung Hsu
  • Patent number: 10784270
    Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 10783960
    Abstract: A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor is connected with a source line and a first program word line. The first floating gate transistor has a first floating gate. The first floating gate transistor is connected with the first select transistor and a first program bit line. The second select transistor is connected with the source line and a first read word line. The second floating gate transistor has a second floating gate. The second floating gate transistor is connected with the second select transistor and a first read bit line. The first floating gate and the second floating gate are connected with each other.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 22, 2020
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Ping-Yu Kuo
  • Patent number: 10784274
    Abstract: An integrated circuit memory cell includes a floating gate, a control gate, and a plurality of inter-poly dielectric (IPD) layers. The IPD layers include an IPD1 layer, an IPD2 layer, and an IPD3 layer, with the IPD2 layer interposed between the IPD1 and IPD3 layers. The IPD2 layer, which may be a nitride, does not flank the floating gate. Thus, no section of the floating gate is laterally between two sections of the IPD2 layer. Also, no section of the IPD2 layer of a first memory cell is between the floating gate of the first memory cell and a floating gate of an immediate adjacent memory cell of the same memory cell string. In some cases, an IPD4 layer is provided between the floating gate and the IPD3 layer. The IPD4 layer is relatively much thinner than layers IPD1-3 and may flank the floating gate, as may the IPD3 layer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Rahul Agarwal, Srivardhan Gowda, Krishna Parat
  • Patent number: 10777450
    Abstract: The present disclosure provides a semiconductor substrate. The semiconductor substrate includes a base, a plurality of mesas extending from an upper surface of the base, a plurality of protrusions connected to the mesas, an insulating layer disposed on the protrusions, a capping layer disposed on the insulating layer, and a passivation layer disposed on sidewalls of the protrusions, the insulating layer, and the capping layer. The passivation layer includes at least one first film and at least one second film arranged in a staggered configuration.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Chih-Wei Huang
  • Patent number: 10777561
    Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Sanjeev Sapra, Masihhur R. Laskar, Darwin Franseda Fan, Jerome A. Imonigie
  • Patent number: 10763272
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10756100
    Abstract: An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a second substrate region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the second substrate region, an electrically conductive control gate insulated from and disposed over a first channel portion of the channel region, an electrically conductive floating gate insulated from and disposed over a second channel portion of the channel region, an electrically conductive source line electrically connected to the second substrate region, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 25, 2020
    Assignee: GREENLIANT IP LLC
    Inventor: Bing Yeh
  • Patent number: 10756186
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory film is formed within each memory openings. A silicon-germanium alloy layer including germanium at an atomic concentration less than 25% is deposited within each memory opening. An oxidation process is performed on the silicon-germanium alloy layer. A vertical semiconductor channel including an unoxidized remaining material portion of the silicon-germanium alloy layer is formed, which includes germanium at an atomic concentration greater than 50%.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yangyin Chen, Christopher Petti
  • Patent number: 10756213
    Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min-hwa Chi, Ajey Jacob, Abhijeet Paul
  • Patent number: 10748964
    Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae-Yeon Lee
  • Patent number: 10748924
    Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jun Hyoung Kim
  • Patent number: 10734491
    Abstract: Memory devices might include an array of memory cells and a control logic to control access of the array of memory cells, where a memory cell of the array of memory cells might include a first dielectric adjacent a semiconductor, a control gate, a second dielectric between the control gate and the first dielectric, and a charge storage structure between the first dielectric and the second dielectric, wherein the charge storage structure comprises a charge-storage material and a gettering agent.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Rhett T. Brewer, Durai V. Ramaswamy
  • Patent number: 10727240
    Abstract: A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: July 28, 2020
    Assignee: Silicon Store Technology, Inc.
    Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
  • Patent number: 10720213
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Patent number: 10714489
    Abstract: A memory device with a memory cell and control circuitry. The memory cell includes source and drain regions formed in a semiconductor substrate, with a channel region extending there between. A floating gate is disposed over a first portion of the channel region for controlling its conductivity. A select gate is disposed over a second portion of the channel region for controlling its conductivity. A control gate is disposed over the floating gate. An erase gate is disposed over the source region and adjacent to the floating gate. The control circuitry is configured to perform a program operation by applying a negative voltage to the erase gate for causing electrons to tunnel from the erase gate to the floating gate, and perform an erase operation by applying a positive voltage to the erase gate for causing electrons to tunnel from the floating gate to the erase gate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Yuri Tkachev, Alexander Kotov, Nhan Do
  • Patent number: 10714582
    Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Ye Lu, Lixin Ge
  • Patent number: 10700077
    Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: June 30, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Mel Hymas, James Walls, Sonu Daryanani
  • Patent number: 10685885
    Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Jie Hong, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 10685971
    Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 16, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Chieh-Fang Chen, Jia-Rong Chiou
  • Patent number: 10685970
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Danny Pak-Chum Shum
  • Patent number: 10672794
    Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Fumihiro Kono
  • Patent number: 10670936
    Abstract: Process for forming a multi-layer electrochromic structure, the process comprising depositing a film of a liquid mixture onto a surface of a substrate, and treating the deposited film to form an anodic electrochromic layer, the liquid mixture comprising a continuous phase and a dispersed phase, the dispersed phase comprising metal oxide particles, metal hydroxide particles, metal alkoxide particles, metal alkoxide oligomers, gels or particles, or a combination thereof having a number average size of at least 5 nm.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: June 2, 2020
    Assignee: KINESTRAL TECHNOLOGIES, INC.
    Inventors: Hye Jin Choi, John David Bass, Eric Lachman, Daniel Mark Giaquinta, Howard W. Turner, Ellen Murphy
  • Patent number: 10665531
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a lateral transistor arranged in the front surface of the semiconductor substrate and having an intrinsic source, and a through substrate via. A first conductive layer lines side walls of the through substrate via and extends from the through substrate via onto the front surface of the semiconductor substrate and is electrically coupled with the intrinsic source of the lateral transistor.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum
  • Patent number: 10651378
    Abstract: Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10644012
    Abstract: A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 5, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
  • Patent number: 10644019
    Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
  • Patent number: 10636910
    Abstract: A semiconductor device is provided, which includes a substrate, a fin structure, a capping layer and an oxide layer. The substrate has a well. The fin structure extends from the well. The capping layer surrounds a top surface and side surfaces of the fin structure. The oxide layer is over the substrate and covers the capping layer. A thickness of a top portion of the oxide layer above the capping layer is greater than a thickness of a sidewall portion of the oxide layer.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10636867
    Abstract: A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xinshu Cai, Shyue Seng Tan, Juan Boon Tan, Danny Pak-Chum Shum
  • Patent number: 10608001
    Abstract: A nonvolatile memory device includes a plurality of unit cells. Each of the plurality of unit cells includes a first active region disposed in a substrate to extend in a first direction, a floating gate extending in a second direction to cross over the first active region, a first selection gate disposed to be adjacent to a first side surface of the floating gate to cross over the first active region, a second selection gate disposed to be adjacent to a second side surface of the floating gate opposite to the first selection gate to cross over the first active region, a first dielectric layer disposed between the floating gate and the first selection gate, and a second dielectric layer disposed between the floating gate and the second selection gate.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix system ic Inc.
    Inventor: Kwang Il Choi
  • Patent number: 10600797
    Abstract: An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 24, 2020
    Assignee: GREENLIANT IP LLC
    Inventor: Bing Yeh
  • Patent number: 10601417
    Abstract: A switching circuit includes a printed circuit board that supports a switching element, a positive power supply circuit, a negative power supply circuit and a driving circuit thereon. The positive power supply circuit generates a positive voltage relative to a GND potential. The negative power supply circuit generates a negative voltage relative to the GND potential. The driving circuit supplies the gate electrode with the positive voltage and the negative voltage when turn on and off the switching element, respectively. The printed circuit board includes wiring as a conducting path extended from the negative power supply circuit to the gate electrode via the driving circuit. The conducting path includes a negative power supply wiring between the negative power supply circuit and the driving circuit. The negative power supply wiring at least partially includes a negative power supply solid pattern.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 24, 2020
    Assignee: DENSO CORPORATION
    Inventors: Yosuke Watanabe, Tomotaka Suzuki
  • Patent number: 10593685
    Abstract: A semiconductor device includes a semiconductor layer having a main surface, a gate insulating film including a thin film portion forming a tunnel window, a thick film portion formed around the thin film portion and having a thickness larger than a thickness of the thin film portion, and an inclined portion connecting the thin film portion and the thick film portion and inclined upward from the thin film portion toward the thick film portion, and covering the main surface of the semiconductor layer, a memory gate structure formed on the thin film portion of the gate insulating film, and a select gate structure formed on the thick film portion of the gate insulating film.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Toshiyuki Kanaya, Tsuyoshi Hosono
  • Patent number: 10593675
    Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 17, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 10586797
    Abstract: A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-hoon Kim, Hong-soo Kim
  • Patent number: 10553597
    Abstract: A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hsien Chen, Liang-Tai Kuo, Hau-Yan Lu, Chun-Yao Ko
  • Patent number: 10553596
    Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: February 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiangzheng Bo, Douglas Tad Grider, III, John MacPeak
  • Patent number: 10546860
    Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 28, 2020
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Jin-Woo Han, Yuniarto Widjaja
  • Patent number: 10541248
    Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang
  • Patent number: 10522551
    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Hsien Huang, Ching-Cheng Lung, Yu-Tse Kuo, Chang-Hung Chen, Shu-Ru Wang, Wei-Chi Lee, Chun-Yen Tseng
  • Patent number: 10522460
    Abstract: A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 31, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Daigo Ichinose, Shigehiro Yamakita
  • Patent number: 10522545
    Abstract: An integrated circuit device includes a substrate, first and second fin-type active areas which extend in a first direction on the substrate, first and second gate lines on the substrate that extend in a second direction that crosses the first direction, and first and second contact structures. The first and second gate lines intersect the first and second fin-type active areas, respectively. The first contact structure is on the first fin-type active area at a side of the first gate line and contacts the first gate line. The second contact structure is on the second fin-type active area at a side of the second gate line. The first contact structure includes a first lower contact including metal silicide and a first upper contact on the first lower contact. The second contact structure includes a second lower contact including metal silicide and a second upper contact on the second lower contact.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-yup Chung
  • Patent number: 10522563
    Abstract: A semiconductor device includes a first channel layer and a second channel layer, each extending from an upper portion to a lower portion; and word lines stacked toward the upper portion from the lower portion, the word lines spaced apart from each other, the word lines each extending to surround the first channel layer and the second layer; a first lower select group surrounding a portion of the first channel layer that further protrudes toward the lower portion than the word lines; and a second lower select group surrounding a portion of the second channel layer that further protrudes toward the lower portion than the word lines.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 31, 2019
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10510902
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Patent number: 10509169
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Chang Chang, Chung-Yen Chou, Ming-Chyi Liu, Shih-Chang Liu
  • Patent number: 10504910
    Abstract: A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 10, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Reynaldo V. Villavelez, Paul I. Mikulan