With Floating Gate Electrode Patents (Class 257/315)
  • Patent number: 11569266
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Patent number: 11557599
    Abstract: A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongha Shin, Yohan Lee
  • Patent number: 11538825
    Abstract: Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is selectively removed. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is selectively removed.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 27, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Xiaofen Zheng, Hongbin Zhu, Lixun Gu, Hanwei Yi
  • Patent number: 11532716
    Abstract: A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen Yang Hsueh, Ling Hsiu Chou, Chih-Yang Hsu
  • Patent number: 11527493
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a first metal plug, a second metal plug, a third metal plug, and a fourth metal plug over a semiconductor substrate; forming an energy removable liner covering the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing an etching process to remove a portion of the energy removable layer from the substrate, while remaining an energy removable block between the first metal plug and the second metal plug in the cell region; forming a dielectric layer covering the energy removable block and the first metal plug, the second metal plug, the third metal plug, and the fourth metal plug; performing a thermal treating process to transform the energy removable layer into a first air gap structure including a first air gap enclosed by liner layer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 13, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tzu-Ching Tsai
  • Patent number: 11521850
    Abstract: A method for manufacturing a semiconductor device according to an, exemplary embodiment of the present disclosure includes: forming a semiconductor layer on a substrate in a chamber; and forming a semiconductor layer on a substrate in a chamber. Forming the insulation layer includes: (a) injecting precursors that include a metal into a surface of the semiconductor layer; (b) removing precursors that are not adsorbed; (c) injecting reactants onto the surface of the semiconductor layer; and (d) removing residual reactants. The semiconductor layer includes a semiconductor material that has a layered structure.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: December 6, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jun Hyung Lim, Hyung Jun Kim, Sun Hee Lee, Seung Gi Seo, Whang Je Woo
  • Patent number: 11522052
    Abstract: A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Jin Ha Kim
  • Patent number: 11495282
    Abstract: Drivers for sense amplifiers are disclosed. A driver may include two or more drain areas extending in a first direction and two or more source areas extending in the first direction. The driver may also include a drain interconnection including two or more first drain-interconnection portions which extend in the first direction above the two of more drain areas and one or more second drain-interconnection portions extending in a second direction between the two or more first drain-interconnection portions. The driver may also include a source interconnection including two or more first source-interconnection portions extending in the first direction above the two or more source areas and one or more second source-interconnection portions extending in the second direction between the two or more first source-interconnection portions. Associated systems are also disclosed.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Mamoru Nishizaki
  • Patent number: 11488665
    Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 1, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11488958
    Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 1, 2022
    Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
  • Patent number: 11488970
    Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: November 1, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Boolean Fan, Nhan Do
  • Patent number: 11488975
    Abstract: A semiconductor structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces and located over a substrate, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces, and memory opening fill structures extending through the alternating stacks. A contact via assembly is provided, which includes a first conductive via structure vertically extending from a top surface of one of the first electrically conductive layers through a subset of layers within the second alternating stack and through the second retro-stepped dielectric material portion, an insulating spacer located within an opening through the subset of layers, and a second conductive via structure laterally surrounding the insulating spacer and contacting a second electrically conductive layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yuji Totoki, Fumitaka Amano
  • Patent number: 11476276
    Abstract: A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: October 18, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Guan-Ru Lee
  • Patent number: 11424340
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Patent number: 11424254
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 23, 2022
    Assignee: WInbond Electronics Corp.
    Inventors: Hsin-Huang Shen, Yu-Shu Cheng, Yao-Ting Tsai
  • Patent number: 11423979
    Abstract: Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 23, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
  • Patent number: 11387246
    Abstract: A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yonghoon Son
  • Patent number: 11384428
    Abstract: Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 12, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Mang-Mang Ling, Thomas Kwon, Jong Mun Kim, Chentsau Chris Ying
  • Patent number: 11380699
    Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Guangyu Huang, Haitao Liu
  • Patent number: 11367731
    Abstract: A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 11367486
    Abstract: Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Patent number: 11355397
    Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 7, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Akhila Mallavarapu, Jaydeep Kulkarni, Michael Watts, Sanjay Banerjee
  • Patent number: 11342429
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark T. Ramsbey, Kuo Tung Chang, Sameer S. Haddad, James Pak
  • Patent number: 11329077
    Abstract: The present technology relates to a semiconductor device, a solid-state imaging device, and electronic equipment, which are able to suppress increase of resistivity to a high level at a connection portion between an ESV and a wiring layer and to improve reliability of an electric connection using an ESV. The semiconductor device according to the present technology has a plurality of semiconductor substrates layered, and includes a through electrode penetrating a silicon layer of the semiconductor substrates, a wiring layer formed inside the semiconductor substrates, and a through electrode reception part. The through electrode reception part is connected to the wiring layer, in which the through electrode has a width smaller than the through electrode reception part, and the through electrode is electrically connected to the wiring layer via the through electrode reception part. The present technology is applicable, for example, to a CMOS image sensor.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 10, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshiya Hagimoto
  • Patent number: 11329127
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 11329215
    Abstract: According to one embodiment, a magnetic memory device includes a substrate, a first layer stack, and a second layer stack at a same side of the first layer stack relative to the substrate, and farther than the first layer stack from the substrate. Each of the first and second layer stack includes a reference layer, a tunnel barrier layer provided in a direction relative to the reference layer, the direction being perpendicular to the substrate, a storage layer provided in the direction relative to the tunnel barrier layer, and a first nonmagnetic layer provided in the direction relative to the storage layer. A heat absorption rate of the first nonmagnetic layer of the first layer stack is lower than a heat absorption rate of the first nonmagnetic layer of the second layer stack.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 10, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuya Sawada, Young Min Eeh, Eiji Kitagawa, Taiga Isoda, Tadaaki Oikawa, Kenichi Yoshino
  • Patent number: 11316024
    Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: April 26, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing, Nhan Do
  • Patent number: 11309263
    Abstract: The present disclosure provides a semiconductor device structure with an air gap structure and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive contact and a second conductive contact disposed over a semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive contact and the second conductive contact, and a second dielectric layer disposed over the first conductive contact, the second conductive contact and the first dielectric layer. The first dielectric layer is separated from the semiconductor substrate by a first air gap structure, the first dielectric layer is separated from the second dielectric layer by a second air gap structure, and the air gap structures reduce capacitive coupling between conductive features.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tzu-Ching Tsai
  • Patent number: 11309331
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 19, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 11302827
    Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a tunneling insulating layer disposed over the substrate, a floating gate disposed over the tunnel oxide layer, a lateral oxidized intervention layer disposed over the floating gate, and a control gate disposed over the dielectric layer. The lateral oxidized intervention layer comprises a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 12, 2022
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Te-Yin Chen
  • Patent number: 11295803
    Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 5, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
  • Patent number: 11289508
    Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 29, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wenyu Hua, Fandong Liu, Zhiliang Xia
  • Patent number: 11289163
    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Benben Li, Akira Goda, Ramey M. Abdelrahaman, Ian C. Laboriante, Krishna K. Parat
  • Patent number: 11282575
    Abstract: In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yo-Han Lee
  • Patent number: 11282559
    Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Reika Tanaka, Masumi Saitoh, Takashi Maeda, Rieko Funatsuki, Hidehiro Shiga
  • Patent number: 11270980
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 11270763
    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 11270952
    Abstract: A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending into the semiconductor strip, wherein a plurality of metal structures and a plurality of via structures stack over the dielectric structure to form a seal ring structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Shan Wang, Shun-Yi Lee
  • Patent number: 11257832
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 22, 2022
    Assignee: Kioxia Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
  • Patent number: 11251088
    Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Long-Jie Hong, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 11251192
    Abstract: A semiconductor device includes a vertical stack of gate electrodes. The gate electrodes extend in different lengths to provide contact regions. The gate electrodes have a conductive region and an insulating region. Contact plugs fills contact holes that pass through the stack of gate electrodes in the contact regions. The contact plugs are connected to the gate electrodes. The contact plugs pass through a conductive region of one gate electrode and are electrically connected to the one gate electrode and pass through the insulating region of other gate electrodes in the contact region. The insulating region is disposed outside of the contact holes in a region in which the gate electrodes intersect the contact plugs.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: So Hyeon Lee
  • Patent number: 11251301
    Abstract: A semiconductor device structure for a vertical field effect transistor comprises a substrate with a shallow trench isolation (STI) region. A lower source/drain area is formed on the STI region with a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin. The third semiconductor fin is formed to couple the first semiconductor fin to the second semiconductor fin across the lower source/drain area. The STI region that is beneath the lower source/drain area comprises opposing sidewall portions curved in opposing directions. In one example the lower source/drain area is formed only at an intersection between the STI region and one or more of the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin. In other example, the second semiconductor fin is disposed parallel to the first semiconductor fin and together with the third semiconductor fin resulting in an H-shaped structure from a top-down view.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Tsung-Sheng Kang, Ruilong Xie, Tao Li, Alexander Reznicek
  • Patent number: 11239242
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Mohd Kamran Akhtar, Silvia Borsari, Alex J. Schrinsky
  • Patent number: 11239166
    Abstract: A semiconductor memory device includes a cell region defined with vertical channels which pass through electrode layers and interlayer dielectric layers alternately stacked; a step region disposed adjacent to the cell region in a first direction, and defined with contacts coupled to the electrode layers extending in different lengths; a first opening passing through the electrode layers and the interlayer dielectric layers in the step region; a second opening passing through the electrode layers and the interlayer dielectric layers in the cell region; under wiring lines coupled with a peripheral circuit defined on a substrate; top wiring lines disposed over the electrode layers and the interlayer dielectric layers, and coupled with the contacts; and vertical vias coupling the under and top wiring lines, wherein the vertical vias include first vertical vias which pass through the first opening and second vertical vias which pass through the second opening.
    Type: Grant
    Filed: May 16, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong Hwan Kim, Jin Ho Kim, Byung Hyun Jun, Chang Woon Choi
  • Patent number: 11239181
    Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Rohit Kothari, Lifang Xu, Jian Li
  • Patent number: 11222854
    Abstract: Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mihir Bohra, Tarun Mudgal
  • Patent number: 11217300
    Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 4, 2022
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja, Zvi Or-Bach
  • Patent number: 11211330
    Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 28, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11205653
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11200923
    Abstract: A semiconductor apparatus includes a first chip that generates a first oscillator signal in response to a detection enable signal and activates a ZQ circuit in response to a ZQ enable signal, and a second chip generates the ZQ enable signal by comparing frequencies of the first oscillator signal and a second oscillator signal with each other in response to the detection enable signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: December 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Ku, Sung Soo Chi