With Floating Gate Electrode Patents (Class 257/315)
  • Patent number: 11114569
    Abstract: The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 7, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11114459
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takaaki Iwai, Hirofumi Tokita, Yoshitaka Otsu, Fumiaki Toyama, Yuki Mizutani
  • Patent number: 11100988
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Tsuneo Inaba, Hiroyuki Takenaka, Akihiko Chiba
  • Patent number: 11101290
    Abstract: A method for manufacturing a semiconductor memory device includes forming a first polysilicon layer on a conductive layer, forming a second polysilicon layer stacked on the first polysilicon layer, and forming a third polysilicon layer stacked on the second polysilicon layer. In the method, a stacked structure of the first, second and third polysilicon layers is patterned into a plurality of stacked structures spaced apart from each other on the conductive layer. Ferroelectric dielectric layers are formed on respective second polysilicon layers of the plurality of stacked structures, and metal layers are formed on the ferroelectric dielectric layers.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari
  • Patent number: 11101325
    Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 24, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
  • Patent number: 11075211
    Abstract: A semiconductor device includes a semiconductor substrate including a first region for a nonvolatile memory cell and a second region that is formed outside the first region and in which a semiconductor element differing from the nonvolatile memory cell is formed, a plurality of first element separating portions by which the first region and the second region are electrically separated from each other, a second element separating portion that is formed in the first region and that partitions the first region into a plurality of active regions, and a dummy region formed adjacently to a first portion that is one, which is closest to the first region, of the plurality of first element separating portions, and, in the semiconductor device, the first portion of the first element separating portion is equivalent in width to the second element separating portion.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: July 27, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Minoru Sogawa
  • Patent number: 11069628
    Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 20, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Mathieu Lisart
  • Patent number: 11062745
    Abstract: Some embodiments relate to a sense amplifier. The sense amplifier includes a fully-depleted silicon on insulator (FDSOI) substrate, including a handle substrate region, an insulator layer over the handle substrate region, and a device region over the insulator layer. An n-well region is disposed in the handle substrate region, and an n-well contact region extends from the n-well region through the insulator layer to an upper surface of the device region. A pair of pull-down transistors are disposed in the device region and over the n-well. The pair of pull-down transistors have their respective gates coupled to a pair of complementary bitlines, respectively, and coupled to the n-well through the n-well contact region.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sing-Kai Huang, Charles Chew-Yuen Young, Jack Liu
  • Patent number: 11056348
    Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 6, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Jeremy Alfred Theil
  • Patent number: 11049556
    Abstract: An electronic device includes a semiconductor memory comprising column lines, row lines crossing the column lines, memory cells located at intersections between the column lines and the row lines, dummy insulating patterns located adjacent to the memory cells, liner layers formed on sidewalls of the memory cells, and dummy liner layers formed on sidewalls of the dummy insulating patterns.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Young Sam Lee
  • Patent number: 11043507
    Abstract: A semiconductor device structure comprises blocks having substantially uniform pitch laterally-extending throughout a first region, a second region laterally-neighboring the first memory region, and a third region laterally-neighboring the second region; memory strings longitudinally-extending through a first portion of the blocks located in the first region; pillar structures longitudinally-extending through a second portion of the blocks located in the second region; conductive contacts longitudinally-extending through a third portion of the blocks located in the third region; and conductive line structures electrically coupled to and laterally-extending between the memory strings and the conductive contacts. Each of the blocks comprises tiers, each tier comprising a conductive structure and an insulating structure longitudinally-neighboring the conductive structure. Semiconductor devices and electronic systems are also described.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Eric N. Lee
  • Patent number: 11031408
    Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell disposed on the semiconductor substrate. The nonvolatile memory cell includes a field-effect transistor for data writing, and a field-effect transistor for data readout that is adjacent to the field-effect transistor for data writing. Each of the field-effect transistor for data writing and the field-effect transistor for data readout includes a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and diffusion layers configuring a source region and a drain region on respective sides of the floating gate viewed in the thickness direction of the semiconductor substrate. The thickness of the gate insulating film of the field-effect transistor for data readout, and the thickness of the gate insulating film of the field-effect transistor for data writing, are different.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 8, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Taku Shibaguchi
  • Patent number: 11024388
    Abstract: Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the access line voltage to an access line coupled to a plurality of memory cells, generating a voltage level for the access line voltage in response to its target voltage level and generating a voltage level for gating the access line voltage to the access line in response to the target overdrive voltage level, and applying the access line voltage to the access line while applying the voltage level for gating the access line voltage to a control gate of a string driver connected to the access line.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Guanglei An, Qiang Tang
  • Patent number: 10998017
    Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: May 4, 2021
    Assignee: Etron Technology, Inc.
    Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
  • Patent number: 10998424
    Abstract: A method of forming a vertical metal-air transistor device is provided. The method includes forming a precursor stack with a stack template on the precursor stack on a substrate. The method further includes forming a bottom spacer on the substrate around the precursor stack, and depositing a liner casing on the precursor stack. The method further includes depositing a conductive gate layer on the bottom spacer and liner casing. The method further includes reducing the size of the stack template to form a template post on the precursor stack, and forming a stack cap on the template post and precursor stack.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 10991429
    Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroyuki Ogawa, Fumiaki Toyama, Takuya Ariki
  • Patent number: 10991691
    Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Sheng Fan, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 10978467
    Abstract: A SONOS nonvolatile memory includes a second gate structure of a selectron isolated from a first gate structure of a memotron by an inter-gate dielectric isolation layer formed on a first side of the first gate structure through self-alignment. The second gate structure is formed on a first side of the inter-gate dielectric isolation layer through self-alignment. A cell structure is formed by two adjacent cell structures. A first window defines an area formed by the two first gate structures. Two sides of each first gate structure are defined through self-alignment by first top silicon nitride layers formed on inner sides of the first window. First silicon nitride spacers are formed on second sides of the first gate structures through self-alignment. The bottom area of a contact hole between the second sides of the first gate structures is defined through self-alignment by the two first silicon nitride spacers.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 13, 2021
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Kegang Zhang, Hualun Chen
  • Patent number: 10971519
    Abstract: A non-volatile memory structure including a substrate, a stacked structure, a conductive pillar, a channel layer, a charge storage structure, and a second dielectric layer is provided. The stacked structure is disposed on the substrate and has an opening. The stacked structure includes first conductive layers and first dielectric layers alternately stacked. The conductive pillar is disposed in the opening. The channel layer is disposed between the stacked structure and the conductive pillar. The charge storage structure is disposed between the stacked structure and the channel layer. The second dielectric layer is disposed between the channel layer and the conductive pillar. The non-volatile memory structure can effectively improve the electrical performance and the reliability of the memory device.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 6, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Zih-Song Wang, Chen-Liang Ma
  • Patent number: 10964709
    Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 10962501
    Abstract: A floating gate based sensor apparatus includes at least two separate electrical bias components with respect to a floating gate based sensor surface within the floating gate based sensor apparatus. By including the at least two electrical bias components, the floating gate based sensor apparatus provides enhanced capabilities for biomaterial and non-biomaterial detection and manipulation while using the floating gate based sensor apparatus.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 30, 2021
    Assignee: Cornell University
    Inventors: Krishna Jayant, Edwin C. Kan
  • Patent number: 10964687
    Abstract: A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 30, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prahbu
  • Patent number: 10964370
    Abstract: A Provided is a semiconductor storage element that includes a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 30, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masanori Tsukamoto
  • Patent number: 10950614
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Patent number: 10937786
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10916417
    Abstract: A pre-processing method, a method for forming a metal silicide and a semiconductor processing apparatus are disclosed by the present invention. In the pre-processing method, a plasma etching process is performed on a semiconductor structure including a substrate. A first conductive portion and an isolation spacer covering a side surface of the first conductive portion are formed on a surface of an active area in the substrate. In the plasma etching process, a bias voltage applied to a surface of the semiconductor structure is adjusted by adjusting power outputs of two RF sources and is not lower than 150 V. In the metal silicide formation method, after a semiconductor structure including a first conductive portion and a second conductive portion is pre-processed in the manner as described above, a metal film is deposited thereon and annealed to result in the formation of the metal silicide.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 9, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hsien Huang, Xiaodong Liu, Jian-Zhi Fang, Chen-Hao Liu
  • Patent number: 10910393
    Abstract: A memory device comprises a plurality of stacks of word lines alternating with insulating strips, the stacks being separated by trenches, the word lines extending in a first direction. A plurality of columns of vertical conductive structures is disposed in the trenches between adjacent stacks. Multi-layer films of memory material and channel material are disposed on sidewalls of word lines on at least one side of the trenches between adjacent vertical conductive structures in the plurality of vertical conductive structure, the channel material in ohmic contact with the vertical conductive structures. At locations of vertical conductive structures in the plurality of vertical conductive structures, the sidewalls of the word lines are recessed between insulating strips in the stacks to form recesses on the sidewalls of the word lines to isolate the word lines from vertical conductive structures.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 2, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10898618
    Abstract: Amorphous SiOx (SiO2), SiONx, silicon nitride (Si3N4), surface treatments are provided, on both metal (titanium) and non-metal surfaces. Amorphous silicon-film surface treatments are shown to enhance osteoblast and osteoblast progenitor cell bioactivity, including biomineral formation and osteogenic gene panel expression, as well as enhanced surface hydroxyapatite (HA) formation. A mineralized tissue interface is provided using the amorphous silicon-based surface treatments in the presence of osteoblasts, and provides improved bone cell generation/repair and improved interface for secure attachment/bonding to bone. Methods for providing PEVCD-based silicon overlays onto surfaces are provided. Methods of increasing antioxidant enzyme (e.g., superoxide dismutase) expression at a treated surface for enhanced healing are also provided.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 26, 2021
    Assignees: THE TEXAS A&M UNIVERSITY SYSTEM, BOARD OF REGENTS, UNIVERSITY OF TEXAS SYSTEM, UT-BATTELLE, LLC
    Inventors: Venu Varanasi, Pranesh Aswath, Megen Maginot, Nickolay V. Lavrick
  • Patent number: 10896911
    Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 19, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsu-Chi Cho, Cheng-Ta Yang
  • Patent number: 10892341
    Abstract: A flash memory with assistant gates, including two floating gates disposed on a substrate, an insulating layer formed on the two floating gates and the substrate, an assistant gate disposed between the two floating gates, wherein a portion of the assistant gate wraps around the two floating gates, and two select gates disposed respectively outside the two floating gates and partially overlap the two floating gates.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hann-Jye Hsu, Cheng-Yuan Hsu
  • Patent number: 10892265
    Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: January 12, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chi-Min Chen, Yung-Tai Hung, Tuung Luoh, Ta-Hung Yang, Kuang-Chao Chen
  • Patent number: 10892266
    Abstract: A nonvolatile memory structure includes a substrate, a select transistor, and a floating-gate transistor. The substrate includes an oxide defined (OD) region and an erase region. The select transistor is disposed on the OD region, and the floating-gate transistor is disposed on the OD region between the select transistor and the erase region, wherein the floating gate has an extended portion capacitively coupled to the erase region, and the extended portion has an extending direction parallel to a first direction. The OD region further has an addition region protruding in a second direction and partially overlapped with the floating gate, in which the second direction is vertical to the first direction.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 12, 2021
    Assignee: eMemory Technology Inc.
    Inventor: Wein-Town Sun
  • Patent number: 10879259
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Patent number: 10876998
    Abstract: A biologically sensitive field effect transistor includes a substrate, a first control gate and a second control gate. The substrate has a first side and a second side opposite to the first side, a source region and a drain region. The first control gate is disposed on the first side of the substrate. The second control gate is disposed on the second side of the substrate. The second control gate includes a sensing film disposed on the second side of the substrate. A voltage biasing between the source region and the second control gate is smaller than a threshold voltage of the second control gate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 29, 2020
    Inventors: Yu-Jie Huang, Jui-Cheng Huang, Cheng-Hsiang Hsieh
  • Patent number: 10876157
    Abstract: Disclosed are insulated nanoelectrode associated with nanopores, useful in macromolecular analysis devices. Also disclosed are related methods of fabrication and use.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 29, 2020
    Assignee: The Trustees of the University of Pennsylvania
    Inventors: Marija Drndic, Ken Healy, Vishva Ray, Lauren J. Willis, Neil Peterman, John Bartel
  • Patent number: 10879247
    Abstract: Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 10872839
    Abstract: A method includes doping a substrate with a dopant to form a first well region of a first core circuit and a second well region of a second core circuit; forming first and second semiconductor fins respectively over the first and second well regions and extending along a direction; forming a first gate stack across the first semiconductor fin and a second gate stack across the second semiconductor fin; forming a first source/drain adjoining the first semiconductor fin and a second source/drain adjoining the second semiconductor fin; and forming a first contact over the first source/drain and having a first width measured along the direction and a second contact over the second source/drain and having a second width measured along the direction, wherein the second width of the second contact is greater than the first width of the first contact.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10868031
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
  • Patent number: 10868023
    Abstract: A non-volatile memory array includes gate structures disposed on a substrate, each of the gate structures including a tunneling oxide layer positioned on the substrate, a floating gate positioned on the tunneling oxide layer and being arranged along a first direction on the tunneling oxide layer, sidewall gates disposed on sidewalls of the floating gate, extending in the first direction and being spaced apart from each other, and a gate dielectric layer interposed between the floating gate and the sidewall gates, bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gates, a drain region positioned in an upper portion of the substrate, the drain region overlapping, and being electrically connected to, the one of the bit lines, and a source line positioned between adjacent sidewall gates, the source line extending in the first direction and being buried in the substrate.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 15, 2020
    Assignee: DB HITEK CO., LTD.
    Inventor: Jun Ho Lee
  • Patent number: 10868039
    Abstract: A manufacturing method of a semiconductor device is provided. The method includes forming a sacrificial layer with different material layers, and etching the sacrificial layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Byung Woo Kang
  • Patent number: 10860923
    Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Borna J. Obradovic, Titash Rakshit, Mark S. Rodder
  • Patent number: 10854602
    Abstract: A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chii-Horng Li, Chien-I Kuo, Lilly Su, Chien-Chang Su, Ying-Wei Li
  • Patent number: 10847228
    Abstract: In a method of programming in a nonvolatile memory device, a memory block including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively. A boosting operation is performed to boost voltages of channels of the plurality of stacks while controlling the switching operation of the intermediate switching transistors during a program operation with respect to the memory block. Program voltage disturbance and pass voltage disturbance are reduced through control of the switching operation of the intermediate switching transistors.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yo-Han Lee
  • Patent number: 10847225
    Abstract: Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 24, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Sonu Daryanani, Matthew G. Martin, Gilles Festes
  • Patent number: 10840261
    Abstract: A semiconductor storage device includes a base portion, a stacked body, and a first column. The base portion includes a substrate, a semiconductor element on the substrate, lower-layer wiring above the semiconductor element, and a first conductive layer above the lower-layer wiring and made of a metal compound or polycrystal silicon. The stacked body is above the first conductive layer. The stacked body includes second conductive layers and insulating films stacked alternately. The first column includes a semiconductor body and a memory film. The semiconductor body extends in a stacked direction of the stacked body and is electrically connected to the first conductive layer. A memory film has a charge trap between the plurality of second conductive layers and the semiconductor body. The first conductive layer is provided between the stacked body and the lower-layer wiring, and between a peripheral region of the stacked body and the lower-layer wiring.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Ito, Ken Komiya, Tsuneo Uenaka
  • Patent number: 10833095
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 10, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Patent number: 10818804
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Szu-Hsien Lu, Yu-Chu Lin
  • Patent number: 10818692
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 27, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 10818761
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Patent number: 10818369
    Abstract: A semiconductor circuit of the disclosure includes: a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 27, 2020
    Assignee: Sony Corporation
    Inventor: Keizo Hiraga