Transient voltage suppressor manufactured in silicon on oxide (SOI) layer
A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P−/P+ substrate layer disposed above the insulator layer.
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1. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacturing a transient voltage suppressor (TVS). More particularly, this invention relates to an improved circuit configuration and method of manufacturing TVS in a silicon-on-insulator (SOI) layer for providing TVS protection with low capacitance.
2. Description of the Relevant Art
The conventional technologies for designing and manufacturing transient voltage suppressor (TVS) are still confronted with certain technical difficulty. Particularly, when the TVS is formed with multiple PN junctions diodes in a semiconductor substrate by applying standard CMOS processing steps, there are inherent PNP and NPN parasitic transistors. In an ESD event or the occurrence of a transient voltage, with a larger voltage applied to this TVS array, the parasitic NPN or PNP transistors are turned on and latched up. The latch-up may cause sudden and strong voltage snapback. The sudden and large snapback may cause the undesired effects of system instability or even damages. Additionally, the latch-up of the parasitic NPN or PNP transistors in the TVS array may further lead to other unexpected or undesirable voltage-current transient conditions. The technical difficulties caused by the parasitic capacitance and parasitic PNP or NPN latch-up in a device implemented with the TVS protection cannot be easily resolved.
Generally, the transient voltage suppressors (TVS) are commonly applied to protecting integrated circuits from damages due to the inadvertent occurrence of an over-voltage imposed onto the integrated circuit. An integrated circuit is designed to operate over a normal range of voltages. However, in situations such as electrostatic discharge (ESD), electrical fast transients and lightning, an unexpected and uncontrollable high voltage may accidentally strike onto the circuit. The TVS devices are required to serve the protection functions to circumvent the damages that are likely to occur to the integrated circuits when such over-voltage conditions occur. As increasing numbers of devices are implemented with the integrated circuits that are vulnerable to over-voltage damages, demands for TVS protection are also increased. Exemplary applications of TVS can be found in the USB power and data line protection, digital video interface, high-speed Ethernet, notebook computers, monitors and flat panel displays.
With the advancement of electronic technologies, there are increasingly more devices and applications that require TVS diode array for ESD protection, particularly for protecting high bandwidth data buses. Referring to
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved TVS circuits that can effectively and conveniently reduce the capacitance and also prevent the parasitic PNP/NPN transistor latch-up.
SUMMARY OF THE PRESENT INVENTIONIt is therefore an aspect of the present invention to provide a new and improved device structure to implement a TVS in the SOI structure to reduce the parasitic capacitance and to prevent the latch-up of the parasitic PNP-NPN transistors such that the above-discussed difficulties and limitations encountered by the conventional TVS array can be overcome.
Another aspect of the present invention is to form the TVS protective circuit in the SOI layer. The lateral distance between adjacent diodes can be reduced without the concerns of parasitic capacitance and inadvertent latch-up.
Briefly in a preferred embodiment this invention discloses a transient voltage-suppressing (TVS) device supported on a semiconductor substrate. The TVS device includes a clamp diode functioning with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer. In another specific exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P−/P+ substrate layer disposed above the insulator layer.
The present invention further discloses a method for manufacturing an electronic device with an integrated transient voltage-suppressing (TVS) device. The method includes a step of manufacturing the TVS array in a semiconductor substrate by forming a silicon layer above an insulator as a silicon on insulator (SOI) layer and forming a clamping diode to function with high-side and low-side diodes for clamping a transient voltage of said electronic device in the SOI layer. In an exemplary embodiment, the process of forming the insulation layer further includes a step of forming a thick body oxide layer in the semiconductor substrate. In a specific embodiment, the BOX layer is formed by forming a thick oxide layer on top surface of P− wafers then bonding and fusing the oxide layers of two wafers face to face together then lapping the substrate to a desired thickness. In another specific embodiment, the method further includes a step of deep dopant implanting the semiconductor substrate to convert a P− substrate layer above the BOX layer into a P+ layer.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.
The low/high side diodes can be formed in a different area of die during the same process on the same substrate 105 with a BOX layer 110 including an optional P−/P+ substrate layer 120.
In order to improve the voltage clamping, a bipolar NPN transistor is implemented in an exemplary embodiment between the N+ cathode dopant region 140, the PW 130 and the N+ dopant region 165 to replace diode as main clamping element shown in
Referring to
Referring to
Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
Claims
1. A transient voltage suppressing (TVS) device supported on a semiconductor substrate comprising:
- a clamp element functioning with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of said semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device.
2. The TVS device of claim 1 wherein:
- said insulator layer further comprising a thick body oxide (BOX) layer.
3. The TVS device of claim 1 wherein:
- said insulator layer further comprising a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts.
4. The TVS device of claim 1 wherein:
- said clamp element further surrounded by a P-well.
5. The TVS device of claim 1 wherein:
- said clamp element further surrounded by a P-well on top of a P−/P+ substrate layer disposed above said insulator layer.
6. The TVS device of claim 1 wherein:
- said clamp element further comprising a Zener diode.
7. The TVS device of claim 6 wherein:
- said Zener diode further comprising a graded doping region.
8. The TVS device of claim 1 wherein:
- said clamp element further comprising a bipolar transistor triggered by a diode.
9. The TVS device of claim 8 wherein:
- said bipolar transistor further comprising extending emitter region for enlarging the base region by providing deeper carrier injection for increases the high current handling capability.
10. The TVS device of claim 1 wherein:
- said insulator layer further comprising a thin layer of Silicon Implant Oxide (SIMOX).
11. The TVS device of claim 1 further comprising:
- heavily doped sinkers to insulate the clamp element from other functional devices.
12. The TVS device of claim 1 further comprising:
- dielectric material filling trenches to insulate the clamp element from other functional devices.
13. A method for manufacturing an electronic device with an integrated transient voltage-suppressing (TVS) device comprising:
- manufacturing the TVS device in a semiconductor substrate by forming a silicon layer above an insulator as a silicon on insulator (SOI) layer and forming a clamping diode to function with high-side and low-side diodes for clamping a transient voltage of said electronic device in the SOI layer.
14. The method for claim 13 wherein:
- the process of forming the insulation layer further includes a step of forming a thick body oxide layer in the semiconductor substrate.
15. The method for claim 13 wherein: the process of forming the insulation layer further includes a step of forming a thick body oxide layer in the semiconductor substrate by forming a thick oxide layer on top surface of P-wafers then bonding and fusing the oxide layers of two wafers face to face together then lapping the substrate to a desired thickness.
16. The method for claim 13 further comprising:
- deep dopant implanting the semiconductor substrate to convert a P−substrate layer above the BOX layer into a P+layer.
Type: Application
Filed: Nov 1, 2007
Publication Date: May 7, 2009
Applicant:
Inventor: Shekar Mallikarjunaswamy (San Jose, CA)
Application Number: 11/982,557
International Classification: H01L 27/06 (20060101); H01L 21/8222 (20060101);