METHODS AND SYSTEMS FOR CONTROLLING ACCUMULATION OF ELECTRICAL CHARGE DURING SEMICONDUCTOR ETCHING PROCESSES

Abstract

A method and system are provided for controlling the accumulation of electrical charge during a semiconductor plasma etching process performed in a plasma etching chamber. The bias voltage supplied to the plasma etching chamber is modulated by a bias power modulation circuit to control the accumulation of electrical charge and to force the accumulated electrical charge to be periodically discharged at a controlled rate of discharge that prevents the wafer from being damaged.

Description

TECHNICAL FIELD OF THE INVENTION

The invention relates to semiconductor fabrication processes. More particularly, the invention relates to controlling the buildup of electrical charge during etching processes that can result in damage to the semiconductor device and to the equipment used to perform the etching process.

BACKGROUND OF THE INVENTION

Plasma etching processes are widely used in the manufacturing of semiconductor devices to form patterns or structures in the semiconductor devices. Semiconductor devices are used in a wide variety of consumer products, including, for example, television sets, radios, computers, as well as in other types of equipment and products, such as biochips used for modern medical laboratory tests and optical components such as light gratings and multiplexers used in the communications industry.

In order to improve the performance of products and equipment that incorporate semiconductor devices and to reduce their costs, the geometries of structures or patterns formed in semiconductor devices are rapidly decreasing in size due to the development of new semiconductor process technologies. These structures or patterns are normally defined on a layer of photoresist by using a semiconductor process known as photolithography. After the photolithography process has been performed, a plasma etching process is used to transfer the patterns or structures onto a wafer substrate. Typically, multiple other layers (e.g., dielectric layers, metal layers, etc.) are deposited onto the wafer substrate and the photolithography and etching processes are performed to form additional structures such as, for example, interconnections (i.e., window metal plugs), local or global connections (i.e., metal runners), transistor gates, resistors and/or shallow trench isolation (STI) structures.

As attempts are continuously being made to achieve higher performance-to-cost ratios, an ever-increasing number of such layers are being integrated on top of the wafer surface. Consequently, photolithography and plasma etching processes are being used more frequently and therefore are becoming larger parts of the overall wafer manufacturing process. Most of the dielectric and metal etching processes are performed at or near the end of the total wafer manufacturing cycle, where structures on wafer become very dense. Therefore, any defect or damage in the wafer that occurs during the etching processes will have a much more significant impact on the total manufacturing process and product yield than a defect or damage in the wafer that occurs during other front-end processes, such as during implantation and various thermal processes.

Charge-induced damage occurring during plasma etching processes is the most frequent type of damage that occurs during the semiconductor manufacturing process. Because of the rapid reduction in the geometries of structures and patterns being formed in semiconductor devices, it has become extremely important to be able to achieve anisotropic etching profiles during plasma etching processes. In order to achieve anisotropic plasma etching profiles, an electrical direct current (dc) bias field is introduced in the plasma etching process chamber to drive the etching chemical compounds in a desired direction toward the surface to be etched with a momentum that will result in the desired anisotropic etching profile being formed in the surface. The plasma environment is created in the chamber by an electric field produced by radio frequency (RF) radiation.

With the existence of this electrical dc bias field in the RF generated plasma environment, some exposed surfaces in the plasma chamber will only be exposed to positively charged ions and others will only be exposed to negatively charged ions or electrons. Most of the chamber parts that are exposed to the plasma are built of or coated with non-conductive isolation material, such as a ceramic material or quartz. The wafer may have many layers of dielectric material and a non-conductive top photoresist layer used to define the patterns or structures in the wafer. Consequently, net charges often accumulate on some of the interior surfaces of the chamber and on the wafer surfaces. When the electrical potential from these accumulated charges becomes sufficiently large, an uncontrolled discharge, i.e., arcing, will occur in the chamber. A rapid uncontrolled discharge of the accumulated charges can cause damage to the wafer and/or to chamber parts. Damage to the wafer can result in one or more of the semiconductor devices formed on the wafer being defective, and therefore unusable, which reduces yield. Damage to the chamber can result in improper operations during the etch process that can lead to defects being formed in wafers during the etch process.

The plasma etching process can be described in three main sequences: (1) a wafer loading step is performed during which a wafer having a patterned layer of photoresist on it is loaded into the plasma etching chamber and the chamber is prepared for etching; (2) sequential plasma etching steps are performed during which different materials in sub-layers of the wafer are targeted to transfer the pattern from the patterned layer photoresist to the sub-layers of the wafer; and (3) a wafer unloading step is performed to retrieve the processed wafer from the plasma etching chamber. The aforementioned charge-induced damage can occur in any of these three steps. Rapid discharge of accumulated charge, or arcing, will occur whenever the electric field associated with the accumulated charge is sufficiently greater than the dielectric strength of the material to cause dielectric breakdown to occur in the material, resulting in electrical paths being formed in the material. Rapid discharge of accumulated charge, or arcing, will also occur whenever an electrical path is formed in the material due to some electrical short circuit being formed as a result of mechanical movement during the loading or unloading of the wafer.

FIG. 1 illustrates a block diagram of a known plasma etching chamber 2. The chamber 2 has a negative bias power terminal 3 and a bias power ground terminal 4. During the plasma etching process, a negative dc voltage that is held at a fixed, i.e., constant, level is supplied to terminal 3 by a power supply (not shown) and the bias power ground terminal 4 is held at a low voltage level of 0 volts. The chamber 2 has a bottom plate 5 electrically coupled to the negative bias power terminal 3 and a top plate 6 electrically coupled to the bias power ground terminal 4. The bottom plate 5 is positioned on a chuck 18, which may be either an electrical static wafer chuck or a mechanical wafer chuck. The surface 7 represents the surface of the electrical static chuck or of the mechanical wafer chuck.

The wafer comprises a substrate 8, one or more sub-layers 9 to be etched and a patterned layer 11 of photoresist. The opening 12 in the photoresist layer 11 represents an opening in the patterned photoresist layer 11 through which positively charged ions will bombard the sub-layer 9 to achieve an anisotropic etch of the sub-layer 9. The plus signs in the circles 19 represent positively charged ions of the plasma etching compound and the negative signs in the circles 21 represent negatively charged ions or electrons of the plasma in the chamber. The smaller plus and minus signs 16 represent positively charged ions and electrons, respectively, being pushed away from or toward layer 11.

The chamber 2 is shown superimposed on a graph that demonstrates the relationship between spatial position in the vertical direction in the chamber and corresponding potentials at certain spatial positions. The RF field is generated by a separate RF power supply (not shown) and fed through a separate RF feed (not shown) or through the bias power terminal 3 to generate the plasma. The potentials V1, V2, V3, V4, V6, and V9 shown in FIG. 1 correspond to key voltage potentials that result from the combined dc bias electrical field and RF-generated plasma electrical field. The surface charges on the wafer layers 8, 9 and 11 are distributed according to these electrical fields.

Once the negative bias voltage has been turned on, the plate 5 is at the bias potential V1. If the chamber incorporates a mechanical wafer chuck, the plate 5 is directly on the mechanical chuck and the wafer substrate 8 is sitting on the chuck surface. Therefore, in that case, the wafer substrate 8 and the wafer chuck are at the same bias potential. For such a configuration, the electrical potentials V2 and V3 are the same and are equal to the bias potential V1 due to the fact that wafer substrate 8 is normally conductive. The electrical potential V4 is the potential at the upper surface of the layer 9.

Once plasma is ignited and maintained by the RF power fed into the chamber 2, the plasma within the chamber can be classified into three main regions; (1) a first dark region 13; (2) an equilibrium region 14, and (3) a second dark region 15. The first dark region 13 is an electron-starved region due to the negative bias potential. The electrons generated by the RF electrical field in this region are quickly pushed away by the bias electrical field in a direction from the plate 5 toward the plate 6. In this region, the chance of charge recombination is very small, and there is very little charge collision due to the unidirectional movement of positively charged ions driven by the bias field. Consequently, the associated photo-luminescent light emission is very weak in this region. Hence, this region is typically referred to as the first dark region.

The first dark region 13 is extremely important for achieving an anisotropic etching profile. The potential V6 corresponds to the potential at the boundary of the first dark region 13 and the equilibrium region 14. The positively charged ions 19 are further accelerated by the first dark region potential V6 to gain kinetic energy. This kinetic energy provides the ions with sufficient physical momentum to penetrate the surface of the material being etched, layer 9, in a desired direction to create an anisotropic etching profile.

The equilibrium region 14 contains an equal amount of positively charged ions and electrons. Most of the active charge exchanges occur in this region. The active charge exchange results in photo-luminescent light emission and high temperature. The light emitted in this region can be detected to determine when the etching process has been completed. The second dark region 15 near the plate 6 is an electron-rich region and behaves like the first dark region 13, except that the region 15 contains mostly negatively charged ions and electrons. The potential V9 corresponds to the potential at the boundary of the second dark region 15 and the equilibrium region 14.

Charges on the surfaces of the wafer layers 9 and 11 come from two main sources; specifically, (1) direct incoming positively charged ions from the dark region 13, and (2) secondary generated electrical charges in photoresist layer 11. Electrical “charge”, as that term is used herein, is intended to denote any one of: (1) an electron, (2) a negatively charged ion, and (3) a positively charged ion. The positively charged ions from the dark region 13 land on and accumulate in either the photoresist layer 11 and/or in wafer surface layer 9. The secondary generated charges in photoresist layer 11 can result when kinetically-energized positively charged ions impact the photoresist layer 11 causing ionization of photoresist molecules. Once photoresist molecules have become ionized, any negatively charged ions or electrons will be pushed away from photoresist layer 11 upward into the chamber as illustrated in FIG. 1 due to the electrical field established by the negative bias potential. On the other hand, any positively charged ions in the photoresist layer 11 will be attracted to the lower surface of photoresist layer 11 due to the electrical field established by the negative bias potential.

Arcing on the wafer is mostly determined by the difference between the potentials V4 and V3. The potential V4 is proportional to the buildup of electrical charge on the upper surface of layer 9 and on the lower surface of photoresist layer 11. The direct consequence of a rise in the potential V4 or charge accumulation on these surfaces is a decrease in the potential difference V6-V4 and an increase in the potential difference V4-V3. The decreasing potential difference V6-V4 will reduce kinetic energy of the positively charged ions of the etching compound, and thus will make the etching profile less anisotropic and will reduce the etching rate. The increase in the potential difference V4-V3 can result in an uncontrolled discharge of accumulated electrical charge, i.e., arcing, that can cause damage to the wafer.

The technique that is most commonly used for controlling the accumulation of charge during the plasma etching process involves lowering the DC bias power voltage level and the RF power level during the etching process. This technique, however, typically results in a compromise in the etching profile and/or a sacrifice in etching efficiency. Another technique for controlling the accumulation of charge during the plasma etching process is disclosed in U.S. Pat. No. 6,914,007. This patent describes a sequence of three process steps for discharging the wafer before the plasma etching process begins. By discharging the wafer prior to the plasma etching process, it is less likely that a sufficient amount of charge will accumulate during the plasma etching process to cause a rapid discharge to occur during the etching process. This patent does not, however, provide a solution to the problem of discharge damages caused by the use of high plasma etching rates during the etching process.

The rate of charge accumulation is determined primarily by equipment design and process setup. Other important factors that are determinative of the rate of charge accumulation are the charge distribution or local charge density on the wafer, which has a relation to the wafer pattern designs, including the pattern designs on metal sub-layers. This is because of the “antenna effect”, which is a phenomenon that can generally be described as follows: a larger capacitor will collect more charge than a smaller capacitor, and any sharp point will create a much stronger electrical field than that which is created by a flat surface. The wafer design is generally an unknown variable and is changed from time to time by most wafer manufacturers. Due to the large uncertainty of the charge buildup and distribution on the wafer caused by the antenna effect, it is extremely difficult to achieve a stable balance among, on one hand, controlling discharge, and on the other, maintaining an adequate etch profile and etch efficiency. As a result, even with well-tuned plasma etching process configurations, semiconductor manufacturers commonly find that approximately 1% to 2% of wafers experience discharge damage.

With the ongoing trend of geometry sizes decreasing and pattern density increasing, the tolerance of semiconductor devices to charge buildup is becoming weaker. Therefore, the need to control charge accumulation during the plasma etching process is becoming increasingly important. Accordingly, a need exists for a method and system for controlling charge accumulation during the plasma etching process.

SUMMARY OF THE INVENTION

The invention provides a system and method for controlling the accumulation of electrical charges on a wafer located in a plasma etching chamber during a plasma etching process. The system comprises bias supply voltage control circuitry and bias power modulation circuitry. The bias supply voltage control circuitry is configured to provide a supply voltage that alternates at a selected frequency between a first supply voltage level and a second supply voltage level. The bias power modulation circuitry is configured to receive the alternating first and second supply voltage levels and to bias the plasma etching chamber at first and second bias voltage levels in response to receiving the first and second supply voltage levels, respectively.

The method comprises: placing a wafer in a plasma etching chamber, applying an RF electrical field and a bias electrical field to the chamber, modulating the bias electrical field between a first bias voltage level and a second bias voltage level, and, after the etching process has been completed, removing the wafer from the chamber.

In accordance with another embodiment, the invention is directed to a system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process. The system comprises a chamber into which a wafer to be etched is loaded and etching process control circuitry. The chamber has first and second bias voltage terminals that are at first and second bias potentials, respectively. The etching process control circuitry is configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged at least one time during the plasma etching process.

These and other features and advantages of the invention will become apparent from the following description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a known plasma etching chamber.

FIG. 2 illustrates a block diagram of a plasma etching system equipped with a bias power modulation circuit in accordance with an illustrative embodiment of the invention.

FIG. 3 illustrates timing diagrams for the potentials V1, V4 and V4-V3 shown in FIG. 2.

FIG. 4 illustrates a block diagram of the apparatus of the invention in accordance with an illustrative embodiment for controlling the bias power modulation circuit.

FIG. 5 illustrates a flowchart that represents the method in accordance with an illustrative embodiment.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

The invention provides a method and system for controlling the accumulation of electrical charge during a semiconductor plasma etching process performed in a plasma etching chamber. In accordance with the invention, the bias voltage supplied to the plasma etching chamber is modulated by a bias power modulation circuit to control the accumulation of electrical charge and to force the accumulated electrical charge to be periodically discharged at a controlled rate of discharge that prevents the wafer from being damaged. The manner in which this is accomplished in accordance with an illustrative embodiment will now be described with reference to FIGS. 2-5.

FIG. 2 illustrates a block diagram of a plasma etching system 100 equipped with a bias power modulation circuit 110 in accordance with an illustrative embodiment of the invention. The system 100 includes a chamber 101 that has a negative bias power terminal 102 and a bias ground terminal 103 electrically coupled to it. Reference numerals 105, 107-109, 111-115, 118, 119, and 121 shown in FIG. 2 represent elements or symbols that are identical to or similar to elements or symbols 5, 7-9, 11-15, 18, 19, and 21, respectively, shown in FIG. 1. Therefore, a description of the elements or symbols represented by reference numerals 105, 107-109, 111-115, 118, 119, and 121 shown in FIG. 2 will not be provided in the interest of brevity.

In order to control the above-mentioned charge buildup on the wafer and chamber surfaces to prevent or help mitigate the resulting degradation of the etching profile and etching rate, the bias power modulation circuit 110 provides a modulated negative bias power rather than the typically fixed or constant dc negative bias power used by the known chamber configuration shown in FIG. 1. In accordance with this illustrative embodiment, the bias power modulation circuit 110 is made up of a diode 131, a resistor 132 and an inductor 133. The bias power modulation circuit 110 may also include a capacitor 134, which is optional, as described below in more detail. Prior to describing the operations of the bias power modulation circuit 110, the manner in which the accumulation of charge is controlled will be described with reference to FIG. 3.

FIG. 3 illustrates timing diagrams 151, 152 and 153 for the potentials V1, V4 and the potential difference V4-V3, respectively, as a function of time. The manner in which the bias power modulation circuit 110 operates to control the discharge of accumulated charge will now be described with reference to these timing diagrams. Prior to time t=0, a wafer to be etched is loaded into the chamber 101. Prior to time t=0, neither the negative bias power supply nor the RF power supply have been turned on. Starting at time t=0, some small negative bias voltage, V_MIN, is applied to the terminal 102 to provide electric static wafer chucking in the event that an electric static wafer chuck is used in the chamber 101. This is indicated by the portion of the timing diagram labeled with the reference numeral 161. If a mechanical wafer chuck is used in the chamber 101, a potential of zero volts is typically applied to the terminal 102 at this time.

The RF power is then turned on (not shown) and the plasma is ignited and maintained in the chamber 101. At this time, respective electrons or positively charged ions generated by the plasma in the chamber 101 are automatically attracted to the wafer surface to neutralize the respective positive or negative charges on the wafer surface, depending on the charge type that the wafer initially carries. After a sufficient amount of time has passed to ensure full wafer neutralization, the bias power supply is turned on at time t=t1, where t1 is some instant in time that occurs after time t=0. This causes the required negative bias voltage, V_MAX, to be applied to terminal 102. The required negative bias voltage will depend on the corresponding etch process steps being performed as specified in an etch recipe. Persons skilled in the art will understand the manner in which the required negative bias voltage is determined based on the particular etch process and etch recipe.

During the time period when the bias power supply is on, which is labeled T_ON in FIG. 3, the V_MAX is being applied to the terminal 102. During this time period, the etching process is occurring and charges are being accumulated on the wafer and chamber surfaces. After some predetermined etch time that depends on several factors (e.g., the etch recipe, the tolerance level of the etch process to charge buildup, the charge buildup rate, etc.), the bias power supply is turned off at time t2 such that the aforementioned small negative bias voltage or zero voltage level, V_MIN, is again applied to the terminal 102. The portion of the timing diagram 151 labeled with reference numeral 165 indicates the return to this minimum or zero bias voltage. The bias power supply remains in this state for a predetermined time period, T_OFF.

At the end of the T_OFF time period, at time instant t=t3, the negative bias power supply is again turned on, causing V_MAX to be applied to terminal 102. The portion of the V1 waveform 151 indicated by reference numeral 167 corresponds to the application of V_MAX to the terminal 102 at the end of the T_OFF time period. This process of modulating the bias power supply between V_MAX and V_MIN in this periodic manner preferably is repeated throughout the entire etching process, i.e., from the point in time when etching is performed on the wafer for the first time since being loaded into the chamber 101 to the point in time when the final etching has been completed and the wafer is ready to be unloaded from the chamber 101. Thus, when V_MAX is being applied to terminal 102, etching is occurring and charge is building on the wafer surface and interior surfaces of the chamber 101, whereas when V_MIN is being applied to terminal 102, charge that has accumulated on the wafer and interior surfaces of the chamber 101 is being discharged in a controlled manner, as will now be described.

The changes in the V1 waveform 151 result in changes in the V4 waveform 152 and in the V4-V3 waveform 153, as will now be described with reference to the vertical lines labeled “a”, “b”, “c”, “d” and “e” in FIG. 3. The vertical lines labeled “a”, “b”, “c”, “d” and “e” represent sequential instants in time occurring during each discharge cycle. The rate at which accumulated charge is discharged to prevent arcing from occurring is governed by the operations of the diode 131, the resistor 132 and the inductor 133 of the bias power modulation circuit 110. At time instant “a”, the bias power supply is turned off, which causes the bias power supply voltage to drop to V_MIN. This causes the diode 131 to be reversely biased such that no electrical discharge current passes through the diode 131, which forces the discharge current to pass through resistor 132 and inductor 133. At the beginning of the T_OFF period (i.e., at time instant “a”), the inductor 133 has a high impedance due to high frequency components contained in the voltage potential across the resistor 132 and inductor 133. These high frequency components are caused by the fast shift in the bias supply voltage level from V_Max to V_MIN. The high impedance of the inductor 133 at the beginning of the T_OFF period limits the amount of discharge current that can pass through the inductor 133.

Over time, the impedance of the inductor 133 decreases as the high frequency components attenuate, until the impedance eventually reaches a level that is close to zero at time instant “d”. At time instant “d”, this low impedance of the inductor 133 allows the discharge current to pass through the inductor 133, and so the resistor 132 becomes the predominant component that limits the amount of discharge current that is allowed to pass through the path containing the resistor 132 and inductor 133. During the transitions from time instant “a” to time instant “d”, the positively charged ions on the wafer surfaces and chamber interior surfaces are being neutralized by the electrons and negatively charged ions in the plasma. Consequently, the potential V1 is dropping during the T_OFF period until it reaches V_MIN, which occurs at time instant “d”. Due to V1 being at this low potential at this instant in time, the value of the resistance needed for the resistor 132 is relatively small because the amount of discharge current that it is limiting at this time is relatively small. Thus, the inductor 133 prevents a surge in the discharge current from occurring at the beginning of the discharge cycle due to the inductor 133 having a very high impedance at that time, whereas the resistor 132 limits the smaller discharge current toward the end of the discharge cycle due to the inductor 133 having a low impedance at that time. The combination of the resistor 132 and inductor 133 provides a discharge network that controls the rate of discharge over the entire discharge cycle.

The discharge from the wafer surface actually begins at time instant “b”, which is the instant in time at which the wafer surface potential V4 shifts from negative to positive to allow the electrons in the plasma to be attracted to the wafer surface to neutralize the positive charges on the wafer surface. This shift is represented by point 171 on the V4 waveform 152. At this instant in time, the rate of change of the potential difference V4-V3 switches from a positive rate of change to a negative rate of change, and remains constant until time instant “d”, as indicated by the negative slope of the portion 181 of the waveform 153 extending from point 179 to point 183 on the waveform 153. The delay in the discharge beginning from time instant “a” to time instant “b” is mainly due to the impedance of the inductor 133. The total time duration of the discharge cycle is T_OFF, which starts at time instant “a” and ends at time instant “e”, although the actual discharge occurs from time instant “b” to time instant “e”.

At time instant “e”, the bias power supply is turned on again causing V_MAX to be applied to the terminal 102. Thus, time instant “e” also corresponds to the beginning of the T_ON time period, during which etching occurs. At this time instant, the diode 131 becomes forwardly biased and the discharge network comprising the resistor 132 and inductor 133 is shunted by the diode 131, thereby allowing the current to bypass the path containing the resistor 132 and the inductor 133 and pass through the path containing diode 131. The portion 167 of the V1 waveform 151 indicates a shift from V_MIN to V_MAX that is almost instantaneous at the end of the T_OFF cycle and the beginning of the T_ON cycle. Therefore, the time period during which etching occurs, T_ON, starts at time instant “e” in one cycle and ends at time instant “a” in the next cycle. Generally, some small amount of etching may continue to occur between time instant “a” and time instant “b” due to the fact that the plate 105 (FIG. 2) is still negatively biased between time instants “a” and “b”.

FIG. 4 illustrates a block diagram of the apparatus 200 of the invention in accordance with an illustrative embodiment for controlling the bias power modulation circuit 110. In accordance with this embodiment, the apparatus 200 comprises a control logic unit (CLU) 210, a memory element 220 and a bias power supply 215. The combination of the apparatus 200 and the bias power modulation circuit may be viewed as etching process control circuitry that controls the entire etching process as well as the process of discharging charge from the wafer. The modulation of the bias power supply between T_OFF and T_ON preferably occurs intermittently throughout the entire wafer etching process from just after a wafer has been loaded into the chamber 101 until just after the etching process has ended and the RF electrical field has been removed, prior to the wafer being removed from the chamber. The T_OFF and T_ON parameters are programmable and are part of the etch recipe, which is output from the computer (not shown) that controls the plasma etching equipment and sent to the CLU 210. The CLU 210 causes the parameters contained in the etch recipe, including the T_ON and T_OFF parameters, to be stored in the memory element 220. If the etch recipe changes, a new etch recipe containing the new T_ON and T_OFF parameters will be output to the CLU 210, which will then replace the current T_ON and T_OFF parameters stored in the memory element 220 with the new T_ON and T_OFF parameters of the new recipe. The memory element 220 may also store other settings, parameters, such as, but not limited to V_MIN and V_MAX, and/or instructions that are used by the CLU 210 to control the modulation of the bias supply voltage 215. For example, if the CLU 210 performs the modulation algorithm in software, software code may be stored in the memory element 220 or in some other computer-readable medium.

The CLU 210 outputs a control signal to the bias power supply 215 that causes the bias power supply 215 to operate to provide V_MIN during the T_OFF cycle and to output V_MAX during the T_ON cycle. As shown in FIG. 4, one of the output terminals of the bias power supply 215 is connected to the terminal labeled 102 of the bias power modulation circuit 110. The other output terminal of the bias power supply 215 is connected to the terminal labeled 103 of the chamber 101. The modulation of the bias power supply 215 preferably is synchronized to the recipe steps in such a way that there will be at least one discharge cycle, T_OFF, preceding the entire plasma etch process and one discharge cycle following the entire plasma etch process. The value of T_ON is variable for different etch steps within an etch recipe, whereas the value of T_OFF will typically remain constant over different etch recipes, although this is not a requirement of the invention. The value of T_ON is typically a function of the wafer charge tolerance level, which is primarily determined by the dielectric film thickness, by the geometry and pattern of the dielectric layer, and by the wafer surface charge buildup rate, which is generally proportional to the RF power and V_MAX.

Therefore, the entire plasma etch process will typically start with a discharge cycle after the wafer is loaded into the chamber 101 and will typically end with a discharge cycle before the wafer is unloaded from the chamber 101. Typically, at least a few discharge cycles will occur during the performance of all of the plasma etch steps specified in the recipe, depending on the length and plasma intensity of the process setup.

For an etch process that does not use an endpoint detector to determine when the process has been completed based on the luminescence detected in the chamber 101, it is rather simple to programmably set the T_OFF and T_ON parameters throughout the entire etch process, as described above with reference to FIG. 4. For etch processes that use an endpoint detector to determine when etch steps have been completed, the discharge cycles should be allocated by the CLU 210 so that a complete discharge cycle occurs just before the endpoint detector is activated and so that the subsequent T_ON cycle is terminated when indicated by the endpoint detector. Alternatively, the T_ON value should be set to be sufficiently long to ensure that the end of the T_ON cycle does not occur before the endpoint detector determines that the etch process has been completed.

The CLU 210 may be any type of computational device and may be made up solely of hardware or of a combination of hardware and software or firmware. Examples of suitable computational devices include microprocessors, microcontrollers, logical gate arrays, programmable logic arrays, etc. The memory element 220 may be any type of memory element, including, for example, solid state memory elements such as random access memory (RAM) elements, read only memory (ROM) elements, programmable ROM (PROM) memory elements, erasable PROM (EPROM) memory elements, flash memory devices, etc., as well as magnetic memory elements, such as magnetic disk and magnetic tape devices.

With reference again to FIG. 2, the negative bias terminal 102 and the bias power modulation circuit 110 provide the feed-in to the system 100 for the bias power. The system 100 will also have a feed-in for the RF power needed to generate the plasma in the chamber 101. Currently, known plasma etching systems such as that shown in FIG. 1 are constructed to either have an RF power feed-in that is separate from the bias power feed-in or to have a common feed-in that is used for both the RF power and the bias power. If the system 100 is constructed to have a feed-in for the RF power that is separate from the feed-in for the bias power, the capacitor 134 may be viewed as representing the parasitic capacitance attributed by the diode 131 and other components (not shown). In this case, the parasitic capacitance should be minimized to achieve better discharge current control performance. If the system 100 is constructed so that the feed-in 102, 110 is to function as the feed-in for both RF power and bias power, the capacitor 134 is a real capacitor used to electrically couple the RF power into the etch chamber 101. For such configurations of the system 100, the capacitor 134 should be selected to be large enough to couple the RF power without unacceptable power loss and small enough to prevent a discharge current surge at the beginning of the discharge cycle.

FIG. 5 illustrates a flowchart that represents the method in accordance with an illustrative embodiment. A wafer is placed in the etch chamber, as indicated by block 301. The etch recipe may be placed in the CLU 210 (FIG. 4), before or after the wafer is been placed in the chamber. Typically, the etch recipe is loaded into the CLU 210 prior to the wafer being placed in the chamber. After the wafer has been placed in the chamber, the bias voltage is modulated between V_MAX and V_MIN in accordance with the T_ON and T_OFF values while the RF electrical field is applied, as indicated by block 303. During T_ON time periods, the plasma etches the wafer. During the T_OFF time periods, the discharge of accumulated charge occurs and etching is briefly paused. As indicated above, at the beginning of the RF electrical field being applied to cause the plasma to be produced, preferably at least one discharge cycle will occur to cause any charge that has accumulated on the wafer and/or on the interior surfaces of the chamber as a result of a previous etching process or loading/unloading of a wafer to be discharged.

After the etching process has been performed, the RF and bias electrical fields are removed, as indicated by block 305. The invention is not limited with respect to the order in which the RF electrical field and the bias electrical field are removed. The wafer is then removed from the chamber, as indicated by block 307. As indicated above, preferably at least one discharge cycle (T_OFF) occurs after the etching process has ended and before the RF electrical field has been removed.

It should be noted that the invention has been described above with reference to etch processes that negatively bias the lower plate 105 (FIG. 2) to cause positively charged ions in the plasma to bombard the wafer and thereby etch the wafer. This is because most, if not all, plasma etching processes currently being used today etch in this fashion, i.e., by using positively charged ions to bombard the wafer. However, it is possible to positively bias the lower plate 105 so that negatively charged ions in the plasma to bombard the wafer and thereby etch the wafer. The modulation apparatus and method described above with reference to FIGS. 2-5 would also be applicable to such a system, as will be understood by those skilled in the art in view of the description provided herein. Those skilled in the art will understand the manner in which the bias power modulation circuit 110 shown in FIG. 2 may be modified is necessary to provide waveforms that are similar to those shown in FIG. 3, but generally reversed in polarity, for achieving the T_ON and T_OFF cycles.

It should be noted that the invention has been described with reference to a few illustrative embodiments for the purposes of demonstrating the principles and concepts of the invention. The invention, however, is not limited to these illustrative embodiments. Persons skilled in the art will understand in view of the description provided herein, that many modifications and variations may be made to the embodiments described herein without deviating from the scope of the invention. For example, the invention has been described with reference to a particular circuit configuration for the bias power modulation circuit 110 shown in FIG. 2. Persons skilled in the art will understand that a variety of circuit configurations may be used to provide a suitable discharge circuit for controlling the rate at which accumulated charge is discharged, and that the invention is not limited to using the configuration of the bias power modulation circuit 110 shown in FIG. 2.

Claims

1. A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:

bias supply voltage control circuitry configured to provide a supply voltage that alternates at a selected frequency between a first supply voltage level and a second supply voltage level; and

bias power modulation circuitry configured to receive the alternating first and second supply voltage levels and to bias the plasma etching chamber at first and second bias voltage levels in response to receiving the first and second supply voltage levels, respectively.

2. The bias supply voltage control circuitry comprising:

a control logic unit (CLU) electrically coupled to a bias power supply, the CLU being configured to generate a control signal that is provided to the bias power supply, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output the first supply voltage level if the control signal is in the first state and to output the second supply voltage level if the control signal is in the second state.

3. The system of claim 2, wherein the CLU is configured to alternate the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period, and wherein when the control signal is maintained at the first state for the first time period, the bias power modulation circuit provides the first bias voltage level to the chamber for a third time period, and wherein when the control signal is maintained at the second state for the second time period, the bias power modulation circuit provides the second bias voltage level to the chamber for a fourth time period.

4. The system of claim 3, wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period.

5. The system of claim 3, wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency.

6. The system of claim 5, wherein the selected frequency is part of an etch recipe that is loaded into the CLU from a computer that controls the plasma etching process.

7. The system of claim 6, wherein the fourth time period corresponding to the etching cycle is variable for different etching steps of a same recipe and wherein the third time period corresponding to the discharge cycle generally remains constant over different etch recipes.

8. The system of claim 1, wherein when the bias power modulation circuit provides the first bias voltage level to the chamber, accumulated electrical charges on one or more surfaces of the wafer are discharged from the chamber at a controlled discharge rate, the controlled discharge rate being determined by the configuration of the bias power modulation circuitry.

9. The system of claim 8, wherein the bias power modulation circuit is configured with a discharge network comprising one or more resistors and one or more inductors that together limit the discharge of accumulated charge to provide the controlled discharge rate.

10. A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:

a control logic unit (CLU), the CLU being electrically coupled to a bias power supply and being configured to generate a control signal that is provided to the bias power supply, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output a first supply voltage level if the control signal is in the first state and to output a second supply voltage level if the control signal is in the second state; and

a bias power modulation circuit, the bias power modulation circuit being electrically coupled to the bias power supply and to a bias voltage terminal of the etching chamber, the bias power modulation circuit receiving the first supply voltage level output from the bias power supply when the control signal is in the first state and receiving the second supply voltage level output from the bias power supply when the control signal is in the second state, wherein when the bias power modulation circuit receives the first supply voltage level, the bias power modulation circuit provides a first bias voltage level to the chamber via the bias voltage terminal, and wherein when the bias power modulation circuit receives the second supply voltage level, the bias power modulation circuit provides a second bias voltage level to the chamber, wherein when the bias power modulation circuit provides the first bias voltage level to the chamber, accumulated electrical charges on one or more surfaces of the wafer are discharged from the chamber.

11. The system of claim 10, wherein the CLU is configured to alternate the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period, and wherein when the control signal is maintained at the first state for the first time period, the bias power modulation circuit provides the first bias voltage level to the chamber for a third time period, and wherein when the control signal is maintained at the second state for the second time period, the bias power modulation circuit provides the second bias voltage level to the chamber for a fourth time period.

12. The system of claim 11, wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period.

13. The system of claim 11, wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency.

14. A method for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the method comprising:

placing a wafer in a plasma etching chamber;

applying a radio frequency (RF) electrical field and a bias electrical field to the chamber;

modulating the bias electrical field between a first bias voltage level and a second bias voltage level; and

after the etching process has been completed, removing the wafer from the chamber.

15. The method of claim 14, wherein modulating the bias electrical field between a first bias voltage level and a second bias voltage level comprises:

with bias supply voltage control circuitry, supplying a supply voltage that alternates at a selected frequency between a first supply voltage level and a second supply voltage level; and

with bias power modulation circuitry, receiving the alternating first and second supply voltage levels and biasing the plasma etching chamber at the first and second bias voltage levels in response to receiving the first and second supply voltage levels, respectively.

16. The method of claim 15, further comprising:

with a control logic unit (CLU) of the supply voltage control circuitry, generating a control signal; and

in a bias power supply of the supply voltage control circuitry, receiving the control signal, the control signal having at least a first state and a second state, the control signal causing the bias power supply to output the first supply voltage level if the control signal is in the first state and to output the second supply voltage level if the control signal is in the second state.

17. The method claim 16, further comprising:

with the CLU, alternating the control signal between the first and second states at a selected frequency such that the control signal is maintained at the first state for a first time period and at the second state for a second time period;

with the bias power modulation circuit, providing the first bias voltage level to the chamber for a third time period when the control signal is maintained at the first state for the first time period; and

with the bias power modulation circuit, providing the second bias voltage level to the chamber for a fourth time period when the control signal is maintained at the second state for the second time period.

18. The method of claim 17, wherein the third time period corresponds to a discharge cycle during which accumulated electrical charge on one or more surfaces of the wafer is discharged from the chamber, and wherein the fourth time period corresponds to an etching cycle during which one or more surfaces of the wafer are etched by a plasma in the chamber, the third time period being shorter than the second time period.

19. The method of claim 17, wherein the CLU is programmable, and wherein the selected frequency at which the control signal alternates between the first and second states is set by programming the CLU with instructions that cause the control signal to alternate between the first and second states at the selected frequency.

20. The method of claim 19, wherein the selected frequency is part of an etch recipe that is loaded into the CLU from a computer that controls the plasma etching process.

21. A system for controlling an accumulation of electrical charge on a wafer located in a plasma etching chamber during a plasma etching process, the system comprising:

a chamber into which a wafer to be etched is loaded, the chamber having first and second bias voltage terminals that are at first and second bias potentials, respectively; and

etching process control circuitry configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged at least one time during the plasma etching process.

22. The system of claim 21, wherein the etching process control circuitry is configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged multiple times during the plasma etching process.

23. The system of claim 22, wherein the etching process control circuitry is configured to cause electrical charge that accumulates on the wafer during a plasma etching process to be discharged multiple times during the plasma etching process, and to be discharged at least one time before the etching process begins and at least one time after the etching process has ended.