Quick turn on apparatus and method for a NMOSFET switch
A quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on. Seamless transition can be further achieved in a single pole double throw switching circuit by using the quick turn on apparatus and method.
This application is a Continuation patent application of co-pending application Ser. No. 11/498,240, filed on 3 Aug. 2006. The entire disclosure of the prior application Ser. No. 11/498,240, from which an oath or declaration is supplied, is considered a part of the disclosure of the accompanying Continuation application and is hereby incorporated by reference.
FIELD OF THE INVENTIONThe present invention is related generally to a quick turn on apparatus and method for a NMOSFET switch.
BACKGROUND OF THE INVENTIONAs shown in
Therefore, it is desired a quick turn on apparatus and method for a NMOSFET switch.
SUMMARY OF THE INVENTIONAn object of the present invention is to provide a quick turn on apparatus and method to speed up a NMOSFET switch to turn on.
Another object of the present invention is to provide a switching circuit with seamless transition.
According to the present invention, a quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on.
According to the present invention, a switching circuit comprises a first NMOSFET switch coupled between a first input and an output, a second NMOSFET switch coupled between a second input and the output, a first quick turn on apparatus coupled to a gate of the first NMOSFET switch, and a second quick turn on apparatus coupled to a gate of the second NMOSFET switch. During the first NMOSFET switch is off, the first quick turn on apparatus maintains the gate voltage of the first NMOSFET switch at a first non-zero level but not enough to turn on the first NMOSFET switch, such that the first NMOSFET switch turns on more quickly due to the gate voltage of the first NMOSFET switch rising up from the first non-zero level when it is to be turned on. Likewise, during the second NMOSFET switch is off, the second quick turn on apparatus maintains the gate voltage of the second NMOSFET switch at a second non-zero level but not enough to turn on the second NMOSFET switch, such that the second NMOSFET switch turns on more quickly due to the gate voltage of the second NMOSFET switch rising up from the second non-zero level when it is to be turned on.
These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
Alternatively, as shown in
In this embodiment, it is the quick turn on apparatus 32 shown in
With reference to
To turn on the NMOSFET switch M2 during the NMOSFET switch M1 is off, the OR gate 664 turns on the NMOS transistor M4 in response to the enable signal EN2, thereby turning on the PMOS transistor M6 by grounding its gate, such that the charge pump 62 charges the gate of the NMOSFET switch M2 to thereby turn on the NMOSFET switch M2. The hysteresis comparator 642 monitors the gate voltage VG1 of the NMOSFET switch M1 in such a manner that, if the gate voltage VG1 is lower than the level Vp1+Vth, the hysteresis comparator 642 produces comparison output to signal the OR gate 644 to turn on the NMOS transistor M3 by the signal V1, thereby grounding the gate of the PMOS transistor M5 to turn on the PMOS transistor M5, such that the charge pump 62 is coupled to the gate of the NMOSFET switch M1 to charge thereto. Once the gate voltage VG1 of the NMOSFET switch M1 reaches the level Vp1+Vth, the NMOS transistor M3 is turned off by the signal V1, and hence the PMOS transistor M5 is turned off too, thereby maintaining the gate voltage VG1 near the level Vp1+Vth but not enough to turn on the NMOSFET switch M1. To turn on the NMOSFET switch M1 and turn off the NMOSFET switch M2, the NMOS transistor M3 and the PMOS transistor M5 are turned on, and the NMOS transistor M4 and the PMOS transistor M6 are turned off, such that the charge pump 62 is coupled to the gate of the NMOSFET switch M1 to pump the gate voltage VG1 from the level Vp1+Vth. Since the time to pull high the gate voltage VG1 from zero to the level Vp1+Vth is saved, and the gate of the NMOSFET switch M2 shares the charges thereon with the gate of the NMOSFET switch M1 through the diode D2 and the PMOS transistor M5, it turns on the NMOSFET switch M1 much faster. The gate voltage VG2 of the NMOSFET switch M2 decays gradually, and once it is detected lower than the level Vp2+Vth by the hysteresis comparator 662, the OR gate 664 turns on the NMOS transistor M4 and thereby the PMOS transistor M6 by the signal V2, causing the charge pump 62 to charge the gate of the NMOSFET switch M2 so as to rise up the gate voltage VG2. Until the gate voltage VG2 reaches the level Vp2+Vth, the NMOS transistor M4 and the PMOS transistor M6 are turned off to maintain the gate voltage VG2 near the level Vp2+Vth.
To turn off the NMOSFET switch M1 and turn on the NMOSFET switch M2 again, the NMOS transistor M3 and the PMOS transistor M5 are turned off, and the NMOS transistor M4 and the PMOS transistor M6 are turned on, so as to couple the charge pump 62 to the gate of the NMOSFET switch M2 to pump the gate voltage VG2 from the level Vp2+Vth. Therefore, the time to pull high the gate voltage VG2 from zero to the level Vp2+Vth is saved, and the gate of the NMOSFET switch M1 shares the charges thereon with the gate of the NMOSFET switch M2 through the diode D1 and the PMOS transistor M6, causing the NMOSFET switch M2 to be turned on much faster. In other embodiments, it may only use either the blocks 64 and 66 or the blocks 65 and 67 for serving as the two quick turn on apparatus for the NMOSFET switches M1 and M2, respectively.
Since the NMOSFET switches M1 and M2 turn on quickly, the switching circuits 50 and 60 can achieve seamless transition.
While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.
Claims
1. A quick turn on apparatus for a NMOSFET switch having a drain coupled to an input and a source coupled to an output, the apparatus comprising:
- a control switch for coupling a voltage to a gate of the NMOSFET switch when the NMOSFET switch is off, such that a gate-to-source voltage of the NMOSFET switch is nonzero but not enough to turn on the NMOSFET switch; said control switch distinct from said NMOSFET switch and controlled by a control signal; said voltage including an existing voltage tied to a voltage of said output.
2. The quick turn on apparatus of claim 1, further comprising a diode serially coupled to the switch for producing a forward bias thereon when the NMOSFET switch is off.
3. A quick turn on apparatus for a NMOSFET switch having a drain coupled to an input and a source coupled to an output, the apparatus comprising:
- an operational amplifier having a non-inverting input coupled with a voltage and an inverting input coupled to a gate of the NMOSFET switch; said voltage including an existing voltage tied to a voltage of said output; and
- a control switch coupled directly between an output of the operational amplifier and the gate of the NMOSFET switch;
- wherein the switch is on when the NMOSFET switch is off, such that a gate-to-source voltage of the NMOSFET switch is nonzero but not enough to turn on the NMOSFET switch; said control switch distinct from said NMOSFET switch and controlled by a control signal.
4. A quick turn on apparatus for a NMOSFET switch having a drain coupled to an input, a source coupled to an output, and a gate coupled to a first switch, the apparatus comprising:
- a second switch for switching the first switch;
- a hysteresis comparator for monitoring a gate voltage of the NMOSFET switch to produce a comparison output; said comparator having a non-inverting input coupled with a voltage, said voltage including an existing voltage tied to a voltage of said output; and
- an OR gate directly coupled to said hysteresis comparator, for producing a control signal according to the comparison output and an enable signal to switch the second switch;
- wherein when the NMOSFET switch is off, if the gate voltage is lower than a threshold, the first switch turns on for the gate of the NMOSFET switch to be charged.
5. A quick turn on method for a NMOSFET switch having a drain coupled to an input and a source coupled to an output, the method comprising the step of:
- operating a control switch, maintaining a gate-to-source voltage of the NMOSFET switch nonzero but not enough to turn on the NMOSFET switch when the NMOSFET switch is off.
6. The method of claim 5, further comprising the step of:
- monitoring the gate-to-source voltage when the NMOSFET switch is off; and
- charging the gate of the NMOSFET switch once the gate-to-source voltage is lower than a threshold.
7. A switching circuit comprising:
- a first input;
- a second input;
- an output;
- a first NMOSFET switch having a drain coupled to the first input and a source coupled to the output;
- a first quick turn on apparatus coupled to a gate of the first NMOSFET switch for maintaining a gate-to-source voltage of the first NMOSFET switch to be nonzero but not enough to turn on the first NMOSFET switch when the first NMOSFET switch is off;
- a second NMOSFET switch having a drain coupled to the second input and a source coupled to the output; and
- a second quick turn on apparatus coupled to a gate of the second NMOSFET switch for maintaining a gate-to-source voltage of the second NMOSFET switch to be nonzero but not enough to turn on the second NMOSFET switch when the second NMOSFET switch is off; wherein the first quick turn on apparatus comprises a first control switch for coupling a voltage to the gate of the first NMOSFET switch when the first NMOSFET switch is off; said first control switch distinct from said first and second NMOSFET.
8. The switching circuit of claim 7, wherein the first quick turn on apparatus further comprises a diode serially coupled to the first control switch for producing a forward bias thereon when the first NMOSFET switch is off.
9. The switching circuit of claim 7, wherein the first quick turn on apparatus comprises:
- an operational amplifier having a non-inverting input coupled with a voltage and an inverting input coupled to the gate of the first NMOSFET switch; said voltage including an existing voltage tied to a voltage of said output; and
- a second control switch coupled between an output of the operational amplifier and the gate of the first NMOSFET switch;
- wherein the switch is on when the NMOSFET switch is off; said second control switch distinct from said first NMOSFET.
10. A switching circuit comprising: said first and second control switch distinct from said first and second NMOSFET switch.
- a first input;
- a second input;
- an output;
- a first NMOSFET switch having a drain coupled to the first input and a source coupled to the output;
- a first control switch coupled to a gate of the first NMOSFET switch;
- a first quick turn on apparatus for monitoring a gate voltage of the first NMOSFET switch when the first NMOSFET switch is off, so as to turn on the first control switch for charging the gate of the first NMOSFET switch once the gate voltage of the first NMOSFET switch is lower than a first threshold;
- a second NMOSFET switch having a drain coupled to the second input and a source coupled to the output;
- a second control switch coupled to a gate of the second NMOSFET switch; and
- a second quick turn on apparatus for monitoring a gate voltage of the second NMOSFET switch when the second NMOSFET switch is off, so as to turn on the second control switch for charging the gate of the second NMOSFET switch once the gate voltage of the second NMOSFET switch is lower than a second threshold;
11. The switching circuit of claim 10, wherein the first quick turn on apparatus comprises:
- a hysteresis comparator for comparing the gate voltage of the first NMOSFET switch and the first threshold to produce a comparison output; said comparator coupled to a voltage; said voltage including an existing voltage tied to a voltage of said output;
- an OR gate, directly coupled to said hysteresis comparator, for switching the first control switch according to the comparison output and an enable signal;
- wherein the enable signal maintains the first control switch on when the first NMOSFET switch is on.
Type: Application
Filed: Mar 12, 2009
Publication Date: Jul 9, 2009
Inventors: Ko-Cheng Wang (Puli Township), Liang-Pin Tai (Gueiren Shiang)
Application Number: 12/382,258
International Classification: H03K 17/687 (20060101);