Field-effect Transistor Patents (Class 327/427)
  • Patent number: 12279911
    Abstract: This patent disclosure relates to an ultrasound transducer including an array of ultrasound transducing elements, a plurality of transducer drive lines. The ultrasound transducer further includes an array of control circuits, wherein each individual control circuit includes a drive switch and a memory element, the drive switch comprising at least one thin-film transistor, the memory element being configured to store and control the state of the drive switch.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: April 22, 2025
    Assignee: IMEC VZW
    Inventors: Florian De Roose, Kris Myny
  • Patent number: 12273098
    Abstract: A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: April 8, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Christian Fachmann, Matteo-Alessandro Kutschak, Otto Wiedenbauer, Winfried Kaindl, Hans Weber
  • Patent number: 12242294
    Abstract: This document describes methods implemented by and systems utilizing an alternating-current (AC) power-switching device. The AC power-switching device includes first and second current input/output (I/O) nodes, a current-limiting resistor, and a bypass switch connected between the first and second current I/O nodes. The bypass switch includes a first light-emitting-diode-input normally closed solid-state relay. Further, the AC power-switching device includes a rectifier, a voltage regulator, and a controller. The controller includes a programmable controller chip and is configured to detect a voltage level at the output of the rectifier, activate the bypass switch in response to the voltage level exceeding a first voltage level threshold, set a first lockout timer in response to activating the bypass switch, and deactivate the bypass switch in response to the voltage level dropping below a second voltage level threshold.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: March 4, 2025
    Assignee: Google LLC
    Inventor: Gary Lee Embler
  • Patent number: 12206393
    Abstract: A current limiting circuit of a switching circuit, and a switching circuit are provided. The switching circuit uses a gallium nitride (GaN) power transistor as a main power transistor. The current limiting circuit includes a first terminal connected with a drain of the GaN power transistor, and a second terminal connected with a controller of the switching circuit. The current limiting circuit is configured to limit a current flowing out of a power supply terminal of the controller. The current limiting circuit suppresses a negative current flowing through the controller.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 21, 2025
    Assignee: Joulwatt Technology Co., Ltd.
    Inventor: Xiangyong Xu
  • Patent number: 12199597
    Abstract: Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 14, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rohan Sinha, Rajat Kulshrestha
  • Patent number: 12176057
    Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: December 24, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Chandra B. Prakash, Cory J. Peterson
  • Patent number: 12155381
    Abstract: A radio frequency (RF) device is described. The RF device includes a switch field effect transistor (FET), having a source region, a drain region, a body region, and a gate region. The RF device also includes a dynamic bias control circuit. The dynamic bias control circuit includes a first transistor coupled to the gate region of the switch FET by a gate resistor. The dynamic bias control circuit also includes a second transistor coupled to the first transistor and coupled to the body region of the switch FET by a body resistor. The dynamic bias control circuit further includes a capacitor coupled to the body region of the switch FET by the body resistor, and the gate region of the switch FET, by the gate resistor.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: November 26, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ravi Pramod Kumar Vedula, Abhijeet Paul, Hyunchul Jung
  • Patent number: 12149231
    Abstract: A switch circuit includes a control unit, a driving unit, a voltage sudden-change unit, and a connection unit. The connection unit is configured to turn on or turn off an electrical connection between a power-supply device and a load. The control unit is configured to control the driving unit to output or stop outputting a driving signal to the connection unit, where the driving signal allows to turn on the connection unit. The voltage sudden-change unit is coupled with a driving node between the driving unit and the connection unit. The control unit is configured to control the voltage sudden-change unit to output a voltage sudden-change signal to the driving node, where the voltage sudden-change signal allows to make the connection unit be switched to a turned-off state from a turned-on state quickly when the driving unit stops outputting the driving signal.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: November 19, 2024
    Assignee: SHENZHEN CARKU TECHNOLOGY CO., LIMITED
    Inventors: Yun Lei, Zhifeng Zhang, Jianping Lin
  • Patent number: 12126272
    Abstract: A power supply device includes a transformer including a primary winding, a secondary winding and an auxiliary winding, first, second and third circuits, and a switch. The first circuit in which a first capacitor and a first rectifier are connected in series is connected to the primary winding in parallel. The switch of which one end is connected to one end of the primary winding. The second circuit in which the auxiliary winding and a second rectifier are connected in serial is connected between a connecting point, to which the first capacitor and the first rectifier are connected, and the other end of the switch. The third circuit including a resistor and a third rectifier is connected to a gate of the switch. In the third circuit, a resistance value in a direction where a current flows into the gate of the switch is smaller than that in a direction where the current flows out of the gate.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: October 22, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yuya Hirano
  • Patent number: 12119814
    Abstract: A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: October 15, 2024
    Assignee: pSemi Corporation
    Inventors: Ravindranath D. Shrivastava, Alper Genc
  • Patent number: 12088210
    Abstract: A switched mode power converter is provided herein and comprises a cycloconverter comprising a plurality of switches, wherein each switch of the plurality of switches is a native four quadrant bi-directional switch with a common drift region configured to allow current flow in a first direction from a first source terminal to second source terminal and in a second direction from the second source terminal to the first direction.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: September 10, 2024
    Assignee: Enphase Energy, Inc.
    Inventor: Michael J. Harrison
  • Patent number: 12088284
    Abstract: A discrete relay driver circuit that includes a first high side gate drive circuit configured to drive a first high side MOSFET and a second high side gate drive circuit configured to drive a second high side MOSFET. The discrete relay driver circuit also includes a first resistor divider configured to sense voltage from the first high side MOSFET, a second resistor divider configured to sense voltage from the second high side MOSFET, and a first low side gate driver circuit configured to drive a first low side MOSFET. The discrete relay driver circuit also includes a second low side gate driver circuit configured to drive a second low side MOSFET based on a first low side enable signal, and a third low side gate driver circuit configured to drive a third low side MOSFET based on a second low side enable signal.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: September 10, 2024
    Assignee: DELPHI TECHNOLOGIES IP LIMITED
    Inventors: Karthik Naik, Wong Chuan Ming, Venkata Jaya Sai Praneeth Ammanamanchi, Engel Joseph
  • Patent number: 12081211
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: September 3, 2024
    Assignee: pSemi Corporation
    Inventor: Payman Shanjani
  • Patent number: 12081207
    Abstract: A semiconductor device includes: a semiconductor body having an active region and a substrate region beneath the active region; a bidirectional switch having first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: September 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Kennith Kin Leong, Gerhard Maderbacher, Herwig Wappis
  • Patent number: 12068740
    Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: August 20, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ting Wu
  • Patent number: 12062701
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 13, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 12063032
    Abstract: A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: August 13, 2024
    Assignee: Littelfuse, Inc.
    Inventor: Bret R. Howe
  • Patent number: 12057824
    Abstract: An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 6, 2024
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Daniel M. Kinzer, Ren Huei Tzeng
  • Patent number: 12051974
    Abstract: A controller for a power converter includes: an estimator configured to estimate or calculate a slew rate of an output voltage of the power converter or a slew rate of an error voltage which corresponds to a difference between the output voltage and a target voltage, during a load transient; and a modulator configured to modify regulation of the output voltage based on the estimated or calculated slew rate. A corresponding voltage regulation method and an electronic system that includes the power converter are also described.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 30, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Zhiqing You, Tim Ng, Sue Perranoski, Benjamim Tang
  • Patent number: 12046575
    Abstract: A method for fabricating a three-dimensional (3D) electronic device. A liquid support material (e.g., an epoxy acrylate with a photoinitiator) is applied by a laser-induced forward transfer (LIFT) process to a printed circuit board (PCB) having one or more connectors and one or more electronic components thereon, and then cured to solid form by cooling and/or exposure to ultraviolet (UV) radiation. A layer of conductive material (e.g., a metal) is printed on the solidified support material by LIFT to electrically connect the one or more electronic components to respective ones of the connectors on the PCB. Subsequently, the layer of conductive material is dried by heating and metal particles in the conductive layer sintered using a laser beam. The assembly may then be encapsulated in an encapsulant.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: July 23, 2024
    Assignee: IO Tech Group Ltd.
    Inventors: Michael Zenou, Ziv Gilan, Guy Nesher
  • Patent number: 12034297
    Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 9, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Kai Zhou, Lei Pan, Ya-Qi Ma, Zhang-Ying Yan
  • Patent number: 12002735
    Abstract: A semiconductor package is disclosed for efficiently facilitating heat dissipation. The semiconductor package includes a substrate layer, a chip, a housing lid and thermal-conductive liquid. A chip is disposed on the substrate layer and electrically coupled to the substrate layer. The chip includes at least one through silicon via (TSV). The housing lid is disposed above both the substrate layer and the chip. Also, the housing lid is coupled to the substrate layer at its edge for forming an internal space that encompasses the chip. The thermal-conductive liquid is filled within the internal space.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: June 4, 2024
    Inventor: Tien-Chien Cheng
  • Patent number: 11996836
    Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: May 28, 2024
    Assignee: Silanna Asia Pte Ltd
    Inventors: Cameron Brown, Yashodhan Vijay Moghe
  • Patent number: 11967355
    Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 11955965
    Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Sushil Subramanian, Stefano Pellerano, Todor Mladenov, JongSeok Park, Bishnu Prasad Patra
  • Patent number: 11869947
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 9, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11848697
    Abstract: A communication device capable of transmitting and receiving high-potential signals is provided. The communication device includes a duplexer including first to fourth transistors, a transmission terminal, a reception terminal, an antenna terminal, and first and second control terminals. The transmission terminal is electrically connected to one of a source and a drain of each of the first and second transistors. The reception terminal is electrically connected to one of a source and a drain of each of the third and fourth transistors. The antenna terminal is electrically connected to the other of the source and the drain of each of the second and fourth transistors. The first control terminal is electrically connected to gates of the second and third transistors. The second control terminal is electrically connected to gates of the first and fourth transistors. A semiconductor of each of the first to fourth transistors contains a metal oxide.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 19, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Hitoshi Kunitake
  • Patent number: 11804729
    Abstract: According to aspects of the disclosure, a method and system are provided for transferring a load between a primary power source and a secondary power source. In accordance with the disclosure, a method of transferring a load between a first power source and a second power source includes analyzing a plurality of power sources to identify one or more power sources providing a power greater than a threshold value. The method also includes selecting a power source from the identified one or more power sources providing power greater than the threshold value. The method further includes connecting the selected power source to a transfer mechanism. The method still further includes actuating the transfer mechanism, using power provided to the transfer mechanism by the selected power source, to transfer the load from a connection with the first power source to a connection with the second power source.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: October 31, 2023
    Assignee: ASCO Power Technologies, L.P.
    Inventor: John E. Hayes
  • Patent number: 11777502
    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 3, 2023
    Inventors: Hiroki Inoue, Munehiro Kozuma, Takeshi Aoki, Shuji Fukai, Fumika Akasawa, Sho Nagao
  • Patent number: 11769564
    Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: September 26, 2023
    Assignee: Silicon Laboratories Inc.
    Inventor: Mohamed M. Elsayed
  • Patent number: 11764824
    Abstract: System and methods for reducing nonlinearity in radio frequency (RF) circuitries (e.g., RF switch circuitry and/or RF amplifier circuitry) are provided. A high-linearity RF integrated circuit device includes an input port; an output port; nonlinear circuitry arranged on a signal path between the input port and the output port; a shunt path including signal adjustment circuitry; and adjustable nonlinearity generation circuitry coupled to the signal adjustment circuitry, the adjustable nonlinearity generation circuitry including one or more metal-oxide-semiconductor (MOS) devices; and at least one nonlinearity generation activation element connected in parallel with a source terminal and a drain terminal of a first MOS device of the one or more MOS devices and responsive to an activation control signal. The nonlinear circuitry may include at least one of switching circuitry or amplifier circuitry. The shunt path may be coupled to the input port or the output port.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: September 19, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Huseyin Kayahan, Berktug Ustundag, Alp Oguz, Turusan Kolcuoglu, Yusuf Atesal
  • Patent number: 11750086
    Abstract: In a drive circuit, a differential circuit unit is configured such that resetting of an output voltage of the differential circuit unit is carried out, and the resetting of the output voltage of the differential circuit unit is cancelled. A value of the difference between first and second divided terminal voltages at a timing of cancelling the resetting is defined as a reference voltage. The differential circuit unit generates, as the output voltage, a product of a voltage change from a reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit. A signal generator generates a gate signal for the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 5, 2023
    Assignee: DENSO CORPORATION
    Inventors: Yasuaki Aoki, Tomohiro Nezuka, Akimasa Niwa
  • Patent number: 11720778
    Abstract: A voltage limiter incorporated in a radio frequency identification (RFID) integrated circuit (IC) for a RFID tag is disclosed. The RFID IC includes a radio frequency (RF) rectifier and a clock generator. The RF rectifier is configured to convert an AC signal received from an antenna incorporated in the RFID tag to a DC signal. The voltage limiter includes a current sink device coupled between output of the RF rectifier and ground and a charge pump to control conduction of current through the current sink device to limit output voltage of the RF rectifier to a predefined voltage level.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: August 8, 2023
    Assignee: NXP B.V.
    Inventors: Thomas Pichler, Ivan Jesus Rebollo Pimentel
  • Patent number: 11714138
    Abstract: A semiconductor device that tests and/or monitors each of batteries provided in an assembled battery is provided. The semiconductor device includes a hysteresis comparator and a circuit, and the circuit has a function of setting a high-level side threshold voltage and a low-level side voltage of the hysteresis comparator. The circuit includes first and second capacitors. A first terminal of the first capacitor is electrically connected to a high-level side reference potential input terminal of the hysteresis comparator and a first terminal of the second capacitor is electrically connected to a low-level side reference potential input terminal of the hysteresis comparator.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 1, 2023
    Inventors: Kei Takahashi, Yuki Okamoto, Minato Ito, Takahiko Ishizu
  • Patent number: 11695335
    Abstract: A method comprises configuring a power converter to operate as a boost converter, the power converter comprising a low side switch and a high side switch, during a first dead time after turning off the low side switch and before turning on the high side switch, configuring the power converter such that a current of the power converter flows through a high speed diode, and after turning on the high side switch, configuring the power converter such that the current of the power converter flows through a low forward voltage drop diode.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: July 4, 2023
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Dianbo Fu, Dong Chen
  • Patent number: 11695393
    Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 4, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Rui Li, De Lu, Venkat Narayanan
  • Patent number: 11652402
    Abstract: The objective is to provide a function of detecting loss of a current detection function, at a time when a switching device has an open failure, in an arm that has the current detection function and a temperature detection function and in which two or more switching devices are connected in parallel with one another. A switching apparatus includes a current detector and a temperature detector provided in at least one of the two or more switching devices that are connected in parallel with one another and a controller that determines an overcurrent in the switching device in which the current detector is provided, that determines an overheating state and a temperature-rising failure in the switching device in which the temperature detector is provided, based on an output of the temperature detector, and that controls the switching devices.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 16, 2023
    Assignee: Mitsubishi Electric Cornoration
    Inventor: Takashi Kaneyama
  • Patent number: 11652348
    Abstract: An integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates an initiation voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates, in response to the initiation voltage at the first node, a first control signal based on a first supply voltage to the second voltage generation circuit. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node, based on a second supply voltage.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 16, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Kai Zhou, Lei Pan, Ya-Qi Ma, Zhang-Ying Yan
  • Patent number: 11645894
    Abstract: A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: May 9, 2023
    Assignee: Google LLC
    Inventors: Daniel Adam Warren, Eric Marschalkowski, Brian Conner
  • Patent number: 11641203
    Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 2, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Cameron Brown, Yashodhan Vijay Moghe
  • Patent number: 11601121
    Abstract: The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Giacomo Cascio, Martin Clara, Christian Lindholm
  • Patent number: 11588390
    Abstract: The present description concerns a method of controlling a bidirectional switch (200), including: first (210 1) and (210 2) field-effect transistors electrically in series between first (262 1) and second (262 2) terminals of the bidirectional switch; third (614) and fourth (612) field-effect transistors electrically in series between said first and second terminals of the bidirectional switch, a first connection node (252) in series with the first and second transistors being common with a second connection node (616) in series with the third and fourth transistors, including steps of: receiving a voltage (V200) between the terminals of the bidirectional switch; detecting, from the received voltage, a first sign of said voltage; at least while the first sign is being detected, coupling the first terminal to said first node (252), potentials of control terminals of the first, second, third, and fourth transistors being referenced to the potential (REF) of the first and second nodes having common sources of th
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: February 21, 2023
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventor: Dominique Bergogne
  • Patent number: 11539361
    Abstract: To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 27, 2022
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Toru Masuda, Seiichi Hayakawa, Yuji Takayanagi, Takae Shimada, Takashi Wada
  • Patent number: 11489521
    Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 1, 2022
    Assignee: FAST SIC SEMICONDUCTOR INCORPORATED
    Inventors: Cheng-Tyng Yen, Fu-Jen Hsu, Hsiang-Ting Hung
  • Patent number: 11476849
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: pSemi Corporation
    Inventor: Payman Shanjani
  • Patent number: 11463087
    Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 4, 2022
    Assignee: PSEMI CORPORATION
    Inventor: Alper Genc
  • Patent number: 11444614
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 13, 2022
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 11418183
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 16, 2022
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Patent number: 11418052
    Abstract: The present disclosure relates to a power circuit including a power supply circuit and a first control circuit. The power supply circuit is electrically connected to a power supply source and a power terminal for selectively providing power to the power terminal. The first control circuit is electrically connected to the power supply circuit and configured to receive a detection signal to enable or disable the power supply circuit. When the detection signal is enabled, the first control circuit provides a first enable signal to the power supply circuit, so that the power supply circuit provides power to the power terminal. When the detection signal is at the disable level, the first control circuit is configured to provide the first disable signal to the power supply circuit, so that the power supply circuit stops providing power from the power supply source to the power terminal.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ya-Hsuan Sung, Leaf Chen
  • Patent number: 11394288
    Abstract: A negative voltage generation circuit 200 includes a first DC voltage source 201 having a positive terminal connected to a first node N1 (Vin), a first diode 202 having a cathode connected to a negative terminal of the first DC voltage source 201 and an anode connected to an output terminal of a first negative voltage VC1 (fourth node N4), and a first capacitor 204 having a first terminal connected to an output terminal of the first negative voltage VC1 and a second terminal connected to a second node N2 (Vs_high), so as to supply the first negative voltage VC1 to a first driver 20 that performs switching control of a first NMOSFET 11 (first switch element) connected between the first node N1 (Vin) and the second node N2 (Vs_high).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 19, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Yusuke Nakakohara, Yuta Okawauchi, Ken Nakahara, Shinichiro Nagai, Yuuki Ootabara