Field-effect Transistor Patents (Class 327/427)
  • Patent number: 11463087
    Abstract: Methods and devices to mitigate de-biasing caused by an undesired gate induced drain body leakage current in FET switch stacks are disclosed. The devices utilize diode stacks to generate discharge paths for the undesired current. The disclosed teachings are applicable to both shunt and series implementations of FET switch stacks.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 4, 2022
    Assignee: PSEMI CORPORATION
    Inventor: Alper Genc
  • Patent number: 11444614
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: September 13, 2022
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 11418052
    Abstract: The present disclosure relates to a power circuit including a power supply circuit and a first control circuit. The power supply circuit is electrically connected to a power supply source and a power terminal for selectively providing power to the power terminal. The first control circuit is electrically connected to the power supply circuit and configured to receive a detection signal to enable or disable the power supply circuit. When the detection signal is enabled, the first control circuit provides a first enable signal to the power supply circuit, so that the power supply circuit provides power to the power terminal. When the detection signal is at the disable level, the first control circuit is configured to provide the first disable signal to the power supply circuit, so that the power supply circuit stops providing power from the power supply source to the power terminal.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ya-Hsuan Sung, Leaf Chen
  • Patent number: 11418183
    Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 16, 2022
    Assignee: pSemi Corporation
    Inventors: Simon Edward Willard, Tero Tapio Ranta, Matt Allison, Shashi Ketan Samal
  • Patent number: 11394288
    Abstract: A negative voltage generation circuit 200 includes a first DC voltage source 201 having a positive terminal connected to a first node N1 (Vin), a first diode 202 having a cathode connected to a negative terminal of the first DC voltage source 201 and an anode connected to an output terminal of a first negative voltage VC1 (fourth node N4), and a first capacitor 204 having a first terminal connected to an output terminal of the first negative voltage VC1 and a second terminal connected to a second node N2 (Vs_high), so as to supply the first negative voltage VC1 to a first driver 20 that performs switching control of a first NMOSFET 11 (first switch element) connected between the first node N1 (Vin) and the second node N2 (Vs_high).
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 19, 2022
    Assignee: Rohm Co., Ltd.
    Inventors: Yusuke Nakakohara, Yuta Okawauchi, Ken Nakahara, Shinichiro Nagai, Yuuki Ootabara
  • Patent number: 11387812
    Abstract: This invention relates to a driving circuit with electronic switches in serial connection structure, and this driving circuit includes: electronic switch module and active drive module, electronic switch module includes: n pcs electronic switches in serial connection, and n pcs electronic switches D and S terminal connected in series in turn; active drive modules includes: n pcs active drive circuits; and in this invention, the power supply and the driving pulse signal of the electronic switch K2 to Kn are obtained successively from electronic switch K1, and the electronic switch K1 to Kn is on and off in turn; The n pcs electronic switches have nanosecond level of the switching performance of the active circuit, which are suitable for the high frequency high power gate drive circuit when n pcs electronic switches series structure is used.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 12, 2022
    Inventor: Shunzhu Tao
  • Patent number: 11262388
    Abstract: According to an embodiment(s), a current detection circuit has first and second main electrodes, a vertical structure output transistor that includes a first control electrode where a control signal is supplied thereto, a third main electrode that is connected to the first main electrode, a second control electrode that is connected to the first control electrode, and a vertical structure detection transistor that has a fourth main electrode. The current detection circuit has a voltage supply circuit that supplies a divided voltage of a voltage between the first and second main electrodes to the fourth main electrode.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Terumitsu Komatsu
  • Patent number: 11201494
    Abstract: Systems and methods for efficiently allowing current to bypass a group of solar cells having one or more malfunctioning or shaded solar cells without overwhelming a bypass diode. This can be done using a switch (e.g., a MOSFET) connected in parallel with the bypass diode. By turning the switch on and off, a majority of the bypass current can be routed through the switch, which is configured to handle larger currents than the bypass diode is designed for, leaving only a minority of the current to pass through the bypass diode.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 14, 2021
    Assignee: Tigo Energy, Inc.
    Inventor: Mordechay Avrutsky
  • Patent number: 11201562
    Abstract: An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 14, 2021
    Assignee: Purdue Research Foundation
    Inventors: Oleg Wasynczuk, Minyu Cai
  • Patent number: 11196336
    Abstract: A gate drive apparatus including a gate drive unit configured to drive a gate of a switching device, a peak detection unit configured to detect that a voltage across main terminals applied between the main terminals of the switching device during a turn-off period of the switching device is at a peak, and a driving condition changing unit configured to increase a change speed of a gate voltage of the switching device caused by the gate drive unit, in response to a detection that the voltage across main terminals is at a peak.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsuyoshi Nagano, Kunio Matsubara
  • Patent number: 11165421
    Abstract: A switching element 1 has a gate terminal connected to an output end 123 of a driving circuit 12 via a capacitor 11 and a resistor 13 connected in parallel. The switching element 1 has a source terminal connected to the driving circuit 12 via a capacitor 14. A diode 15 connected in series with a resistor 16 has a cathode terminal connected to a section between the capacitor 11 and the resistor 13, and the gate terminal and an anode terminal connected, via the resistor 16, to a section between the source terminal and the capacitor 14.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 2, 2021
    Assignee: OMRON CORPORATION
    Inventors: Noriyuki Nosaka, Wataru Okada, Hironori Nakada, Satoshi Iwai
  • Patent number: 11146226
    Abstract: Provided is an analog switch circuit that allows switching between an on-state and an off-state according to a control signal, the analog switch circuit including a main input terminal that receives an input voltage, an output terminal, an upper-side power supply terminal that receives an upper supply voltage, a lower-side power supply terminal that receives a lower supply voltage, a main N-channel MOS transistor and a main P-channel MOS transistor that are disposed in parallel between the main input terminal and the output terminal, and a controller that includes a voltage generating circuit that generates a high-side voltage according to the upper supply voltage and the input voltage and a low-side voltage according to the input voltage and the lower supply voltage. The controller can control a gate and a back gate of each of the main N-channel and P-channel MOS transistors based on the high-side and low-side voltages.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 12, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Mitsuteru Sakai
  • Patent number: 11146259
    Abstract: A voltage equalization method for use in a radiofrequency switch having multiple transistors connected in series and the radiofrequency switch. In the voltage equalization method, capacitors are additionally provided as parasitic capacitances between source electrodes and drain electrodes of transistors (M1-MN) connected in series to compose a radiofrequency switch, and voltage drop uniformity is implemented for the transistors (M1-MN) by adjusting the parasitic capacitances of the transistors (M1-MN). By means of different combinations of the positions, sizes, and spacing of metal bars on a first metal layer (1) and on a second metal layer (2), the parasitic capacitances between the source electrodes and the drain electrodes of the transistors (M1-MN) can be finely adjusted, thus increasing the voltage drop uniformity of the transistors (M1-MN). The method uses less transistors to accomplish the design of the radiofrequency switch.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: October 12, 2021
    Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.
    Inventors: Yunfang Bai, Sheng Lin
  • Patent number: 11114543
    Abstract: A group III-V device structure is provided. The group III-V device structure includes a channel layer formed over a substrate and an active layer formed over the channel layer. The group III-V device structure also includes a gate structure formed over the active layer and a source electrode and a drain electrode formed over the active layer. The source electrode and the drain electrode are formed on opposite sides of the gate structure. The group III-V device structure further includes a through via structure formed through the channel layer, the active layer and a portion of the substrate, and the through via structure is electrically connected to the source electrode or the drain electrode.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hong Chang, Chih-Yuan Chan, Shen-Ping Wang, Chung-Cheng Chen, Chien-Li Kuo, Po-Tao Chu
  • Patent number: 11088685
    Abstract: An NMOS transistor performs electrical conduction or cut-off between a drain and a source by controlling a potential at a gate. A resistive element is connected between a back gate of the NMOS transistor and a high-frequency ground. A first switching circuit is disposed in parallel with the resistive element between the back gate and the high-frequency ground and causes a short circuit between the back gate and the high-frequency ground upon cut-off.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: August 10, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takanobu Fujiwara, Mitsuhiro Shimozawa
  • Patent number: 11081159
    Abstract: A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 3, 2021
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventors: Rolf Jähne, Marko Noack
  • Patent number: 11025248
    Abstract: A device includes a first diode and a second diode connected in series between a first terminal and a second terminal of a switching element, wherein the switching element is a unidirectional device and an anode of the first diode is directly connected to an anode of the second diode, a third diode connected between the first terminal and the second terminal of the switching element and a switch connected in parallel with the first diode.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 1, 2021
    Assignee: Futurewei Technologies, Inc.
    Inventors: Dianbo Fu, Zhaohui Wang, Jun Zhang, Lei Shi
  • Patent number: 10938199
    Abstract: Embodiments of the disclosure include a switch having an on-state resistance that varies based on a temperature coefficient of the switch and an overcurrent protection circuit coupled to the switch and having an adjustable overcurrent threshold level determined based on an adjustable voltage generated by the overcurrent protection circuit, the adjustable voltage generated based on the temperature coefficient of the switch.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 2, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventor: Guanghua Ye
  • Patent number: 10923908
    Abstract: The disclosure relates to an electronic module comprising a source terminal for receiving an input current from an electrical voltage source and comprising an electrical input capacitance which is effective with respect to the source terminal, wherein the input capacitance is connected to the source terminal via a transistor circuit. The disclosure additionally provides that the transistor circuit is configured to conduct the input current via a respective switching path of at least one transistor, and a control device is configured to switch, during the switch-on process for limiting the input current, a control voltage at a respective control terminal of the at least one transistor, in a plurality of steps, from an off value at which each switching path is switched off, to a connection value at which a contact resistance of each switching path is minimized.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 16, 2021
    Assignee: Continental Automotive GmbH
    Inventors: Emil Kovatchev, Aurel-Vasile Neic
  • Patent number: 10903821
    Abstract: A complementary metal-oxide semiconductor (CMOS) compatible radio frequency (RF) switch circuit and high voltage control circuit (HVCC) are disclosed. In a mobile device, an RF switch circuit couples a first RF circuit to a shared antenna through a low resistance path while electrically isolating other RF circuits from the antenna by a high resistance path. Each path in the RF switch circuit includes a series metal-oxide semiconductor (MOS) Field-Effect Transistor (FET) MOSFET switch which provides a low resistance path when fully turned on by a strong positive gate-to-source voltage and a corresponding body bias voltage, and a high resistance path when fully turned off by a strong negative gate-to-source voltage and corresponding body bias voltage. The RF switch circuit paths are controlled by a CMOS compatible HVCC which supplies high and low voltage signals to the gate node and body bias node of each MOSFET in each path.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Yan Guo, Patrick T. Clancy
  • Patent number: 10891529
    Abstract: An RFID tag is provided as a wireless communication device that transmits and receives a communication signal. The RFID tag includes a base material, a conductor pattern including an antenna pattern provided at the base material, and a discharge auxiliary electrode. The discharge auxiliary electrode is disposed at a position where the discharge auxiliary electrode overlaps or is close to the antenna pattern in planar view, and lowers a dielectric breakdown voltage between two different opposed portions on the conductor pattern. With this configuration, ignition and combustion is prevented even in a situation in which the RFID tag is subjected to high-frequency power for heating a food item while attached to the food item.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: January 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hirokazu Yazaki
  • Patent number: 10866475
    Abstract: An active matrix substrate according to an aspect of the disclosure includes a pixel portion including a plurality of gate lines and a plurality of source lines, and a plurality of pixel electrodes, and a split switch circuit configured to split a signal from a source driver to supply to the plurality of source lines, wherein the pixel portion includes a first TFT including a first oxide semiconductor layer, the split switch circuit includes a second TFT including a second oxide semiconductor layer and a third oxide semiconductor layer, and the third oxide semiconductor layer covers at least a portion of an upper face and a portion of an edge face of the second oxide semiconductor layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yuhichi Saitoh
  • Patent number: 10812072
    Abstract: A novel approach for the control of AC power uses power MOSFETs in a bidirectional switch subcircuit configuration having an optically coupled, electrically floating control circuit that self-biases the switches into the “on” state and uses an optically coupled control element to force the switches into the “off” state. The time constant of the control circuit is fast enough to allow phase control as well as on-off control. A plurality of subcircuits can be easily cascaded to provide improved performance.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 20, 2020
    Inventors: Mark Telefus, Bradley Larson, Harry Rodriguez
  • Patent number: 10778087
    Abstract: A switching half-bridge has two field-effect transistors and a supplementary circuit arranged upstream of a gate terminal of a first field-effect transistor and formed of a first circuit branch having a damping resistor and an inductor connected in series with the damping resistor and a second circuit branch being connected in parallel with the first circuit branch and having a series resistor and an auxiliary switch connected in series with the series resistor. The half-bridge can be switched from a first switching state to a second switching state, wherein while the auxiliary switch is open, a change in the control voltage causes the first circuit branch to temporarily change the gate-source voltage of the first field-effect transistor from the switch-on level to a second switch-off level greater than a first switch-off level, with the gate-source voltage thereafter returning to the first switch-off level.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: September 15, 2020
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Andreas März, Mark-Matthias Bakran
  • Patent number: 10763251
    Abstract: A semiconductor device has a protected line connected to a ground line by a triggered clamp. A variable shunt, which includes a depletion mode JFET, is connected between the protected line and the ground line, in parallel with the triggered clamp. The depletion mode JFET is formed in a substrate of the semiconductor device. The channel of the depletion mode JFET provides a resistive path for the variable shunt when the semiconductor device is unpowered, to dissipate charge from the powered line after an ESD event. When the semiconductor device is operated, that is, powered up, the gate of the depletion mode JFET may be biased to turn off the channel, and so reduce impairment of operation of the semiconductor device.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, James P Di Sarro, Mariano Dissegna, Lihui Wang, Ann Margaret Concannon
  • Patent number: 10763842
    Abstract: a radio frequency (RF) switching circuit, including: a conducting module, configured to conduct an RF signal; a gate control voltage generating module, configured to provide a gate control voltage for the conducting module to control the conducting module operating at ON-state or OFF-state; wherein the gate control voltage generating module further includes: a first resistance adaptive module, providing a first impedance in a first state for a series branch where the conducting module and the gate control voltage generation module locate, and a second impedance in a second state for the series branch where the conducting module and the gate control voltage generation module locate, wherein the first impedance is greater than the second impedance. FOM is improved comprehensively, and Ron, Coff, and a power breakdown performance are optimized, which further improves circuit performance and reduces cost.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 1, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Ruofan Dai
  • Patent number: 10734991
    Abstract: A voltage switching device, an integrated circuit device, and a voltage switching method are provided. The voltage switching device includes a reference voltage generator generating a first reference voltage and a second reference voltage, a fuse system coupled to a circuit device, and a switch circuit coupled to the reference voltage generator, the fuse system, and the circuit device. The fuse system generates a first enable signal and a second enable signal according to an input signal from a circuit device. The switch circuit transmits the first reference voltage or the second reference voltage to the circuit device according to the first enable signal and the second enable signal from the fuse system.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 4, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ting-Shuo Hsu, Chih-Wei Shen
  • Patent number: 10659034
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Renan Lethiecq
  • Patent number: 10637526
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 28, 2020
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 10615817
    Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 7, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Fergus John Downey
  • Patent number: 10607949
    Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 31, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Yves Mazoyer, Philippe Galy, Philippe Sirito-Olivier
  • Patent number: 10574225
    Abstract: Provided is a driving circuit for driving a switching element in accordance with an input signal. The driving circuit includes a driving unit connected to a control terminal of the switching element, where the driving unit is configured to switch, in accordance with the input signal, which one of a source current and a sink current is to be fed to the control terminal of the switching element, a first limiter configured to operate with a predetermined time constant and to limit a control voltage at the control terminal of the switching element to a first reference voltage when overcurrent is detected for a collector current of the switching element, and a second limiter configured to, when the overcurrent is detected, start lowering the control voltage earlier than an operation start timing of the first limiter that is determined by the time constant.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Akira Nakamori
  • Patent number: 10536082
    Abstract: A power supply device includes a voltage conversion circuit, a current controller and a current controlling circuit. The voltage conversion circuit generates a DC voltage from an AC power source and outputs the DC voltage to a pair of output terminals. The current controller is disposed on a first current path through which an output current flows and controls the current in the first current path. The current controlling circuit drives the current controller so as to reduce a ripple component generated in the output current, based on (i) a voltage at a first potential point set on a path from an output terminal at a high-potential side of the voltage conversion circuit to the current controller in the first current path and (ii) a current detecting voltage indicating the magnitude of the output current.
    Type: Grant
    Filed: December 23, 2018
    Date of Patent: January 14, 2020
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventors: Daisuke Imade, Naoto Endo
  • Patent number: 10516333
    Abstract: A circuit for slew rate control for a high-side switch is disclosed. The circuit comprises a sample and level-shift circuit. The sample and level-shift circuit is connected to the high-side switch. The circuit further comprises a sampling capacitor, and the sampling capacitor is configured to sample an input voltage corresponding to the sample and level-shift circuit. Additionally, the circuit includes a charge-limiting circuit. The sampling capacitor is configured to charge a gate capacitance of the high-side switch. The charge-limiting circuit is configured to limit a rate of charge transferred to the gate capacitance of the high-side switch per unit of time.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 24, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Sureshkumar Ramalingam, Udo Karthaus
  • Patent number: 10476496
    Abstract: A drive circuit turns on an NPN transistor and a transistor in response to a turn-on command in a control signal to supply a positive current to a gate of a power transistor, and turns off the transistor after lapse of a certain time period to lower gate driving capability. The drive circuit turns on a PNP transistor and a transistor in response to a turn-off command in the control signal to supply a negative current to the gate of the power transistor, and turns off the transistor after lapse of a certain time period to lower gate driving capability.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeshi Horiguchi
  • Patent number: 10473699
    Abstract: An electronic device is described. The electronic device includes line voltage measuring circuitry configured to measure a line voltage to produce a line voltage measurement. The electronic device also includes load voltage measuring circuitry configured to measure a load voltage to produce a load voltage measurement. The electronic device further includes a processor coupled to the line voltage measuring circuitry and the load voltage measuring circuitry. The processor is configured to adjust a voltage ramp waveform for a transition of a first metal-oxide-semiconductor field-effect transistor (MOSFET) and a second MOSFET based on the line voltage measurement and the load voltage measurement to minimize heat generation and electromagnetic interference creation by the MOSFETs. The first MOSFET and the second MOSFET control a current to a load in an alternating current configuration.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 12, 2019
    Assignee: Control4 Corporation
    Inventors: Gregory Scott Smith, Sidney Lyle King, Robert Don Bruhn, Jr.
  • Patent number: 10396772
    Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 27, 2019
    Assignee: pSemi Corporation
    Inventors: Payman Shanjani, Eric S. Shapiro
  • Patent number: 10345142
    Abstract: A laser detection device can be used to protect an integrated circuit. The device includes a detection cell having a buried channel of a first conductivity type extending in a substrate of the integrated circuit. The substrate is of a second conductivity type. The detection cell also has a first electrical connection coupling a first point in the buried channel to a supply voltage rail, and a second electrical connection coupled to a second point in the buried channel. A detection circuit is coupled to the second point in the buried channel via the second electrical connection and adapted to detect a fall in the voltage at the second point.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 9, 2019
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Alexandre Sarafianos, Clement Champeix
  • Patent number: 10312885
    Abstract: A self-matching phase shifter/attenuator including several incremental impedance matched phase shifter/attenuator elements is disclosed. Each incremental impedance matched phase shifter element comprises a reactive component (such as either a capacitor or inductor) that can be coupled in shunt to the signal path. The shunt reactive component is coupled in series with a ground switch. When closed, the ground switch connects the shunt reactive component to ground. When the ground switch is open, the switch removes the shunt reactive component from the circuit. In addition, each incremental impedance matched phase shifter element comprises a series reactive component having a reactance that is typically equal and inverse of that of the shunt reactive component.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: June 4, 2019
    Assignee: pSemi Corporation
    Inventor: Ravindranath Shrivastava
  • Patent number: 10305412
    Abstract: In a semiconductor device in the related art, it has been necessary to match the threshold voltage of a power element with the circuit operation of a gate driver; accordingly, it has been difficult to realize the operation of the gate driver most appropriate for the employed power element. According to one embodiment, when a power element is turned off, the semiconductor device monitors the collector voltage of the power element, and increases the number of NMOS transistors that draw out charges from the gate of the power element in a period until the collector voltage becomes lower than the pre-set determination threshold, rather than in the period after the collector voltage becomes lower than the determination threshold.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Ojima, Yoshihiko Yokoi
  • Patent number: 10270349
    Abstract: A voltage generator including an oscillator having an output, a charge pump having an input and an output, the input of the charge pump being coupled to the output of the oscillator, a smoothing capacitor, a resistor having an input end and an output end, wherein the input end is coupled to the charge pump and the output end is coupled to the smoothing capacitor, and a shorting element connected in parallel with the resistor and which, when turned on, causes the resistor to be at least partially bypassed, wherein the voltage generator is configured to supply voltage to a radio frequency (RF) switch via the smoothing capacitor, and a frequency of the oscillator is controlled to be faster during a switching period of the RF switch.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: April 23, 2019
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 10261563
    Abstract: A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 16, 2019
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Ajay Kumar Bhatia
  • Patent number: 10262614
    Abstract: The present disclosure provides a scan driving circuit for driving an Nth-stage scanning line including: a pull-up control module for receiving a cascade signal of an upper stage and generating a scan level signal of the Nth-stage scanning line based on the cascade signal of the upper stage; a pull-up module for pulling down the scanning signal of the Nth-stage scanning line when the first clock signal is low according to the scan level signal and the first clock signal; the pull-up control module includes a first control unit and a second control unit, the control terminal of the second control unit inputs a second clock signal for controlling the scan level signal to become smaller when the second clock signal is at a high level. The present disclosure can prevent the waveform of the gate from appearing spikes, and thus the waveform of the gate is output normally.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Longqiang Shi, Congwei Liao
  • Patent number: 10255551
    Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: The Regents of The University of Michigan, Mythic, Inc.
    Inventors: David Alan Fick, Laura E. Fick, Skylar J. Skrzyniarz, Manar El-Chammas
  • Patent number: 10250177
    Abstract: A ground assembly includes a first layer, a second layer, and a bypass capacitor. The first layer includes a power ground, a communication ground spaced from the power ground, a conductive path defining a parasitic inductance and electrically coupled between the power ground and the communication ground, and an electrically insulating layer. At least a portion of the insulating layer is positioned between the power and communication grounds. The second layer includes a first substrate that is spaced from the power ground to define a first parasitic capacitance therebetween and is spaced from the communication ground to define a second parasitic capacitance therebetween. The bypass capacitor is electrically coupled between the power ground and the first substrate.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 2, 2019
    Assignee: Regal Beloit America, Inc.
    Inventors: Ming Li, Roger Carlos Becerra
  • Patent number: 10250999
    Abstract: A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 2, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francesco Polo, Richard Gaggl, Benno Muehlbacher, Luca Valli
  • Patent number: 10224924
    Abstract: A device includes a semiconductor body having an active region and a substrate region that is beneath the active region. A bidirectional switch is formed in the semiconductor body having first and second gate structures that are configured to block voltage across two polarities as between first and second input-output terminals that are in ohmic contact with the electrically conductive channel. First and second switching devices are configured to electrically connect the substrate region to the first and second input-output terminals, respectively. A passive electrical network includes a first capacitance connected between a control terminal of the first switching device and the second input-output terminal and a second capacitance connected between a control terminal of the second switching device and the first input-output terminal. The passive electrical network is configured temporarily electrically connect the substrate region to the first and second input-output terminal at different voltage conditions.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Kennith Kin Leong
  • Patent number: 10211655
    Abstract: A method for controlling a state of a battery includes: providing and using a specific connecting interface to connect the battery and a portable device; and controlling the battery to enter a shipping mode and exit the shipping mode by using the specific connecting interface.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: February 19, 2019
    Assignee: MediaTek Inc.
    Inventors: Jui-Chi Wu, Chi-Ming Lee, Chih-Yuan Hsu
  • Patent number: 10204882
    Abstract: A package module includes a power module, a first thermal dissipating component and a packaging plastic. The power module includes a substrate and at least one power semiconductor component disposed on the substrate. The first thermal dissipating component is disposed over the power module. The packaging plastic covers the power module and the first thermal dissipating component, wherein a portion of the first thermal dissipating component is exposed from the packaging plastic.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 12, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Le Liang, Shou-Yu Hong, Zhen-Qing Zhao
  • Patent number: 10193440
    Abstract: A power converter provides a pyramidal structure of switches communicating between a capacitive divider at the base of the pyramid and a terminal at the top of the pyramid to provide a transformation of a relationship between current and voltage in power transferred between the capacitive divider and the terminal at the top of the pyramid while providing reduced electrical interference and electrical rate of change (dv/dt).
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Venkata Giri Venkataramanan, Mahima Gupta, Daniel Ludois, Robert Mark Cuzner