DATA PROCESSING

Abstract

A data processor comprises a plurality of interconnected real processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units. At least one emulated processing unit is emulated by contributions from two or more real processing units; and at least one real processing unit contributes to emulating two or more emulated processing units.

Description

This invention relates to data processing.

As an example of data processing, electronic games are well known and may be supplied on a variety of distribution media, such as magnetic and/or optical discs. General computers or dedicated games consoles may be used to play these games.

There is sometimes a need to emulate the operation of one processor on another processor. That is to say, the emulating processor runs native program code arranged so that such native instructions or groups of native instructions have the same effect as data processing instructions relating to the emulated system.

A situation in which this need arises is where a data processor has been upgraded by the manufacturer to a new “generation”—for example, a new hardware architecture or instruction protocol, but the manufacturer still wants software relating to the older generation device to be handled (so-called backwards compatibility). Often the only way of achieving this is for the newer generation device to run emulation software which in turn acts in response to instructions relating to the older generation device. In this case, while it is of course acknowledged that running an emulation is generally much more processor-intensive than running native software, the general trend of generational improvements in the performance of data processing hardware is such that the increased processing overhead can usually be handled.

This invention provides a data processor comprising a plurality of interconnected real processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units, in which:

at least one emulated processing unit is emulated by contributions from two or more real processing units; and

at least one real processing unit contributes to emulating two or more emulated processing units.

The invention addresses a problem relevant to an emulating system which uses a multi-processor architecture, particularly (though not exclusively) one in which communication between processors (in the emulating system) is relatively slow compared to the general speed of operation of the emulating system. The invention recognises that a division of the emulation of an emulated processing unit between two (or more) emulating processing units can reduce the message traffic needed to provide communication between the emulations of those emulated processing units. Similarly, by grouping together (on a single emulating processing unit) the emulation of multiple processing units which normally communicate heavily with one another, once again the message traffic needed to provide communication between the emulations of those emulated processing units can be greatly reduced. These measures, taken together, can provide a faster and more efficient emulation.

Various further respective aspects and features of the invention are defined in the appended claims.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

FIG. 1 schematically illustrates the overall system architecture of the PlayStation2;

FIG. 2 schematically illustrates the architecture of an Emotion Engine;

FIG. 3 schematically illustrates the configuration of a Graphics Synthesiser;

FIG. 4 schematically illustrates the structure of an emulating processor, in particular a Sony® PlayStation 3® device;

FIG. 5 schematically illustrates a cell processor;

FIG. 6 schematically illustrates a graphics unit; and

FIG. 7 schematically illustrates logical interactions within the emulating processor.

Referring now to the drawings, FIG. 1 schematically illustrates the overall system architecture of the PlayStation2 computer games machine. A system unit 10 is provided, with various peripheral devices connectable to the system unit.

The system unit 10 comprises: an Emotion Engine 100; a Graphics Synthesiser 200; a sound processor unit 300 having dynamic random access memory (DRAM); a read only memory (ROM) 400; a compact disc (CD) and digital versatile disc (DVD) reader 450; a Rambus Dynamic Random Access Memory (RDRAM) unit 500; an input/output processor (IOP) 700 with dedicated RAM 750. An (optional) external hard disk drive (MD) 390 may be connected.

The input/output processor 700 has two Universal Serial Bus (USB) ports 715 and an iLink or IEEE 1394 port (iLink is the Sony Corporation implementation of the IEEE 1394 standard) (not shown). The IOP 700 handles all USB, iLink and game controller data traffic. For example when a user is playing a game, the IOP 700 receives data from the game controller and directs it to the Emotion Engine 100 which updates the current state of the game accordingly. The IOP 700 has a Direct Memory Access (DMA) architecture to facilitate rapid data transfer rates. DMA involves transfer of data from main memory to a device without passing it through the CPU. The USB interface is compatible with Open Host Controller Interface (OHCI) and can handle data transfer rates of between 1.5 Mbps and 12 Mbps. Provision of these interfaces means that the PlayStation2 is potentially compatible with peripheral devices such as digital video cassette recorders (VCRs) e.g. camcorders, digital cameras, microphones, printers, and input devices such as a keyboard, mouse and joystick.

Generally, in order for successful data communication to occur with a peripheral device connected to a USB port 715, an appropriate piece of software such as a device driver should be provided. Device driver technology is very well known and will not be described in detail here, except to say that the skilled man will be aware that a device driver or similar software interface may be required in the embodiment described here.

In the present embodiment, a USB microphone 730 is connected to the USB port. It will be appreciated that the USB microphone 730 may be a hand-held microphone or may form part of a head-set that is worn by the human operator. The advantage of wearing a head-set is that the human operator's hands are free to perform other actions. The microphone includes an analogue-to-digital converter (ADC) and a basic hardware-based real-time data compression and encoding arrangement, so that audio data are transmitted by the microphone 730 to the USB port 715 in an appropriate format, such as a streaming compressed audio format for decoding at the PlayStation 2 system unit 10.

Apart from the USB ports, two other ports 705, 710 are proprietary sockets allowing the connection of a proprietary non-volatile RAM memory card 720 for storing game-related information, a hand-held game controller 725 or a device (not shown) mimicking a hand-held controller, such as a dance mat.

The system unit 10 may be connected to a network adapter 805 that provides an interface (such as an Ethernet interface) to a network. This network may be, for example, a LAN, a WAN or the Internet. The network may be a general network or one that is dedicated to game related communication. The network adapter 805 allows data to be transmitted to and received from other system units 10 that are connected to the same network, (the other system units 10 also having corresponding network adapters 805).

The Emotion Engine 100 is a 128-bit Central Processing Unit (CPU) that has been specifically designed for efficient simulation of 3 dimensional (3D) graphics for games applications. The Emotion Engine components include a data bus, cache memory (part of its CPU core) and registers, all of which are 128-bit. This facilitates fast processing of large volumes of multi-media data. Conventional PCs, by way of comparison, have a basic 64-bit data structure. The floating point calculation performance of the PlayStation2 is 6.2 GFLOPs. The Emotion Engine also comprises MPEG2 decoder circuitry which allows for simultaneous processing of 3D graphics data and DVD data The Emotion Engine performs geometrical calculations including mathematical transforms and translations and also performs calculations associated with the physics of simulation objects, for example, calculation of friction between two objects. It produces sequences of image rendering commands which are subsequently utilised by the Graphics Synthesiser 200. The image rendering commands are output in the form of display lists. A display list is a sequence of drawing commands that specifies to the Graphics Synthesiser which primitive graphic objects (e.g. points, lines, triangles, sprites) to draw on the screen and at which co-ordinates. Thus a typical display list will comprise commands to draw vertices, commands to shade the faces of polygons, render bitmaps and so on. The Emotion Engine 100 can asynchronously generate multiple display lists.

The Graphics Synthesiser 200 is a video accelerator that performs rendering of the display lists produced by the Emotion Engine 100. The Graphics Synthesiser 200 includes a graphics interface unit (GIF) which handles, tracks and manages the multiple display lists. The rendering function of the Graphics Synthesiser 200 can generate image data that supports several alternative standard output image formats, i.e., NTSC/PAL, High Definition TV and VESA. In general, the rendering capability of graphics systems is defined by the memory bandwidth between a pixel engine and a video memory, each of which is located within the graphics processor. Conventional graphics systems use external Video Random Access Memory (VRAM) connected to the pixel logic via an off-chip bus which tends to restrict available bandwidth. However, the Graphics Synthesiser 200 of the PlayStation2 provides the pixel logic and the video memory on a single high-performance chip which allows for a comparatively large 38.4 Gigabyte per second memory access bandwidth. The Graphics Synthesiser is theoretically capable of achieving a peak drawing capacity of 75 million polygons per second. Even with a full range of effects such as textures, lighting and transparency, a sustained rate of 20 million polygons per second can be drawn continuously. Accordingly, the Graphics Synthesiser 200 is capable of rendering a film-quality image.

The Sound Processor Unit (SPU) 300 is effectively the soundcard of the system which is capable of handling 3D digital sound such as Digital Theater Surround (DTS®) sound and AC-3 (also known as Dolby Digital) which is the sound format used for DVDs.

A display and sound output device 305, such as a video monitor or television set with an associated loudspeaker arrangement 310, is connected to receive video and audio signals from the graphics synthesiser 200 and the sound processing unit 300.

The main memory supporting the Emotion Engine 100 is the RDRAM (Rambus Dynamic Random Access Memory) module 500 licensed by Rambus Incorporated. This RDRAM memory subsystem comprises RAM, a RAM controller and a bus connecting the RAM to the Emotion Engine 100.

FIG. 2 schematically illustrates the architecture of the Emotion Engine 100 of FIG. 1. The Emotion Engine 100 is a collective term for a number of processing units interconnected to give a desired set of functionality. Viewed in this context, the Emotion Engine comprises: a floating point unit (FPU) 104; a central processing unit (CPU) core 102; vector unit zero (VU0) 106; vector unit one (VU1) 108; a graphics interface unit (GIF) 110; an interrupt controller (INTC) 112; a timer unit 114; a direct memory access controller 116; an image data processor unit (IPU) 118; a dynamic random access memory controller (DRAMC) 120; a sub-bus interface (SIF) 122; and all of these individual processing units are connected via a 128-bit main bus 124.

The CPU core 102 is a 128-bit processor clocked at 300 MHz (in fact 294.912 MHz, but 300 MHz tends to be used as shorthand for this figure). The CPU core has access to 32 MB of main memory via the DRAMC 120. The CPU core 102 instruction set is based on MIPS III RISC with some MIPS IV RISC instructions together with additional multimedia instructions. MIPS III and IV are Reduced Instruction Set Computer (RISC) instruction set architectures proprietary to MIPS Technologies, Inc. Standard instructions are 64-bit, two-way superscalar, which means that two instructions can be executed simultaneously. Multimedia instructions, on the other hand, use 128-bit instructions via two pipelines. The CPU core 102 comprises a 16 KB instruction cache, an 8 KB data cache and a 16 KB scratchpad RAM which is a portion of cache connected by a dedicated bus to the CPU, allowing data access independent of the main bus.

The FPU 104 serves as a first co-processor for the CPU core 102. The vector unit 106 acts as a second co-processor. The FPU 104 comprises a floating point division calculator (FDIV). The vector units 106 and 108 perform mathematical operations and are essentially specialised FPUs that are extremely fast at evaluating the multiplication and addition of vector equations. They use Floating-Point Multiply-Adder Calculators (FMACs) for addition and multiplication operations and Floating-Point Dividers (FDIVs) for division and square root operations. The FMACs operate on 32-bit values so when an operation is carried out on a 128-bit value (composed of four 32-bit values) an operation can be carried out on all four parts concurrently. For example adding 2 vectors together can be done at the same time. The VUs have built-in memory for storing micro-programs and interface with the rest of the system via Vector Interface Units (VIFs) referred to by the same number as the corresponding Vector Unit. Vector unit zero 106 can work as a coprocessor to the CPU core 102 via a dedicated 128-bit bus so it is essentially a second specialised FPU. Vector unit one 108, on the other hand, has a dedicated bus to the Graphics synthesiser 200 and thus can be considered as a completely separate processor. The inclusion of two vector units allows the software developer to split up the work between different parts of the CPU and the vector units can be used in either serial or parallel connection.

Vector unit zero 106 comprises 4 FMACS and 1 FDIV. It is connected to the CPU core 102 via a coprocessor connection. It has 4 KB of vector unit memory for data and 4 KB of micro-memory for instructions. Vector unit zero 106 is useful for performing physics calculations associated with the images for display. It primarily executes non-patterned geometric processing together with the CPU core 102.

Vector unit one 108 comprises 5 FMACS and 2 FDIVs. It has no direct path to the CPU core 102, although it does have a direct path to the GIF unit 110. It has 16 KB of vector unit memory for data and 16 KB of micro-memory for instructions. Vector unit one 108 is useful for performing transformations. It primarily executes patterned geometric processing and directly outputs a generated display list to the GIF 110.

The GIF 110 is an interface unit to the Graphics Synthesiser 200. It converts data according to a tag specification at the beginning of a display list packet and transfers drawing commands to the Graphics Synthesiser 200 whilst mutually arbitrating multiple transfer. The interrupt controller (INTC) 112 serves to arbitrate interrupts from peripheral devices, except the DMAC 116.

The timer unit 114 comprises four independent timers with 16-bit counters. The timers are driven either by the bus clock (at 1/16 or 1/256 intervals) or via an external clock. The DMAC 116 handles data transfers between main memory and scratchpad RAM, or between main memory or scratchpad RAM and peripherals. It arbitrates the main bus 124 at the same time. Performance optimisation of the DMAC 116 is a key way by which to improve Emotion Engine performance. The image processing unit (IPU) 118 is an image data processor that is used to expand compressed animations and texture images. It performs macro-Block decoding, colour space conversion and vector quantisation. Finally, the sub-bus interface (SIF) 122 is an interface unit to the IOP 700. The IPU has its own memory and bus to control 10 devices such as sound chips and storage devices.

FIG. 3 schematically illustrates the configuration of the Graphic Synthesiser 200. The Graphics Synthesiser comprises: a host interface 202; a pixel pipeline 206; a memory interface 208; a local memory 212 including a frame page buffer 214 and a texture page buffer 216; and a video converter 210.

The host interface 202 transfers data with the host (in this case the GIF 110). Both drawing data and buffer data from the host pass through this interface. The output from the host interface 202 is supplied to the graphics synthesiser 200 which develops the graphics to draw pixels based on vertex information received from the Emotion Engine 100, and calculates information such as RGBA value, depth value (i.e. Z-value), texture value and fog value for each pixel. The RGBA value specifies the red, green, blue (RGB) colour components and the A (Alpha) component represents opacity of an image object. The Alpha value can range from completely transparent to totally opaque. The pixel data is supplied to the pixel pipeline 206 which performs processes such as texture mapping, fogging and Alpha-blending and determines the final drawing colour based on the calculated pixel information.

The pixel pipeline 206 comprises 16 pixel engines PE1, PE2, . . . , PE16 so that it can process a maximum of 16 pixels concurrently. The pixel pipeline 206 runs at 150 MHz (in fact 294.912/2 MHz) with 32-bit colour and a 32-bit Z-buffer. The memory interface 208 reads data from and writes data to the local Graphics Synthesiser memory 212. It writes the drawing pixel values (RGBA and Z) to memory at the end of a pixel operation and reads the pixel values of the frame buffer 214 from memory. These pixel values read from the frame buffer 214 are used for pixel test or Alpha-blending. The memory interface 208 also reads from local memory 212 the RGBA values for the current contents of the frame buffer. The local memory 212 is a 32 Mbit (4 MB) memory that is built-in to the Graphics Synthesiser 200. It can be organised as a frame buffer 214, texture buffer 216 and a Z-buffer 215. The frame buffer 214 is the portion of video memory where pixel data such as colour information is stored.

The Graphics Synthesiser uses a 2D to 3D texture mapping process to add visual detail to 3D geometry. Each texture may be wrapped around a 3D image object and is stretched and skewed to give a 3D graphical effect. The texture buffer is used to store the texture information for image objects. The Z-buffer 215 (also known as depth buffer) is the memory available to store the depth information for a pixel. Images are constructed from basic building blocks known as graphics primitives or polygons. When a polygon is rendered with Z-buffering, the depth value of each of its pixels is compared with the corresponding value stored in the Z-buffer. If the value stored in the Z-buffer is greater than or equal to the depth of the new pixel value then this pixel is determined visible so that it should be rendered and the Z-buffer will be updated with the new pixel depth. If however the Z-buffer depth value is less than the new pixel depth value the new pixel value is behind what has already been drawn and will not be rendered. Alternative Z-buffer tests are available, so that (a) the new pixel always replaces the previous value, or (b) the new pixel replaces the previous pixel value if its depth is greater than or equal to the previous value stored in the Z buffer.

The local memory 212 has a 1024-bit read port and a 1024-bit write port for accessing the frame buffer and Z-buffer and a 512-bit port for texture reading. The video converter 210 is operable to display the contents of the frame memory in a specified output format.

An arrangement will now be described to allow the emulation of the system described with reference to FIGS. 1 to 3. Note that for convenience, the processing units shown in FIGS. 1 to 3 will be referred to as “emulated” processing units, whereas in the emulating system to be described below, processing units of that (emulating)-system will be referred to as “emulating” processing units. To avoid any-possible confusion, note that both categories of processing units (“emulated” and “emulating” processing units) represent physical processing units capable of running native software appropriate to those processing units.

FIG. 4 schematically illustrates the overall system architecture of the Sony® Playstation 3® entertainment device. A system unit 910 is provided, with various peripheral devices connectable to the system unit.

The system unit 910 comprises: a Cell processor 1100; a Rambus® dynamic random access memory (XDRAM) unit 1500; a Reality Synthesiser graphics unit 1200 with a dedicated video random access memory (VRAM) unit 1250; and an I/O bridge 1700.

The system unit 910 also comprises a Blu Ray® Disk BD-ROM® optical disk reader 1430 for reading a disk 1440 and a removable slot-in hard disk drive (HDD) 1400, accessible through the I/O bridge 1700. Optionally the system unit also comprises a memory card reader 1450 for reading compact flash memory cards, Memory Stick® memory cards and the like, which is similarly accessible through the I/O bridge 1700.

The I/O bridge 1700 also connects to six Universal Serial Bus (USB) 2.0 ports 1710; a gigabit Ethernet port 1720; an IEEE 802.11b/g wireless network (Wi-Fi) port 1730; and a Bluetooth® wireless link port 1740 capable of supporting of up to seven Bluetooth connections.

In operation the I/O bridge 1700 handles all wireless, USB and Ethernet data, including data from one or more game controllers 1751. For example when a user is playing a game, the I/O bridge 1700 receives data from the game controller 1751 via a Bluetooth link and directs it to the Cell processor 1100, which updates the current state of the game accordingly.

The wireless, USB and Ethernet ports also provide connectivity for other peripheral devices in addition to game controllers 1751, such as: a remote control 1752; a keyboard 1753; a mouse 1754; a portable entertainment device 1755 such as a Sony Playstation Portable® entertainment device; a video camera such as an EyeToy® video camera 1756; and a microphone headset 1757. Such peripheral devices may therefore in principle be connected to the system unit 910 wirelessly; for example the portable entertainment device 1755 may communicate via a Wi-Fi ad-hoc connection, whilst the microphone headset 1757 may communicate via a Bluetooth link.

The provision of these interfaces means that the Playstation 3 device is also potentially compatible with other peripheral devices such as digital video recorders (DVRs), set-top boxes, digital cameras, portable media players, Voice over IP telephones, mobile telephones, printers and scanners.

In addition, a legacy memory card reader 1410 may be connected to the system unit via a USB port 1710, enabling the reading of memory cards 1420 of the kind used by the Playstation® or Playstation 2® devices.

In the present embodiment, the game controller 1751 is operable to communicate wirelessly with the system unit 910 via the Bluetooth link. However, the game controller 1751 can instead be connected to a USB port, thereby also providing power by which to charge the battery of the game controller 1751. In addition to one or more analogue joysticks and conventional control buttons, the game controller is sensitive to motion in 6 degrees of freedom, corresponding to translation and rotation in each axis. Consequently gestures and movements by the user of the game controller may be translated as inputs to a game in addition to or instead of conventional button or joystick commands. Optionally, other wirelessly enabled peripheral devices such as the Playstation Portable device may be used as a controller. In the case of the Playstation Portable device, additional game or control information (for example, control instructions or number of lives) may be provided on the screen of the device. Other alternative or supplementary control devices may also be used, such as a dance mat (not shown), a light gun (not shown), a steering wheel and pedals (not shown) or bespoke controllers, such as a single or several large buttons for a rapid-response quiz game (also not shown).

The remote control 1752 is also operable to communicate wirelessly with the system unit 910 via a Bluetooth link. The remote control 1752 comprises controls suitable for the operation of the Blu Ray Disk BD-ROM reader 1430 and for the navigation of disk content.

The Blu Ray Disk BD-ROM reader 1430 is operable to read CD-ROMs compatible with the Playstation and PlayStation 2 devices, in addition to conventional pre-recorded and recordable CDs, and so-called Super Audio CDs. The reader 1430 is also operable to read DVD-ROMs compatible with the Playstation 2 and PlayStation 3 devices, in addition to conventional pre-recorded and recordable DVDs. The reader 1430 is further operable to read BD-ROMs compatible with the Playstation 3 device, as well as conventional pre-recorded and recordable Blu-Ray Disks.

The system unit 910 is operable to supply audio and video, either generated or decoded by the Playstation 3 device via the Reality Synthesiser graphics unit 1200, through audio and video connectors to a display and sound output device 1300 such as a monitor or television set, having a display screen 1305 and one or more loudspeakers 1310. The audio connectors 1210 may include conventional analogue and digital outputs whilst the video connectors 1220 may variously include component video, S-video, composite video and one or more High Definition Multimedia Interface (HDMI) outputs. Consequently, video output may be in formats such as PAL or NTSC, or in 720p, 1080i or 1080p high definition.

Audio processing (generation, decoding and so on) is performed by the Cell processor 1100. The Playstation 3 device's operating system supports Dolby® 5.1 surround sound, Dolby® Theatre Surround (DTS), and the decoding of 7.1 surround sound from Blu-Ray® disks.

In the present embodiment, the video camera 1756 comprises a single charge coupled device (CCD), an LED indicator, and hardware-based real-time data compression and encoding apparatus so that compressed video data may be transmitted in an appropriate format such as an intra-image based MPEG (motion picture expert group) standard for decoding by the system unit 910. The camera LED indicator is arranged to illuminate in response to appropriate control data from the system unit 910, for example to signify adverse lighting conditions. Embodiments of the video camera 1756 may variously connect to the system unit 910 via a USB, Bluetooth or Wi-Fi communication port. Embodiments of the video camera may include an associated microphone and also be capable of transmitting audio data. In embodiments of the video camera, the CCD may have a resolution suitable for high-definition video capture. In use, images captured by the video camera may for example be incorporated within a game or interpreted as game control inputs.

In general, in order for successful data communication to occur with a peripheral device such as a video camera or remote control via one of the communication ports of the system unit 910, an appropriate piece of software such as a device driver should be provided. Device driver technology is well-known and will not be described in detail here, except to say that the skilled man will be aware that a device driver or similar software interface may be required in the present embodiment described.

Referring now to FIG. 5, the Cell processor 1100 has an architecture comprising four basic components: external input and output structures comprising a memory controller 1160 and a dual bus interface controller 1170A,B; a main processor referred to as the Power Processing Element (PPE) 1150; eight co-processors referred to as Synergistic Processing Elements (SPEs) 1110A-H; and a circular data bus connecting the above components referred to as the Element Interconnect Bus 1180. The total floating point performance of the Cell processor is 218 GFLOPS, compared with the 6.2 GFLOPs of the Playstation 2 device's Emotion Engine.

The Power Processing Element (PPE) 1150 is based upon a two-way simultaneous multithreading Power 970 compliant PowerPC core (PP) 1155 running with an internal clock of 3.2 GHz. It comprises a 512 kB level 2 (L2) cache and a 32 kB level 1 (L1) cache. The PPE 1150 is capable of eight single position operations per clock cycle, translating to 25.6 GFLOPs at 3.2 GHz. The primary role of the PPE 1150 is to act as a controller for the Synergistic Processing Elements 111A-H, which handle most of the computational workload. In operation the PPE 1150 maintains a job queue, scheduling jobs for the Synergistic Processing Elements 1110A-H and monitoring their progress. Consequently each Synergistic Processing Element 110A-H runs a kernel whose role is to fetch a job, execute it and synchronise with the PPE 1150.

Each Synergistic Processing Element (SPE) 1110A-H comprises a respective Synergistic Processing Unit (SPU′—to distinguish it from the Sound Processing Unit mentioned above) 1120A-H, and a respective Memory Flow Controller (MFC) 1140A-H comprising in turn a respective Dynamic Memory Access Controller (DMAC) 1142A-H, a respective Memory Management Unit (MMU) 1144A-H and a bus interface (not shown). Each SPU′ 1120A-H is a RISC processor clocked at 3.2 GHz and comprising 256 kB local RAM 1130A-H, expandable in principle to 4 GB. Each SPE gives a theoretical 25.6 GFLOPS of single precision performance. An SPU′ can operate on 4 single precision floating point members, 4 32-bit numbers, 8 16-bit integers, or 16 8-bit integers in a single clock cycle. In the same clock cycle it can also perform a memory operation. The SPU′ 1120A-H does not directly access the system memory XDRAM 1500; the 64-bit addresses formed by the SPU′ 1120A-H are passed to the MFC 1140A-H which instructs its DMA controller 1142A-H to access memory via the Element Interconnect Bus 1180 and the memory controller 1160.

The Element Interconnect Bus (FIB) 1180 is a logically circular communication bus internal to the Cell processor 1100 which connects the above processor elements, namely the PPE 1150, the memory controller 1160, the dual bus interface 1170A,B and the 8 SPEs 1110A-H, totalling 12 participants. Participants can simultaneously read and write to the bus at a rate of 8 bytes per, clock cycle. As noted previously, each SPE 1110A-H comprises a DMAC 1142A-H for scheduling longer read or write sequences. The EIB comprises four channels, two each in clockwise and anti-clockwise directions. Consequently for twelve participants, the longest step-wise data-flow between any two participants is six steps in the appropriate direction. The theoretical peak instantaneous EIB bandwidth for 12 slots is therefore 96 B (bytes) per clock, in the event of full utilisation through arbitration between participants. This equates to a theoretical peak bandwidth of 307.2 GB/s (gigabytes per second) at a clock rate of 3.2 GHz.

The memory controller 1160 comprises an XDRAM interface 1162, developed by Rambus Incorporated. The memory controller interfaces with the Rambus XDRAM 1500 with a theoretical peak bandwidth of 25.6 GB/s.

The dual bus interface 1170A,B comprises a Rambus FlexIO® system interface 1172A,B. The interface is organised into 12 channels each being 8 bits wide, with five paths being inbound and seven outbound. This provides a theoretical peak bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) between the Cell processor and the I/O Bridge 1700 via the controller 1170A and the Reality Simulator graphics unit 1200 via controller 1170B.

Data sent by the Cell processor 1100 to the Reality Simulator graphics unit 1200 will typically comprise display lists, being a sequence of commands to draw vertices, apply textures to polygons, specify lighting conditions, and so on.

Referring now to FIG. 6, the Reality Simulator graphics (RSX) unit 1200 is a video accelerator based upon the NVidia® G70/71 architecture that processes and renders lists of commands produced by the Cell processor 1100. The RSX unit 1200 comprises a host interface 1202 operable to communicate with the bus interface controller 1170B of the Cell processor 1100; a vertex pipeline 1204 (VP) comprising eight vertex shaders 1205; a pixel pipeline 1206 (PP) comprising 24 pixel shaders 1207; a render pipeline 1208 (RP) comprising eight render output units (ROPs) 1209; a memory interface 1210; and a video converter 1212 for generating a video output. The RSX 1200 is complemented by 256 MB double data rate (DDR) video RAM (VRAM) 1250, clocked at 600 MHz and operable to interface with the RSX 1200 at a theoretical peak bandwidth of 25.6 GB/s. In operation, the VRAM 1250 maintains a frame buffer 1214 and a texture buffer 1216. The texture buffer 1216 provides textures to the pixel shaders 1207, whilst the frame buffer 1214 stores results of the processing pipelines. The RSX can also access the main memory 1500 via the EIB 1180, for example to load textures into the VRAM 1250.

The vertex pipeline 1204 primarily processes deformations and transformations of vertices defining polygons within the image to be rendered.

The pixel pipeline 1206 primarily processes the application of colour, textures and lighting to these polygons, including any pixel transparency, generating red, green, blue and alpha (transparency) values for each processed pixel. Texture mapping may simply apply a graphic image to a surface, or may include bump-mapping (in which the notional direction of a surface is perturbed in accordance with texture values to create-highlights and shade in the lighting model) or displacement mapping (in which the applied texture additionally perturbs vertex positions to generate a deformed surface consistent with the texture).

The render pipeline 1208 performs depth comparisons between pixels to determine which should be rendered in the final image. Optionally, if the intervening pixel process will not affect depth values (for example in the absence of transparency or displacement mapping) then the render pipeline and vertex pipeline 1204 can communicate depth information between them, thereby enabling the removal of occluded elements prior to pixel processing, and so improving overall rendering efficiency. In addition, the render pipeline 1208 also applies subsequent effects such as full-screen anti-aliasing over the resulting image.

Both the vertex shaders 1205 and pixel shaders 1207 are based on the shader model 3.0 standard. Up to 136 shader operations can be performed per clock cycle, with the combined pipeline therefore capable of 74.8 billion shader operations per second, outputting up to 840 million vertices and 10 billion pixels per second. The total floating point performance of the RSX 1200 is 1.8 TFLOPS.

Typically, the RSX 1200 operates in close collaboration with the Cell processor 1100; for example, when displaying an explosion, or weather effects such as rain or snow, a large number of particles must be tracked, updated and rendered within the scene. In this case, the PPU 1155 of the Cell processor may schedule one or more SPEs 1110A-H to compute the trajectories of respective batches of particles. Meanwhile, the RSX 1200 accesses any texture data (e.g. snowflakes) not currently held in the video RAM 1250 from the main system memory 1500 via the element interconnect bus 1180, the memory controller 1160 and a bus interface controller 1170B. The or each SPE 1110A-H outputs its computed particle properties (typically coordinates and normals, indicating position and attitude) directly to the video RAM 1250; the DMA controller 1142A-H of the or each SPE 1110A-H addresses the video RAM 1250 via the bus interface controller 1170B. Thus in effect the assigned SPEs become part of the video processing pipeline for the duration of the task.

In general, the PPU 1155 can assign tasks in this fashion to six of the eight SPEs available; one SPE is reserved for the operating system, whilst one SPE is optionally disabled. The disabling of one SPE provides a greater level of tolerance during fabrication of the Cell processor, as it allows for one SPE to fail the fabrication process. Alternatively if all eight SPEs are functional, then the eighth SPE provides scope for redundancy in the event of subsequent failure by one of the other SPEs during the life of the Cell processor.

The PPU 1155 can assign tasks to SPEs in several ways. For example, SPEs may be chained together to handle each step in a complex operation, such as accessing a DVD, video and audio decoding, and error masking, with each step being assigned to a separate SPE. Alternatively or in addition, two or more SPEs may be assigned to operate on input data in parallel, as in the particle animation example above.

Software instructions implemented by the Cell processor 1100 and/or the RSX 1200 may be supplied at manufacture and stored on the HDD 1400, and/or may be supplied on a data carrier or storage medium such as an optical disk or solid state memory, or via a transmission medium such as a wired or wireless network or internet connection, or via combinations of these.

The software supplied at manufacture comprises system firmware and the Playstation 3 device's operating system (OS). In operation, the OS provides a user interface enabling a user to select from a variety of functions, including playing a game, listening to music, viewing photographs, or viewing a video. The interface takes the form of a so-called cross media-bar (XMB), with categories of function arranged horizontally. The user navigates by moving through the functions horizontally using a game controller 1751, remote control 1752 or other suitable control device so as to highlight the desired function, at which point options pertaining to that function appear as a vertically scrollable list centred on that function, which may be navigated in analogous fashion. However, if a game, audio or movie disk 1440 is inserted into the BD-ROM optical disk reader 1430, the Playstation 3 device may select appropriate options automatically (for example, by commencing the game), or may provide relevant options (for example, to select between playing an audio disk or compressing its content to the HDD 1400).

In addition, the OS provides an on-line capability, including a web browser, an interface with an on-line store from which additional game content, demos and other media may be downloaded, and a friends management capability, providing on-line communication with other Playstation 3 device users nominated by the user of the current device; for example, by text, audio or video depending on the peripheral devices available. The on-line capability also provides for on-line communication, content download and content purchase during play of a suitably configured game, and for updating the firmware and OS of the Playstation 3 device itself.

The operation of the PS2 arrangement described with reference to FIGS. 1 to 3 is reproduced (or very nearly reproduced) by software running on the arrangement of FIGS. 4 to 6, despite the fact that the emulating processing units of FIGS. 4 to 6 have tin general terms) a different architecture, speed, memory accessing capabilities and so on, compared to the emulated processing units of FIGS. 1 to 3.

The reproduction of the operation of the PS2 arrangement is an emulation rather than a simulation. That is to say, it is not the case that all of the operations contributing to the functionality of the PS2 are reproduced by the emulating system in a lock-step, clock-by-clock manner. Rather, some functions may be carried out by time division on a single emulating processing unit, and in general the processing units communicate with one another only when there is a need (within the emulated system) to do so.

The PPE 1150 controls the overall operation of the emulating system and runs an operating system (OS) for the emulating system. It also has one thread which provides interpretation of native Emotion Engine PS2 instructions into native SPE instructions which it supplies, with any associated information (such as allocation of emulation functions—see below) which is required to carry out the respective part of the emulation, to the relevant SPEs via the EIB, while another thread provides the function of recompiling new code native to the emulating system to provide the particular functionality defined by the interpreted PS2 code. Emulation of the various parts of the PS2 system described above is devolved to the eight SPEs acting as emulating processing units, which emulate PS2 functionality as set out below. It will be appreciated that the precise identity of the individual SPEs is just a convenient notation and has no technical significance because of the nature of the message-passing interface between the SPEs. So, for example, the operations assigned to the SPEs 1110A and 1110B could be swapped in their entirety with no technical effect on the overall emulation process. It will also be appreciated that the disabling of one SPE can be carried out as mentioned above, so that the tasks are in fact divided amongst the remaining seven SPEs.

SPE 1110A IPU 118
SPE 1110B Emotion Engine CPU 102 and Vector Unit 0
SPE 1110C VIF 0, VIF 1, GIF 110
SPE 1110D Vector Unit 1
SPE 1110E GS 200 (i.e. that part of the operation of the GS 200
          specific to the PS2 system; the SPE 1110G also interfaces
          with a graphics controller of the emulating system (not
          shown) for non-PS2-specific graphics operations)
SPE 1110F generally unused, but can be used to recompile code to
          emulate Vector Unit 1, to ease the load on the one thread
          of the PPE 1150 described above
SPE 1110G SPU 300
SPE 1110H IOP 700 and SIF 122

The PS2 used a conventional bus for communication between the various emulated processing units. The emulating system makes use of the EIB 1180 for passing messages between SPEs and between an SPE, the PPE 1150 and the I/O bridge 1700 (and/or other system devices such as the RSX 1200). The PS2 system had conventional memory access arrangements to access the RDRAM 500. The emulating system uses a distributed DMA system (the DMA controllers 1142A-H). The main system memory 1500 is treated as a common memory “pool”, with all SPEs having access to it.

Each of the SPEs runs locally, on its own time clock The SPEs run software to allow parts of the functionality of the PS2 system to be emulated. As between EPUs, synchronisation is required only when the emulated processing units emulated by the EPUs need to communicate with one another. At that time, synchronisation takes place just between the devices concerned, using a message transfer mechanism via the EIB.

To achieve this, when synchronisation (of emulated functionality) is required between two SPEs, one of the SPEs places a message onto the EIB (including a source SPE identifier, a destination SPE identifier etc), addressed to the other of the SPEs. The message may include a request for a certain piece of data, or may include a data item which is being sent to that other SPE involved in that particular synchronisation. When an acknowledgement is returned by that other SPE, the transaction is complete. This is a reliable but rather slow method of synchronising two emulated processors.

The way in which the SPEs are logically arranged is shown schematically in FIG. 5. Example paths of logical communication between the SPEs are also shown, although these need not be exhaustive. It can be seen that some functions are shared on the same SPE which avoids entirely the need to use the message-passing mechanism to communicate between them. So, providing the emulation of two (or more) emulated processing units on a single SPE can improve the system's performance by reducing the amount of inter-SPE communication needed.

Another feature which is not exhaustively indicated on FIG. 5, for clarity of the diagram, is that where the emulated processing units emulated by two different SPEs need to communicate with one another a lot in order to carry out particular functions of the PS2, a part of the functionality of one real processor can be carried out by the “other” processor's SPE.

For example, the PS2 sound processing unit is mostly emulated on one SPE. This processes samples and mixes them into the final samples for output. It also processes accesses to its register map. However, the registers used to write to sound processing unit sample memory are emulated on the IOP's SPE which manages the queuing of accesses, directly accesses the sample memory image in main memory, and raises any interrupts these might cause as though they had been routed from the sound processing unit.

Another example of a device in the PS2 system which is implemented on more than one SPE is the DMAC, whose function is distributed between the emulating components primarily used for the Emotion Engine, VIF, GIF, IPU and others.

An example of one emulating SPE handling the emulation of multiple PS2 system devices is that the emulation of the PS2's IOP is shared (on a single emulating device) with the bulk of the emulation of a CD disk controller.

This division of the emulation of an emulated processing unit between two (or more) SPEs (emulating processing units) again can reduce the message traffic needed to provide communication between the emulations of those emulated processing units. The PPE can vary the distribution of emulation tasks between the SPEs (during an overall emulation operation), so as to alter which SPE emulates a particular emulated processing unit, and/or which emulated processing units are emulated by a particular SPE.

In so far as the embodiments of the invention described above are implemented, at least in part, using software-controlled data processing apparatus, it will be appreciated that a computer program providing such software control, a storage medium by which such a computer program is stored and a transmission medium by which such a computer program is transmitted are envisaged as aspects of the present invention. It is noted that such software may be provided on a storage medium such as an optical disk or a hardware memory, an/or via a transmission medium such as a network connection or the internet.

Claims

1. A data processor comprising a plurality of interconnected emulating processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units, in which:

at least one emulated processing unit is emulated by contributions from two or more emulating processing units; and

at least one emulating processing unit contributes to emulating two or more emulated processing units.

2. A data processor according to claim 1, in which the emulating processing units communicate with one another by a message-passing communication protocol.

3. A data processor according to claim 2, in which the emulating processing units are arranged to synchronise emulated operations via the message-passing communication protocol.

4. A data processor according to claim 2, in which the emulating processing units are interconnected by a circular data bus.

5. A data processor according to claim 4, in which the data bus is bidirectional.

6. A data processor according to claim 1, comprising a supervisory processor to interpret instructions relating to an emulated processor and provide information to the emulating processing units to allow the interpreted instructions to be executed.

7. A data processor according to claim 6, in which the information supplied to the emulating processing units comprises object code, native to the emulating processing units.

8. A data processor according to claim 6, in which the supervisory processor is operable to vary the allocation of emulation tasks to the emulating processing units, so as to change which emulated processing units are emulated by an emulating processing unit.

9. A data processing method relating to a system having a plurality of interconnected emulating processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units;

the method comprising the steps of:

emulating an emulated processing unit by contributions from two or more emulating processing units; and

emulating two or more emulated processing units by one emulating processing unit.

10. Computer software for carrying out a method according to claim 9.

11. A medium by which computer software according to claim 10 is provided.

12. A medium according to claim 11, the medium being a storage medium.

13. A medium according to claim 11, the medium being a transmission medium.