METHOD OF ETCHING A DIELECTRIC LAYER

Abstract

A method of etching a dielectric layer includes providing a substrate, which includes a dielectric layer and a metal layer, performing a first etching process on the metal layer, and performing a second etching process on the dielectric layer to form a opening in the dielectric layer. The first etching process and the second etching process are in-situ carried out in the same reaction chamber without a vent. Since the first and second etching processes are not performed in different reaction chambers respectively, the cycle time can therefore be improved in the present invention. Because the first and second etching processes are performed without a vent, the substrate is protected from the pollution existing in surrounding.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of etching a dielectric layer, and more particularly, to a method of etching a dielectric layer by utilizing a metal hard mask as an etching mask.

2. Description of the Prior Art

Devices in the semiconductor industry need to undergo several complicated processes such as a photolithograph process, a dry or wet etching process, an ion implantation, and a heat treatment, etc. to construct precise integrated circuits in layers. Among those complicated processes, the process control of dielectric layer etching has become a critical factor, particularly in some applications such as a damascene process or an interconnection technique. For example, in a damascene process, a dielectric layer is etched to form patterns comprising trenches or via. Next the trenches or via are filled with copper, and a planarization process is performed to complete formation of the damascene structure. Additionally, to satisfy requirements of low RC delay effects, a low-K material, an ultra low-k (ULK) material, or a porous low-k material is used to be the dielectric layer in the damascene structure.

Please refer to FIG. 1 through FIG. 2, which are schematic diagrams of the traditional method of etching a dielectric layer. As shown in FIG. 1, a substrate 12 is first provided. The substrate 12 has a dielectric layer 18 thereon. Thereafter, a patterned photoresist 24 is formed on the dielectric layer 18, and an opening 26 of a conductive line pattern is defined in the patterned photoresist 24. As shown in FIG. 2, an etching process is afterward performed to etch the dielectric layer 18 through the opening 26 of the patterned photoresist 24 so that a trench 28 is formed in the dielectric layer 18. The etching process is performed until exposing the substrate 12.

Since the process of etching the dielectric layer 18 also causes a great loss of the patterned photoresist 24, the patterned photoresist 24 formed on the dielectric layer 18 must be thick enough for masking the dielectric layer 18. However, when the integrated density of semiconductor devices gets higher, the critical dimension (CD) of etch element becomes smaller, and the aspect ratio of the opening 28 becomes higher. The trend to fabricate semiconductor devices with smaller features, has presented difficulties when attempting to form the opening 28 with a high aspect ratio in the dielectric layer 18. For example, the etching by-products are easily piled up in the opening 28. As a result, the traditional method of etching the dielectric layer by utilizing the patterned photoresist 24 as the only etching mask is insufficient for the micro-miniaturization. Accordingly, it is still an important issue to provide an effective etching method without destroying the patterns of the dielectric layer.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the present invention to provide a method of etching a dielectric layer to solve the above-mentioned problem.

From one aspect of the present invention, a method of etching a dielectric layer is disclosed. First, a substrate is provided. The substrate includes a base layer, a dielectric layer and a metal layer. The dielectric layer and the metal layer are disposed above the base layer. Subsequently, a first etching process is performed on the metal layer to turn the metal layer into a patterned metal layer. Next, a second etching process is performed on the dielectric layer to form at least one opening in the dielectric layer. The first etching process and the second etching process are performed in a same reaction chamber.

It is an advantage of the present invention that the cycle time can therefore be improved, and the substrate is protected from the pollution existing in the surrounding environment, since the first and second etching process are not performed in different reaction chambers respectively.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

FIG. 1 through FIG. 2 are schematic diagrams of the traditional method of etching a dielectric layer;

FIGS. 3-6 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with one preferred embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a reaction chamber provided in the present invention;

FIGS. 8-10 are schematic diagrams illustrating a method of forming an opening of a dual damascene structure in accordance with another preferred embodiment of the present invention; and

FIGS. 11-14 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with another preferred embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 3 through FIG. 7. FIGS. 3-6 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with one preferred embodiment of the present invention, where FIG. 7 is a schematic diagram illustrating a reaction chamber provided in the present invention. A trench structure is formed in this preferred embodiment. Like number numerals designate similar or the same parts, regions or elements. It is to be understood that the drawings are not drawn to scale and are used only for illustration purposes, and that some lithographic and etching processes relating to the present invention method are known in the art and thus not explicitly shown in the drawings.

As shown in FIG. 3, a semiconductor substrate 100 is first provided. The semiconductor substrate 100 includes a base layer 102, a liner layer 103 disposed on the base layer 102, a dielectric layer 104 disposed on the liner layer 103, a cap layer 106 disposed on the dielectric layer 104, and a metal layer 108 disposed on the cap layer 106. Subsequently, a cap layer 110, a bottom anti-reflection coating layer (BARC layer) 112 and a patterned photoresist 114 are formed over the metal layer 108 in turn.

The opening of the patterned photoresist 114 can include a predetermined pattern for the subsequent process, such as a trench pattern, and can expose parts of the BARC layer 112. The base layer 102 can include a dielectric layer and a plurality of conducting lines disposed in the dielectric layer. The detail structure of the base layer 102 can be adjusted according to the product design, so is not shown in the drawings. The metal layer 108 can serve as a hard mask during the follow-up etching processes, and is preferably a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer. The cap layer 106 or the cap layer 110 can include a silicon carbide (SiC), tetra-ethyl-ortho-silicate (TEOS), or silicon oxynitride (SiON). In addition, the dielectric layer 104 can include a low-k material (k≦2.9), such as fluoride silicate glass (FSG), organosilicate (OSG), or ultra low-k (ULK) materials. The liner layer 103 can be applied to a copper (Cu) process to prevent copper from diffusing into the adjacent dielectric layers. In addition, the liner layer 103 can also function as an etching stop layer. The liner layer 103 can include silicon nitride compounds, silicon oxide compounds, or silicon carbide compounds, such as SiC, SiN, SiON, SiCn, or NBLOK.

As shown in FIG. 4, an etching process is next performed to etch the BARC layer 112 and the cap layer 110 by utilizing the patterned photoresist 114 as an etching mask. In this embodiment, the process of etching the BARC layer 112 can include a trifluoromethane (CHF₃) gas and a tetrafluoromethane (CF₄) gas. The flowing rate of the CHF₃ gas can be about 70 standard cubic centimeters per minute (sccm), and the flowing rate of the CF₄ gas can be about 110 sccm.

Furthermore, as shown in FIG. 5, another etching process is carried out to etch the metal layer 108 by utilizing the patterned photoresist 114 as an etching mask. This etching process can turn the metal layer 108 into a patterned metal layer 108a, and is performed until exposing the cap layer 106. The process of etching the metal layer 108 can be a plasma etching process, and usually includes an effective and potent corrosive as an etching gas, such as sulfur hexafluoride (SF₆) gas or chlorine (Cl₂) gas. For instance, the process of etching the metal layer 108 can include an argon (Ar) gas and a chlorine gas. The flowing rate of the Ar gas can be about 200 sccm, and the flowing rate of the Cl₂ gas can be about 75 sccm. Afterward, a flash process can be optionally performed (in other words, the flash process can be omitted in other embodiments). In the flash process, a flash gas, such as a nitrogen-containing gas, an oxygen-containing gas, an argon-containing gas, or a compound of the above chemical elements, can flow into the reaction chamber to remove the unwanted residuals on the semiconductor substrate 100. For example, a carbon monoxide (CO) gas can flow into the reaction chamber to remove polymers formed in the above etching processes.

As the FIG. 5 shows, the cap layer 110, the BARC layer 112 and the patterned photoresist 114 can still cover parts of the underlying patterned metal layer 108a after the process of etching the metal layer 108. It deserves to be mentioned that the cap layer 110, the BARC layer 112 and/or the patterned photoresist 114 can be consumed during the etching process in other embodiment, so there can be no patterned photoresist 114 above the patterned metal layer 108a.

Next, as shown in FIG. 6, another etching process is carried out on the dielectric layer 104 in the same reaction chamber. The patterned photoresist 114, the remaining BARC layer 112, the remaining cap layer 110, and the patterned metal layer 108a are utilized as an etching mask for etching the dielectric layer 104, so as to form a trench 116 in the dielectric layer 104. The process of etching the dielectric layer 104 can be a plasma etching process, and can include a hexafluorobutadiene (C₄F₆) gas, a nitrogen (N₂) gas, a CF₄ gas and an Ar gas. The flowing rate of the C₄F₆ gas can be about 10 sccm, the flowing rate of the N₂ gas can be about 70 sccm, the flowing rate of the CF₄ gas can be about 150 sccm, and the flowing rate of the Ar gas can be about 200 sccm. In practice, the process of etching the dielectric layer 104 can include a plurality of etching steps. For instance, the process of etching the dielectric layer 104 can include a first main etching procedure, an ashing procedure and a second main etching procedure.

It should be noted that the process of etching the metal layer 108, the flash process and the process of etching the dielectric layer 104 are preferably performed in the same reaction chamber continuously and in-situ by simply changing the process recipes, such as the process gases, the process frequencies, or the process pressures. In addition, the process of etching the metal layer 108, the flash process and the process of etching the dielectric layer 104 are preferably performed without a vent (without break the vacuum). Since it is unnecessary for the semiconductor substrate 100 to transfer between different chambers of an equipment for undergoing the process of etching the metal layer 108 and the process of etching the dielectric layer 104, the cycle time of the processes can be effectively reduced, and the throughput can therefore be improved. Furthermore, because the process of etching the metal layer 108 and the process of etching the dielectric layer 104 are performed without a vent, the patterned metal layer 108a can be protected from the external pollutions, such as water, chlorine gas or other chemicals. Thus, the pollutions do not damage the profile and shape of the patterned metal layer 108a, and do not affect the process of etching the dielectric layer 104. As shown in FIG. 7, the reaction chamber 118 provided in this embodiment can include a housing 120, a high-frequency-providing device 122, a two-frequency-providing device 124, at least a gas-flowing pipe 126, and a protecting layer 128. The position of the high-frequency-providing device 122, the position of the two-frequency-providing device 124, the position of the gas-flowing pipe 126, and the position of the protecting layer 128 can be adjusted as required, and are not limited to FIG. 7. The housing 120 is applied for performing various reactions on the semiconductor substrate 100, and can isolate the semiconductor substrate 100 from the pollution existing in surrounding environments. The gas-flowing pipe 126 allows the process gases flowing into the reaction chamber 118 or flowing out. The high-frequency-providing device 122 can provide a high frequency at about 30 MHz, 60 MHz or 160 MHz, so to control the plasma density in a range about 10¹⁰ to 10¹¹ per cubic centimeter in the reaction chamber 118. The two-frequency-providing device 124 can optionally provide two different frequencies: 2 MHz and 13.56 MHz. The protecting layer 128 can be disposed on any part of the reaction chamber 118, which may contact the reaction. For instance, the protecting layer 128 can be disposed on an inner surface of the reaction chamber 118 and/or an inner surface of the gas-flowing pipe 126. The protecting layer 128 can prevent the reaction chamber 118 from being etched by the reaction of the performed process, and can include any material, which are hard etched in the etching processes, such as siliconcarbon or yttrium oxide compounds. For example, SiC or Y₂O₃ can be included in the protecting layer 128. The etching selectivity ratio of the etching target layer to the protecting layer 128 of the etching process is preferably large, so it is more difficult to etch the protecting layer 128.

In other embodiments, the method of etching a dielectric layer can be applied to processes of forming a dual damascene structure. Please refer to FIG. 8 and FIG. 10. FIGS. 8-10 are schematic diagrams illustrating a method of forming an opening of a dual damascene structure in accordance with another preferred embodiment of the present invention. As shown in FIG. 8, after the patterned metal layer 108a is formed by the processes shown in FIG.3 through FIG. 5, the BARC layer 112 and the patterned photoresist 114 disposed above the patterned metal layer 108a can be removed. Afterward, another BARC layer 140 and another patterned photoresist 142 can be formed over the semiconductor substrate 100 in turn. The patterned photoresist 142 has an opening used to define a via pattern of a damascene structure.

As shown in FIG. 9, another etching process is performed on the dielectric layer 104 by utilizing the patterned photoresist 142 as an etching mask, so parts of the BARC layer 140, parts of the cap layer 106, and parts of the dielectric layer 104, which are not covered by the patterned photoresist 142, are etched through the opening, and a partial via feature is formed in an upper portion of the dielectric layer 104. Thereafter, the remaining patterned photoresist 142, the BARC layer 140 and the cap layer 110 can be stripped off by an oxygen plasma etching process.

Next, as shown in FIG. 10, an etching process is performed to etch the dielectric layer 104 and the liner layer 103 by utilizing the patterned metal layer 108a as an etching hard mask, until the base layer 102 is exposed. Therefore, a trench 116 and a via hole 130 are formed in the dielectric layer 104, and the trench 116 and the via hole 130 form the opening of a dual damascene structure. It should be noted that the process of etching the metal layer 108 and the process of etching the dielectric layer 104 are performed in the same reaction chamber, such as the reaction chamber 118 shown in FIG. 7. It should also be noted that the liner layer 103 can be etched together with the dielectric layer 104 in one etching process to expose parts of the base layer 102 in this embodiment. In other embodiments, the liner layer 103 can function as an etching stop layer in the process of etching the dielectric layer 104. In other words, the dielectric layer 104 is etched by utilizing the patterned metal layer 108a as an etching hard mask, until the liner layer 103 is exposed, and the exposed part of the liner layer 103 is next removed to expose the base layer 102.

The method of etching the dielectric layer in the present invention can be applied to various processes of forming openings, such as processes of forming a via hole, processes of forming a contact hole, a via-first process of forming an opening of a dual damascene structure, a trench-first process of forming an opening of a dual damascene structure, a partial-via-first process of forming an opening of a dual damascene structure, or a self-aligned process of forming an opening of a dual damascene structure. Please refer to FIG. 11 through FIG. 14. FIGS. 11-14 are schematic diagrams illustrating a method of etching a dielectric layer in accordance with another preferred embodiment of the present invention, where a contact hole is formed in this preferred embodiment. As shown in FIG. 11, a semiconductor substrate 200 is first provided. The semiconductor substrate 200 includes a base layer 202, a liner layer 203 disposed on the base layer 202, a dielectric layer 204 disposed on the liner layer 203, and a metal layer 208 disposed on the dielectric layer 204. Subsequently, a BARC layer 112 and a patterned photoresist 214 are formed over the metal layer 208 in turn.

The opening of the patterned photoresist 214 can include a predetermined pattern for the subsequent process, such as a contact hole pattern, and can expose parts of the BARC layer 112. The base layer 202 can include a silicon-based substrate and various devices disposed on the silicon-based substrate. The detail structure of the base layer 202 can be adjusted according to the product design, so is not shown in the drawings. The metal layer 208 is preferably a TiN layer or a TaN layer. The dielectric layer 204 can include an inter-level dielectric layer (ILD), and can be made from low-k materials or ULK materials. The liner layer 203 can include stressed SiN.

As shown in FIG. 12, an etching process is next performed to etch parts of the BARC layer 112 by utilizing the patterned photoresist 214 as an etching mask. In this embodiment, the process of etching the BARC layer 112 can include a CHF₃ gas and a CF₄ gas. The flowing rate of the CHF₃ gas can be about 50 sccm, and the flowing rate of the CF₄ gas can be about 150 sccm. Furthermore, as shown in FIG. 13, another etching process is carried out to etch the metal layer 208 by utilizing the patterned photoresist 214 as an etching mask. This etching process can turn the metal layer 208 into a patterned metal layer 208a. The process of etching the metal layer 208 can be a plasma etching process, and usually includes an effective and potent corrosive as an etching gas, such as SF₆ gas or Cl₂ gas. For instance, the process of etching the metal layer 208 can include an Ar gas and a Cl₂ gas. The flowing rate of the Ar gas can be about 200 sccm, and the flowing rate of the Cl₂ gas can be about 75 sccm.

As the FIG. 13 shows, the BARC layer 112 and the patterned photoresist 214 can still cover parts of the underlying patterned metal layer 208a after the process of etching the metal layer 208. It deserves to be mentioned that the BARC layer 112 and/or the patterned photoresist 214 can be consumed during the etching process in other embodiment, so there can be no patterned photoresist 214 above the patterned metal layer 208a.

Next, as shown in FIG. 14, another etching process is carried out on the dielectric layer 204 and the liner layer 203 in the same reaction chamber, where the liner layer 203 can function as a contact etch stop layer (CESL). The dielectric layer 204 is etched by utilizing the patterned photoresist 214, the remaining BARC layer 112, and the patterned metal layer 208a as an etching hard mask, until the liner layer 203 is exposed, and the exposed part of the liner layer 203 is next removed to expose the base layer 202. Therefore, a contact hole 216 is formed in the dielectric layer 204. The process of etching the dielectric layer 204 can be a plasma etching process, and can include a C₄F₆ gas, a carbon monoxide (CO) gas, a CH₂F₂ gas and an 02 gas. The flowing rate of the C₄F₆ gas can be about 20 sccm, the flowing rate of the CO gas can be about 300 sccm, the flowing rate of the CH₂F₂ gas can be about 40 sccm, and the flowing rate of the O₂ gas can be about 27 sccm. In practice, the process of etching the dielectric layer 204 can include a plurality of etching steps. For instance, the process of etching the dielectric layer 204 can include a main etching procedure, an ashing procedure and an over-etching procedure. It should be noted that the process of etching the metal layer 208 and the process of etching the dielectric layer 204 are performed in the same reaction chamber, such as the reaction chamber 118 shown in FIG. 7. The different processes can be performed in the same reaction chamber by changing the process recipes, such as providing different process gases, providing different process frequencies, providing different process pressures. As a result, the cycle time can therefore be improved in the present invention, and the substrate is protected from the pollution existing in surrounding environments.

It should also be noted that the liner layer 203 can function as the CESL in the process of etching the dielectric layer 204, and is further removed to expose base layer 202 in this embodiment. In other embodiments, the liner layer 203 can be etched together with the dielectric layer 204 by utilizing the patterned photoresist 214, the remaining BARC layer 112, and the patterned metal layer 208a as an etching hard mask, until the base layer 202 is exposed to form the contact hole 216 in the dielectric layer 204.

Thereafter, the patterned metal layer 208a, the BARC layer 112 and the patterned photoresist 214 can be removed from the dielectric layer 204. Next, a conductive structure is formed in the contact hole 216 to complete the fabrication of a contact plug (not shown in the drawings).

In the above-mentioned embodiments, a metal layer can be first etched to form a patterned metal layer, and thereafter a dielectric layer is etched in the same reaction chamber by using the patterned metal layer as an etching mask. However, the present invention should not be limited to these embodiments. It is one aspect of this invention that the process of etching a metal layer and the process of etching a dielectric layer can be performed on a semiconductor substrate in the same reaction chamber. Accordingly, the process of etching a dielectric layer might be performed immediately after the process of etching a metal layer in the same reaction chamber in-situ; the process of etching a metal layer might be performed immediately after the process of etching a dielectric layer in the same reaction chamber in-situ; or other processes, such as a cleaning process or a degas process, can be performed between the process of etching a metal layer and the process of etching a dielectric layer. In some embodiments, the semiconductor substrate can be protected in the same reaction chamber from the outside pollutions during the period between the metal-etching process and the dielectric-etching process without a vent (without breaking the vacuum). In other embodiments, the reaction chamber can be vented (breaking the vacuum), or the semiconductor substrate can be transferred outward from said reaction chamber as required.

In sum, the process of etching a dielectric layer and the process of etching a metal layer can be performed in the same reaction chamber without a vent in this invention to protect the semiconductor structure from external pollutions. Thus, the structures of the subsequently formed metal lines or conductive plugs can be improved. The metal layer is usually more anticorrosive than the photoresist in the process of etching dielectric layer. Thus, the patterned metal layer applied as an etching mask can be thinner than the patterned photoresist, and the aspect ratio of the formed opening can therefore be smaller. Since the metal-etching process and the dielectric-etching process are not performed in different reaction chambers respectively, the cycle time can therefore be improved in the present invention, and an efficient process is provided.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims

1. A method of etching a dielectric layer, comprising:

providing a substrate, the substrate comprising a base layer, a dielectric layer and a metal layer, the dielectric layer and the metal layer being disposed above the base layer;

performing a first etching process on the metal layer to turn the metal layer into a patterned metal layer; and

performing a second etching process on the dielectric layer to form at least one opening in the dielectric layer, wherein the first etching process and the second etching process are performed in a same reaction chamber.

2. The method of claim 1, wherein the metal layer comprises titanium nitride (TiN).

3. The method of claim 1, wherein the second etching process utilizes the patterned metal layer as an etching mask to etch the dielectric layer.

4. The method of claim 3, wherein the opening of the dielectric layer comprises a trench, a via hole or an opening of a dual damascene structure.

5. The method of claim 4, further comprising a step of forming a patterned photoresist on the metal layer, wherein the first etching process utilizes the patterned photoresist as an etching mask to etch the metal layer.

6. The method of claim 5, further comprising a step of forming a first cap layer on the metal layer before forming the patterned photoresist.

7. The method of claim 6, further comprising a step of forming a bottom anti-reflection coating layer (BARC layer) on the first cap layer before forming the patterned photoresist, wherein the patterned photoresist exposes parts of the BARC layer.

8. The method of claim 7, further comprising a step of etching the BARC layer and the first cap layer by utilizing the patterned photoresist as an etching mask after forming the patterned photoresist.

9. The method of claim 5, wherein the substrate further comprises a second cap layer disposed between the dielectric layer and the metal layer.

10. The method of claim 9, wherein the second etching process utilizes the patterned metal layer as an etching mask to etch the first cap layer and the dielectric layer.

11. The method of claim 1, wherein the opening of the dielectric layer comprises a contact hole.

12. The method of claim 11, further comprising a step of forming a patterned photoresist on the metal layer, wherein the first etching process utilizes the patterned photoresist as an etching mask to etch the metal layer.

13. The method of claim 12, further comprising a step of forming a bottom anti-reflection coating layer (BARC layer) on the metal layer before forming the patterned photoresist, wherein the patterned photoresist exposes parts of the BARC layer.

14. The method of claim 13, further comprising a step of etching the BARC layer by utilizing the patterned photoresist as an etching mask after forming the patterned photoresist.

15. The method of claim 11, wherein the dielectric layer comprises an inter-level dielectric layer.

16. The method of claim 1, wherein the first etching process and the second etching process comprises a plasma etching process.

17. The method of claim 1, wherein the first etching process comprises sulfur hexafluoride gas or chlorine gas.

18. The method of claim 1, wherein the reaction chamber comprises a protecting layer disposed on an inner surface of the reaction chamber.

19. The method of claim 18, wherein the protecting layer comprises silicon carbide or yttrium oxide compounds.

20. The method of claim 1, wherein the substrate is kept in the reaction chamber during a period between the first etching process and the second etching process.