Mask Resist Contains Inorganic Material Patents (Class 216/51)
  • Patent number: 11316108
    Abstract: A method for manufacturing a mask includes providing a mask mother substrate including a first portion and a plurality of second portions adjacent to the first portion, forming a reflecting plate on the mask mother substrate, forming a photoresist layer on the reflecting plate, removing a third portion of the photoresist layer that overlaps the plurality of second portions using an auxiliary mask, removing a fourth portion of the reflecting plate that overlaps the plurality of second portions, and removing the plurality of second portions of the mask mother substrate using a laser.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: April 26, 2022
    Inventors: Inkyung Yoo, SangJin Park, Donghyun Yang, Sungbae Ju
  • Patent number: 11233082
    Abstract: A method for forming a light sensing device is provided. The method includes forming a light sensing region in a semiconductor substrate and forming a light shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the light shielding layer and partially removing the light shielding layer and the dielectric layer to form a light shielding element and a dielectric element. A top width of the light shielding element is greater than a bottom width of the dielectric element. The light shielding element and the dielectric element surround a recess, and the recess is aligned with the light sensing region. The method further includes forming a filter element in the recess.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Yi-Hsing Chu, Yin-Chieh Huang, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 11011385
    Abstract: A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
  • Patent number: 11004692
    Abstract: A method for shallow etching a substrate surface forms a shallow modified substrate layer overlying unmodified substrate using an accelerated neutral beam and etches the modified layer, stopping at the unmodified substrate beneath, producing controlled shallow etched substrate surfaces.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 11, 2021
    Assignee: Exogenesis Corporation
    Inventors: Sean R. Kirkpatrick, Richard C. Svrluga
  • Patent number: 10816705
    Abstract: A batch processing method for fabrication of diffractive optics is disclosed, having applicability to high resolution ultra-high aspect ratio Fresnel Zone Plates for focusing of X-rays or gamma-rays having energies up to hundreds of keV. An array of precursor forms comprising columns is etched into a planar substrate. After sidewall smoothing, a nanolaminate, comprising a sequence of alternating layers of different complex refractive index, is deposited on the sidewall of each column by atomic layer deposition (ALD), to define a specified diffractive line pattern around each column, to form a binary or higher order diffractive optic. After front surface planarization and thinning of the substrate to expose first and second surfaces of the diffractive line pattern of each diffractive optic, the height h in the propagation direction provides a designed absorption difference and/or phase shift difference between adjacent diffractive lines.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 27, 2020
    Assignee: ALCORIX CO.
    Inventor: Nicolaie A. Moldovan
  • Patent number: 10787698
    Abstract: Provided is a surface having metal regions and an interstitial region having a composition that differs from the metal regions, wherein a continuous gel layer coats the surface across the metal regions and the interstitial regions. Nucleic acids or other analytes can be attached to the continuous gel layer such that a greater amount is attached over the metal regions than over the interstitial region. Also provided are methods for making such surfaces. Methods are also provided for making an array of nucleic acids or other analytes using such surfaces.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 29, 2020
    Assignee: ILLUMINA, INC.
    Inventors: Shengrong Lin, Yir-Shyuan Wu, Kevin Gunderson, John A. Moon
  • Patent number: 10679853
    Abstract: A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frank Robert Libsch, Ghavam G. Shahidi, Ko-Tao Lee, Stephen M. Rossnagel
  • Patent number: 10672589
    Abstract: A plasma processing apparatus includes: a processing container; an electrode that places a workpiece thereon; a plasma generation source that supplies plasma into the processing container; a bias power supply that supplies a bias power to the electrode; an edge ring disposed at a periphery of the workpiece; a DC power supply that supplies a DC voltage to the edge ring; a controller that executes a first control procedure in which the DC voltage periodically repeats a first state having a first voltage value and a second state having a second voltage value, the first voltage value is supplied in a partial time period within each period of a potential of the electrode, and the second voltage value is supplied such that the first and second states are continuous.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Chishio Koshimizu, Shin Hirotsu
  • Patent number: 10522796
    Abstract: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 31, 2019
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Julien Ladroue, Mohamed Boufnichel
  • Patent number: 10497580
    Abstract: A plasma etching method according to the present disclosure includes a first etching step of performing plasma etching of the silicon nitride film on the workpiece by supplying a processing gas containing a gas of a compound represented by a composition formula C3H2BrF3 including a 2-bromo-3,3,3-trifluoropropene gas, a (Z)-1-bromo-3,3,3-trifluoropropene gas, an (E)-1-bromo-3,3,3-trifluoropropene gas, and/or a 3-bromo-2,3,3-trifluoropropene gas into the processing chamber, such that a ratio CF2/F obtained by emission spectrometry of the gas of the compound represented by the composition formula C3H2BrF3 is at least 0.33 within the processing chamber.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: December 3, 2019
    Assignee: ZEON CORPORATION
    Inventor: Takaaki Sakurai
  • Patent number: 10435808
    Abstract: An etching apparatus having a liquid bath storing an etching liquid, a substrate installation part capable of supporting the semiconductor substrate in vertical placement at a position at which a treatment surface of the semiconductor substrate is immersed in the etching liquid, a sample electrode provided at the substrate installation part and electrically connected to the semiconductor substrate, a counter electrode disposed at a position at which the counter electrode is immersed in the etching liquid in the liquid bath, a light source irradiating the treatment surface of the semiconductor substrate with light, and an irradiation window provided between the treatment surface of the semiconductor substrate and the light source and at a position separated from the semiconductor substrate in a horizontal direction.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Eiko Ishii, Yumi Saito, Teruhisa Akashi, Kenji Nakashima
  • Patent number: 10366902
    Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 30, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Vinayak Rastogi
  • Patent number: 10357768
    Abstract: A method for fabricating an MEMS device includes providing a first substrate with a central region and a peripheral region, and forming a plurality of first openings in the peripheral region and a plurality of third openings in the central region by etching the first substrate from a front side. The depth of the first openings is larger than the depth of the third openings. The method further includes forming a photosensitive layer on the surfaces of the first openings and the third openings, bonding a second substrate to the front side of the first substrate, and forming a trench by etching the first substrate from a back side using a patterned mask layer as an etch mask. The trench has a concave bottom surface and exposes a portion of the photosensitive layer formed on the bottom surfaces of the first openings and the third openings.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Chao Zheng
  • Patent number: 10103196
    Abstract: Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the magnetic cell core comprises forming a first magnetic region over the substrate, forming a tunnel barrier material over the first magnetic region, and forming a second magnetic region over the tunnel barrier material. A temperature of at least one of the substrate or a wafer stage underlying the substrate is maintained at a temperature below about 0° C. and the magnetic cell core material is exposed to at least a first beam comprising one of an ion beam or a neutral beam comprising ions or elements of at least one noble gas to remove portions of the magnetic cell core material. Related magnetic memory cells and methods of forming an array of memory cells are also disclosed.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 16, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ken Tokashiki
  • Patent number: 10043711
    Abstract: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped III-V material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Kevin K. Chan, John Rozen, Jeng-Bang Yau, Yu Zhu
  • Patent number: 9818638
    Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: November 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Chung-Chi Ko, Shing-Chyang Pan
  • Patent number: 9817927
    Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guo Xiang Ning, Yuping Ren, David Power, Lalit Shokeen, Chin Teong Lim, Paul W. Ackmann, Xiang Hu
  • Patent number: 9704746
    Abstract: A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Jinping Liu, Archana Subramaniyan
  • Patent number: 9466485
    Abstract: A conductor pattern forming method includes forming, on a conductor film, a laminated film including a first layer thinner than the conductor film, a second layer thicker than the first layer, and a third layer thinner than the second layer, which layers are laminated in order from the conductor film side. A first mask is formed from the third layer by dry-etching the third layer using a photoresist mask formed on the laminated film. A second mask is formed from the second layer by dry-etching the second layer using the first mask. The conductor film is exposed by dry-etching the first layer using the second mask. A conductor pattern is formed from the conductor film by dry-etching the conductor film using the second mask.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keita Torii
  • Patent number: 9302933
    Abstract: A method of making an article having a textured glass surface, including, for example: attaching microencapsulated particles to a portion of a glass surface of the article; and contacting the glass surface having the attached microencapsulated particles with an etchant to form the textured surface. A glass article prepared by the method including: at least one textured surface having excellent haze, distinctness-of-image, surface roughness, and uniformity properties, as defined herein. A display system that incorporates the glass article, as defined herein, is also disclosed.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: April 5, 2016
    Assignee: Corning Incorporated
    Inventors: Timothy Edward Myers, Vasudha Ravichandram, Christine Coulter Wolcott
  • Patent number: 9070800
    Abstract: The present invention relates to a solar cell. The solar cell includes a substrate of a first conductive type, the substrate having a textured surface on which a plurality of projected portions are formed, and surfaces of the projected portions having at least one of a plurality of particles attached thereto and a plurality of depressions formed thereon; an emitter layer of a second conductive type opposite the first conductive type, the emitter layer being positioned in the substrate so that the emitter layer has the textured surface; an anti-reflection layer positioned on the emitter layer which has the textured surface and including at least one layer; a plurality of first electrodes electrically connected to the emitter layer; and at least one second electrode electrically connected to the substrate.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 30, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Jinsung Kim, Chulchae Choi, Changseo Park, Jaewon Chang, Hyungseok Kim, Youngho Choe, Philwon Yoon
  • Patent number: 9034198
    Abstract: A plasma etching method using a plasma etching apparatus including a lower electrode and an upper electrode is provided. The plasma etching method includes a first etching step of performing plasma etching using a first process gas and a second etching step of performing the plasma etching using a second process gas. The adhesion of a radical of the second process gas to an object of processing is less than the adhesion of a radical of the first process gas to the object of processing. While alternately repeating a first condition of turning on high-frequency electric power for plasma generation and a second condition of turning off the high-frequency electric power, the second etching step applies a negative direct-current voltage to the upper electrode so that the absolute value of the applied voltage is greater in a period of the second condition than in a period of the first condition.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Fumio Yamazaki, Hiromi Mochizuki
  • Patent number: 9034197
    Abstract: The disclosure relates generally to a method for fabricating a patterned medium. The method includes providing a substrate with an exterior layer under a lithographically patterned surface layer, the lithographically patterned surface layer comprising a first pattern in a first region and a second pattern in a second region, applying a first masking material over the first region, transferring the second pattern into the exterior layer in the second region, forming self-assembled block copolymer structures over the lithographically patterned surface layer, the self-assembled block copolymer structures aligning with the first pattern in the first region, applying a second masking material over the second region, transferring the polymer block pattern into the exterior layer in the first region, and etching the substrate according to the second pattern transferred to the exterior layer in the second region and the polymer block pattern transferred to the exterior layer in the first region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 19, 2015
    Assignee: HGST NETHERLANDS B.V.
    Inventors: Jeffrey S. Lille, Kurt A. Rubin, Ricardo Ruiz, Lei Wan
  • Publication number: 20150131408
    Abstract: Provided are a laser-induced ultrasound generator and a method of manufacturing the laser-induced ultrasound generator. The laser-induced ultrasound generator includes: a substrate including a plurality of nanostructures provided on a first surface of the substrate; and a thermoelastic layer provided on the first surface of the substrate, the thermoelastic layer being configured to generate an ultrasound by absorbing a laser beam incident onto a second surface of the substrate, the second surface facing the first surface. The nanostructures may be cylinder-shaped nano-pillars.
    Type: Application
    Filed: June 5, 2014
    Publication date: May 14, 2015
    Applicants: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-chan KANG, Jong-seok KIM, Chang-jung KIM, Seung-bum YANG, Young-jae OH, Yong-seop YOON, Ki-hun JEONG
  • Patent number: 9023219
    Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin Deshpande, Sanjeev Aggarwal, Kerry Nagel
  • Publication number: 20150118625
    Abstract: Provided herein is a method, including a) transferring an initial pattern of an initial template to a substrate; b) performing block copolymer self-assembly over the substrate with a density multiplication factor k; c) creating a subsequent pattern in a subsequent template with the density multiplication factor k; and d) repeating steps a)-c) with the subsequent template as the initial template until a design specification for the subsequent pattern with respect to pattern density and pattern resolution is met.
    Type: Application
    Filed: January 2, 2015
    Publication date: April 30, 2015
    Inventors: XiaoMin Yang, Zhaoning Yu, Kim Yang Lee, Michael Feldbaum, Yautzong Hsu, Wei Hu, Shuaigang Xiao, Henry Yang, HongYing Wang, Rene Johannes Marinus van de Veerdonk, David Kuo
  • Patent number: 8999181
    Abstract: In a method for manufacturing a ridge-type waveguide, a substrate is provided. An etching resistance stripe is coated on the substrate. The substrate with the etching resistance stripe is subjected to a wet etching process to form a ridge under the etching resistance stripe. The etching resistance stripe is removed. A titanium stripe is then coated onto the ridge and diffused into the ridge to form a waveguide in the ridge by a high temperature diffusing process.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Hsin-Shun Huang
  • Patent number: 8980418
    Abstract: A plasma etch resist material modified by an inorganic protective component via sequential infiltration synthesis (SIS) and methods of preparing the modified resist material. The modified resist material is characterized by an improved resistance to a plasma etching or related process relative to the unmodified resist material, thereby allowing formation of patterned features into a substrate material, which may be high-aspect ratio features. The SIS process forms the protective component within the bulk resist material through a plurality of alternating exposures to gas phase precursors which infiltrate the resist material. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: March 17, 2015
    Assignee: UChicago Argonne, LLC
    Inventors: Seth B. Darling, Jeffrey W. Elam, Yu-Chih Tseng, Qing Peng
  • Patent number: 8974682
    Abstract: A self-assembled pattern forming method in an embodiment includes: forming a guide pattern on a substrate; forming a layer of a first polymer; filling a first block copolymer; and phase-separating the first block copolymer. The guide pattern includes a first recessed part having a depth T and a diameter D smaller than the depth T, and a second recessed part having a width larger than double of the diameter D. The first block copolymer has the first polymer and a second polymer which are substantially the same in volume fraction. By phase-separating the first block copolymer, a cylinder structure and a lamellar structure are obtained.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hieda, Yoshiyuki Kamata, Naoko Kihara, Akira Kikitsu, Ryosuke Yamamoto
  • Publication number: 20150065389
    Abstract: The present invention is drawn to the generation of micropatterns of biomolecules and cells on standard laboratory materials through selective ablation of a physisorbed biomolecule with oxygen plasma. In certain embodiments, oxygen plasma is able to ablate selectively physisorbed layers of biomolecules (e.g., type-I collagen, fibronectin, laminin, and Matrigel) along complex non-linear paths which are difficult or impossible to pattern using alternative methods. In addition, certain embodiments of the present invention relate to the micropatterning of multiple cell types on curved surfaces, multiwell plates, and flat bottom flasks. The invention also features kits for use with the subject methods.
    Type: Application
    Filed: March 26, 2014
    Publication date: March 5, 2015
    Applicant: Massachusetts Institute of Technology
    Inventors: David T. Eddington, Sangeeta N. BHATIA
  • Patent number: 8968587
    Abstract: Methods of preparing graphene nano ribbons may include forming a graphene sheet on at least one surface of a substrate, forming a plasma mask having a nano pattern on the graphene sheet, and forming a nano pattern on the graphene sheet by plasma treating a stack structure on which the plasma mask is formed.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-jin Shin, Jae-young Choi, Young-hee Lee, Gang-hee Han
  • Publication number: 20150034592
    Abstract: A method or process is disclosed for etching deep, high-aspect ratio features into silicon dioxide material layers and substrates, including glass, fused silica, quartz, or similar materials, using a plasma etch technology. The method has application in the fabrication and manufacturing of MEMS, microelectronic, micro-mechanical, photonic and nanotechnology devices in which silicon dioxide material layers or substrates are used and must be patterned and etched. Devices that benefit from the method described in this invention include the fabrication of MEMS gyroscopes, resonators, oscillators, microbalances, accelerometers, for example. The etch method or process allows etch depths ranging from below 10 microns to over 1 millimeter and aspect ratios from less than 1 to 1 to over 10 to 1 with etched feature sidewalls having vertical or near vertical angles. Additionally, the disclosed method provides requirements of the etched substrates to reduce or eliminate undesired effects of an etch.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: Corporation For National Research Initiatives
    Inventors: Michael A. Huff, Michael Pedersen
  • Publication number: 20150021293
    Abstract: A method for providing a nanopattern of periodically ordered metal oxide nanostructures on a substrate is described. The method comprises the steps of providing a microphase separated block copolymer as a thin film on a substrate, the block copolymer comprising a first polymer having an affinity for a cations of the metal and a second polymer having a lower affinity for the cations than the first polymer, and selectively incorporating a salt of the metal cation into the first polymer of the block copolymer by means of a solvation process prior to or after formation of the microphase separated block copolymer. The block copolymer film is then treated to oxidise the metal ion salt and remove the polymers leaving a nanopattern of metal oxide nanostructures on the substrate.
    Type: Application
    Filed: November 16, 2012
    Publication date: January 22, 2015
    Inventors: Michael Morris, Dipu Borah, Tandra Ghoshal, Parvaneh Mokarian
  • Patent number: 8932953
    Abstract: A composition for forming a silicon-containing resist underlayer film that contains: a component (A) including at least one or more compounds selected from the group consisting of a polymer having repeating units shown by the following general formulae (1-1a) and (1-1b) and being capable of generating a phenolic hydroxyl group, a hydrolysate of the polymer, and a hydrolysis-condensate of the polymer, and a component (B) which is a silicon-containing compound obtained by hydrolysis-condensation of a mixture containing, at least, one or more hydrolysable silicon compounds represented by the following general formula (2) and one or more hydrolysable silicon compounds represented by the following general formula (3).
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Toshiharu Yano, Yoshinori Taneda
  • Publication number: 20140353277
    Abstract: The present invention discloses a method for fabricating a default free silicon mold insert. The method includes providing a silicon mold insert substrate, producing a photoresist pattern, coating a metal film, removing the photoresist pattern, performing heating and annealing, performing dry etching, and removing the metal balls so as to fabricate the default free silicon mold insert. The default free silicon mold insert produced by the method of the present invention can be applied to the nonoimprint process in manufacturing epitaxy wafers to microscopicly provide uniform distances of patterns on the silicon mold insert, and macroscopicly eliminate the grid lines on the epitaxy wafers, and enormously raise the throughput of epitaxy wafer productions. With the ease of application, cheap and fully reproducible nature of the default free silicon mold insert, nanoimprint technology can really replace the stepper machines used nowadays for producing default free nanoimprint mold insert.
    Type: Application
    Filed: July 16, 2013
    Publication date: December 4, 2014
    Inventors: Chong-Ming LEE, Chung-Hua LEE
  • Publication number: 20140346142
    Abstract: A method for making a chemical contrast pattern uses directed self-assembly of block copolymers (BCPs) and sequential infiltration synthesis (SIS) of an inorganic material. For an example with poly(styrene-block-methyl methacrylate) (PS-b-PMMA) as the BCP and alumina as the inorganic material, the PS and PMMA self-assemble on a suitable substrate. The PMMA is removed and the PS is oxidized. A surface modification polymer (SMP) is deposited on the oxidized PS and the exposed substrate and the SMP not bound to the substrate is removed. The structure is placed in an atomic layer deposition chamber. Alumina precursors reactive with the oxidized PS are introduced and infuse by SIS into the oxidized PS, thereby forming on the substrate a chemical contrast pattern of SMP and alumina. The resulting chemical contrast pattern can be used for lithographic masks, for example to etch the underlying substrate to make an imprint template.
    Type: Application
    Filed: May 25, 2013
    Publication date: November 27, 2014
    Inventors: Yves-Andre Chapuis, Ricardo Ruiz, Lei Wan
  • Patent number: 8889562
    Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ying Zhang
  • Publication number: 20140332776
    Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
    Type: Application
    Filed: March 21, 2014
    Publication date: November 13, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Su Yeon YUN, Dong Jin SON
  • Publication number: 20140335691
    Abstract: A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
    Type: Application
    Filed: September 5, 2013
    Publication date: November 13, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventor: Dong-Jin SON
  • Patent number: 8883645
    Abstract: Methods for fabrication of nanopillar field effect transistors are described. These transistors can have high height-to-width aspect ratios and be CMOS compatible. Silicon nitride may be used as a masking material. These transistors have a variety of applications, for example they can be used for molecular sensing if the nanopillar has a functionalized layer contacted to the gate electrode. The functional layer can bind molecules, causing an electrical signal in the transistor.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 11, 2014
    Assignee: California Institute of Technology
    Inventors: Chieh-Feng Chang, Aditya Rajagopal, Axel Scherer
  • Patent number: 8871106
    Abstract: This present invention provides a masking method for locally treating surface of a workpiece by masking the workpiece. The workpiece has a targeting treatment area and a non-targeting treatment area. The masking method includes: covering a fixture on the non-targeting treatment area of the workpiece to expose the targeting treatment area of the workpiece; by using an adsorbing force existing between the fixture and the workpiece, getting the fixture to closely contact with the non-targeting treatment area of the workpiece and to make an end edge of the fixture correspond to the edge of the targeting treatment area of the workpiece, wherein the adsorbing force is a vacuum adsorbing force or a static electric adsorbing force. Thereby the surface treatment only effects in an area within the range of the targeting treatment area of the workpiece so as to reduce the treatment defect.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Apone Technology Ltd.
    Inventor: Wei-Lin Liu
  • Publication number: 20140299576
    Abstract: A plasma processing method includes an etching process of etching an insulating film formed on a processing target object in a chamber by plasma of a first fluorine-containing gas with a TiN film having a preset pattern as a mask; a modifying process of modifying, between a carbon-containing film and a Ti-containing film adhering to a component within the chamber, a surface of the Ti-containing film by plasma of an oxygen-containing gas while removing the carbon-containing film by the plasma of the oxygen-containing gas, after the etching process; a first removing process of removing a TiO film, which is obtained by modifying the surface of the Ti-containing film, by plasma of a second fluorine-containing gas; and a second removing process of removing a residual film of the Ti-containing film, which is exposed by removing the TiO film, from the component within the chamber by plasma of a chlorine-containing gas.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 9, 2014
    Applicant: Tokyo Electron Limited
    Inventor: Shunichi MIKAMI
  • Publication number: 20140291288
    Abstract: Provided is a method of etching a transition metal-containing film using a substrate processing apparatus. The substrate processing apparatus includes: a processing container configured to define a processing chamber and a plasma generation chamber; and a shielding unit provided between the processing chamber and the plasma generation chamber and formed with a plurality of openings to communicate the processing chamber and the plasma generation chamber with each other. The shielding unit has a shielding property against ultraviolet rays. The method includes: supplying neutral particles of oxygen atoms to the processing chamber in which a workpiece is accommodated by generating plasma of a first gas containing oxygen in the plasma generation chamber; supplying a second gas to complex a transition metal oxidized while supplying the neutral particles of oxygen to the processing chamber; and supplying neutral particles of rare gas atoms to the processing chamber by generating plasma of a rare gas.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Xun GU, Seiji SAMUKAWA
  • Publication number: 20140291287
    Abstract: The present invention refers to a method for selectively structuring of a polymer matrix comprising AgNW (silver nano wires) or CNTs (carbon nano tubes) or comprising mixtures of AgNW and CNTs on a flexible plastic substructure or solid glass sheet. The method also includes a suitable etching composition, which allows to proceed the method in a mass production.
    Type: Application
    Filed: September 28, 2012
    Publication date: October 2, 2014
    Applicant: MERCK PATENT GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler, Christian Matuschek
  • Patent number: 8845909
    Abstract: A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Tzu-Shih Shen
  • Publication number: 20140256158
    Abstract: According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masamitsu Itoh, Shingo Kanamitsu
  • Publication number: 20140238013
    Abstract: This disclosure provides systems, methods, and apparatus related to vanadium dioxide microactuators. In one aspect, a method includes depositing a vanadium dioxide layer on a sacrificial layer disposed on a substrate. A metal layer is deposited on the vanadium dioxide layer. The metal layer is patterned. Portions of the vanadium dioxide layer that are not covered by the metal layer are removed. At least a portion of the sacrificial layer is removed to form a cantilever-type structure including the vanadium dioxide layer and the metal layer disposed on the vanadium dioxide layer.
    Type: Application
    Filed: October 30, 2013
    Publication date: August 28, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Junqiao Wu, Kai Liu, Kevin Wang
  • Patent number: 8801944
    Abstract: A method for manufacturing a magnetic write pole of a magnetic write head that achieves improved write pole definition reduced manufacturing cost and improves ease of photoresist mask re-work. The method includes the use of a novel bi-layer hard mask beneath a photoresist mask. The bi-layer mask includes a layer of silicon dielectric, and a layer of carbon over the layer of silicon dielectric. The carbon layer acts as an anti-reflective coating layer that is unaffected by the photolithographic patterning process used to pattern the write pole and also acts as an adhesion layer for resist patterning. In the event that the photoresist patterning is not within specs and a mask re-work must be performed, the bi-layer mask can remain intact and need not be removed and re-deposited. In addition, the low cost and ease of use silicon dielectric and carbon reduce manufacturing cost and increase throughput.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 12, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Guomin Mao, Yi Zheng
  • Patent number: 8771531
    Abstract: A substrate for a liquid ejection head, including: forming a sacrifice layer on a first surface of a silicon substrate in a region in which a liquid supply port is to open, the sacrifice layer containing aluminum which is selectively etched with respect to the silicon substrate; forming an etching mask on a second surface which is a rear surface of the first surface of the silicon substrate, the etching mask having an opening corresponding to the sacrifice layer; a first etching step of etching the silicon substrate by using the etching mask as a mask and by using a first etchant containing 8 mass % or more and less than 15 mass % of tetramethylammonium hydroxide; and after the first etching step, a second etching step of removing the sacrifice layer by using a second etchant containing 15 mass % or more and 25 mass % or less of tetramethylammonium hydroxide.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 8, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenta Furusawa, Shuji Koyama, Hiroyuki Abo, Taichi Yonemoto
  • Publication number: 20140184958
    Abstract: The present invention relates to a cliché for offset printing and a method of manufacturing the same, and the cliché for offset printing according to the present invention comprises: a groove pattern, wherein a depth of at least a partial region of the groove pattern is different from a depth of a residual region. The present invention may comprise a double etching process when a cliché for offset printing is manufactured to control a bottom touch phenomenon that is a problem exhibited when a known wide line width is implemented, thus manufacturing the cliché for offset printing having various line widths and etching depths.
    Type: Application
    Filed: September 27, 2012
    Publication date: July 3, 2014
    Inventors: Ji Young Hwang, Beom Mo Koo