Composition for copper plating and associated methods

A composition for copper plating and associated methods, a method of forming a copper wiring including forming an insulation layer having a recessed portion on a substrate, and forming a copper layer on the insulation layer to fill the recessed portion by performing an electroplating process using a composition that includes an aqueous electrolyte solution containing a copper ion and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO) having a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

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Description
BACKGROUND

1. Field

Embodiments relate to a composition for copper plating and associated methods.

2. Description of the Related Art

As the integration degree of an electronic device, a semiconductor device, and/or an integrated circuit device increases, a width and/or a thickness of a line or a wiring and an intervals therebetween have become smaller. Use of a metal material having low resistance has also increased to form a fine or ultrafine wiring without a decrease in a response rate. Aluminum wiring has typically been used as a wiring of an integrated circuit device and, recently, use of a copper wiring is increasing.

Aluminum has a relatively high specific resistance, and therefore, aluminum wiring may have problems relating to signal delay in a circuit, which may be obstacles to fabricating a high-speed and/or high-performance circuit. Copper wiring has been used as a substitute of the aluminum wiring. Copper has a specific resistance about 40% lower than that of aluminum. Thus, copper may reduce or suppress signal delay problems. Copper may also have excellent resistance to electromigration. Accordingly, copper may be useful for manufacturing various conductive structures, e.g., a wiring, a contact, a plug, a thin film, etc., of a high-speed and/or high-performance semiconductor device.

SUMMARY

Embodiments are directed to a composition for copper plating and associated methods, which substantially overcome one or more of the drawbacks, limitations, and/or disadvantages of the related art.

It is a feature of an embodiment to provide a method of forming a copper wiring, which may fill a recess or a hole having a high aspect ratio with copper while reducing generation voids in the copper wiring.

It is another feature of an embodiment to provide a plating composition having an extended usable life span and greatly reduces generation of voids.

It is another feature of an embodiment to provide a plating composition having improved hole or trench filling characteristics.

It is another feature of an embodiment to provide a plating composition that produces a copper wiring with enhanced surface flatness.

At least one of the above and other features and advantages may be realized by providing a method of forming a copper wiring including forming an insulation layer having a recessed portion on a substrate, and forming a copper layer on the insulation layer to fill the recessed portion by performing an electroplating process using a composition that includes an aqueous electrolyte solution containing a copper ion and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO),

wherein in Formula 1, R1 and R3 are each independently substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, R2 and R4 are each independently hydrogen, C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, Rm and Rn are each independently a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion, in Formulae 3 and 4, R7 and R10 are each independently C1-C20 alkyl, cycloalkyl or aromatic hydrocarbon, R8, R9, R11, and R12 are each independently C1-C4 alkyl, and n is an integer of 1 to about 10, and the triblock copolymer of PEO-PPO-PEO has a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

The composition may include the disulfide compound represented by Formula 1, and the disulfide compound may be a compound represented by Formula 2,

wherein R5 and R6 are each independently methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, tert-butyl or trialkylsilyl, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion.

The composition may include the PEO-PPO-PEO triblock copolymer, and the PEO-PPO-PEO triblock copolymer may have a weight average molecular weight of about 2,500 to about 3,500 g/mol.

The composition may include the betaine compound represented by at least one of Formulae 3 and 4, and in Formulae 3 and 4, R7 and R10 may each independently be C6-C20 alkyl.

The composition may include the betaine compound represented by at least one of Formulae 3 and 4, and the betaine compound represented by at least one of Formulae 3 and 4 may include at least one of lauryl dimethyl betaine and lauramidopropyl dimethyl betaine.

The method may further include forming a diffusion barrier layer on the insulation layer having the recessed portion.

The method may further include forming a seed layer on the diffusion barrier layer, wherein the copper layer is formed on the seed layer to fill the recessed portion.

The aqueous electrolyte solution may further include a halide ion.

At least one of the above and other features and advantages may also be realized by providing a method of forming a copper wiring including forming a first insulation layer on the substrate having a conductive structure, the first insulation layer including a first opening exposing the conductive structure, forming a second insulation layer on the first insulation layer, the second insulation layer including a second opening exposing the first opening, forming a diffusion barrier layer along the first opening and the second opening, forming a seed layer on the diffusion barrier layer, forming a copper layer on the seed layer to fill the first opening and the second opening by performing an electroplating process using a composition that includes an aqueous electrolyte solution containing a copper ion and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO),

wherein in Formula 1, R1 and R3 are each independently substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, R2 and R4 are each independently hydrogen, C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, Rm and Rn are each independently a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion, in Formulae 3 and 4, R7 and R10 are each independently C1-C20 alkyl, cycloalkyl or aromatic hydrocarbon, R8, R9, R11, and R12 are each independently C1-C4 alkyl, and n is an integer of 1 to about 10, and the triblock copolymer of PEO-PPO-PEO has a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

The first opening may have a hole shape and the second opening may have a trench shape.

The conductive structure may be a portion of the substrate doped with impurities.

The conductive structure may be one of a pad or a conductive line formed on the substrate.

The composition may include the disulfide compound represented by Formula 1.

The aqueous electrolyte solution may further include a halide ion.

At least one of the above and other features and advantages may also be realized by providing a composition for copper plating including an aqueous electrolyte solution containing a copper ion; and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO),

wherein in Formula 1, R1 and R3 are each independently substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, R2 and R4 are each independently hydrogen, C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, Rm and Rn are each independently a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion, in Formulae 3 and 4, R7 and R10 are each independently C1-C20 alkyl, cycloalkyl or aromatic hydrocarbon, R9, R9, R11, and R12 are each independently C1-C4 alkyl, and n is an integer of 1 to about 10, and the triblock copolymer of PEO-PPO-PEO has a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

The composition may include the disulfide compound represented by Formula 1.

The aqueous electrolyte solution may further include a halide ion.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

FIGS. 1 through 4 illustrate cross-sectional views of stages in a method of forming a copper wiring according to an embodiment;

FIGS. 5 through 10 illustrate cross-sectional views of stages in a method of forming a copper wiring according to another embodiment;

FIGS. 11 through 13 illustrate diagrams of cross-sections of copper wirings formed using the compositions of Example 7 and Comparative Examples 2 and 3, respectively; and

FIG. 14 illustrates Formulae 1 through 4.

 DETAILED DESCRIPTION

Korean Patent Application No. 10-2008-0097600, filed on Oct. 6, 2008, in the Korean Intellectual Property Office, and entitled: “Compositions for Copper Plating and Methods of Forming a Copper Wiring,” is incorporated by reference herein in its entirety.

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it may be directly connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would be oriented “above” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belongs. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Compositions for Copper Plating

A composition for copper plating may include an aqueous electrolyte solution containing a copper ion and a disulfide compound acting as an accelerator. The disulfide compound may function as a catalyst in a reduction reaction of a copper ion to thereby raise a copper deposition rate. The disulfide compound may have a chemical structure represented by Formula 1:

In Formula 1, R1 and R3 may each independently be substituted- or unsubstituted-C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl. R2 and R4 may each independently be hydrogen, substituted- or unsubstituted-C1-C10 alkyl, or alkylsilyl. Rm and Rn may each independently be a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain. M1+ and M2+ may each independently be a hydrogen ion, an alkali metal ion, or an ammonium ion. In an implementation, R1 and R3 may each independently be methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, tert-butyl, cyclohexyl, phenyl, trimethylsilyl, triethylsilyl, etc. R2 and R4 may each independently be hydrogen, methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, tert-butyl, cyclohexyl, trimethylsilyl, triethylsilyl, etc.

In the disulfide compound represented by Formula 1, the carbon atom adjacent to the sulfonate terminal group may have a substituent, i.e., R1 and R3, of substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl. A disulfide compound including such a substituent at the carbon atom adjacent to the sulfonate terminal group may have improved chemical stability, compared to a disulfide compound in which the carbon atom adjacent to the sulfonate terminal group is unsubstituted. Due to the excellent stability, the disulfide compound including the substituent at the carbon atom adjacent to the sulfonate terminal group may not be readily decomposed while performing an electroplating process. Therefore, the disulfide compound may be used as an accelerator to extend a usable lifetime of the composition for copper plating. Thus, the composition including such a disulfide compound may reduce a generation of voids in copper wiring, even if the composition for copper plating is repeatedly used for coating a larger number of, e.g., substrates or wafers, with copper.

In an implementation, the disulfide compound may include a compound represented by Formula 2:

In Formula 2, R5 and R6 may each independently be C1-C4 alkyl (e.g., methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, or tert-butyl) or trialkylsilyl. M1+ and M2+ may each independently be a hydrogen ion, an alkali metal ion, or an ammonium ion.

Examples of the disulfide compound suitable for use in the composition of an embodiment may include bis(3-sulfo-3-methylpropyl) disulfide salt, bis(3-sulfo-3-ethylpropyl) disulfide salt, bis(3-sulfo-3-isopropylpropyl) disulfide salt, bis(3-sulfo-3-t-butylpropyl) disulfide salt, bis(3-sulfo-3-trimethylsilylpropyl) disulfide salt, bis(3-sulfo-3,3-dimethylpropyl) disulfide salt, bis(3-sulfo-3,3-diethylpropyl) disulfide salt, bis(2-sulfo-2-methylethyl) disulfide salt, bis(2-sulfo-2-ethylethyl) disulfide salt, bis(4-sulfo-4-methylbutyl) disulfide salt, bis(4-sulfo-4-ethylbutyl) disulfide salt, bis(5-sulfo-5-methylpentyl) disulfide salt, bis(6-sulfo-6-methylhexyl) disulfide salt, 3-sulfo-3-methylpropyl-4-sulfo-4-methylbutyl disulfide salt, 2-sulfo-2-methylpropyl-3-sulfo-3-methylpropyl disulfide salt, and combinations thereof.

The composition for copper plating may include the disulfide compound at a concentration of about 0.1 mg/L to about 10 g/L. In an implementation, the disulfide compound may be included at a concentration of about 0.1 mg/L to about 200 mg/L.

The composition for copper plating may include an aqueous electrolyte solution containing a copper ion. The aqueous electrolyte solution may include, e.g., dissolved copper ions and an electrolyte for providing electric conductivity to a plating bath.

Examples of a suitable copper salt that may be soluble in the aqueous electrolyte solution may include copper sulfate, copper carbonate, copper oxide, copper chloride, copper fluoroborate, copper (II) nitrate, copper ethanesulfonate, copper methanesulfonate, copper propanolsulfonate, copper acetate, copper citrate, and combinations thereof. The copper salt may be included in the composition at a concentration of about 0.1 g/L to about 1,000 g/L. In an implementation, the soluble copper salt may be copper sulfate pentahydrate (CuSO4·5H2O) and may be included at a concentration of about 1 g/L to about 300 g/L.

The aqueous electrolyte solution may include and acid, e.g., an inorganic acid or an organic acid. Examples of the acid that may be used in the aqueous electrolyte solution may include sulfuric acid, acetic acid, fluoroboric acid, methanesulfonic acid, ethanesulfonic acid, citric acid, etc. The aqueous electrolyte solution may include the acid at a concentration of about 0.1 g/L to about 1,000 g/L. In an implementation, the acid may be included at a concentration of about 1 g/L to about 200 g/L. The aqueous electrolyte solution may also include a halogen ion, e.g., a chloride ion, at a concentration of about 0 mg/L to about 1,000 mg/L.

The composition for copper plating may include a suppressor to, e.g., reduce a growth rate of copper or to suppress movement of a copper ion in the aqueous electrolyte solution. Examples of the suppressor may include a copolymer of polyethylene oxide (PEO) and polypropylene oxide (PPO), polyethylene oxide, polypropylene oxide, polyethyleneimine, etc. Examples of the copolymer of PEO and PPO may include a triblock copolymer of PEO-PPO-PEO, a diblock copolymer of PEO-PPO, a triblock copolymer of PPO-PEO-PPO, a tetrablock copolymer of PEO-PPO-PEO-PPO, etc. A weight average molecular weight (Mw) of the polymer used as the suppressor may be about 100 to about 100,000 g/mol.

In an implementation, the composition for copper plating may include the triblock copolymer of PEO-PPO-PEO as the suppressor. A Mw of the triblock copolymer of PEO-PPO-PEO may be about 300 to about 10,000 g/mol. In the triblock copolymer, a weight ratio of ethylene oxide (EO % (w/w)) based on the total weight of ethylene oxide (EO) and propylene oxide (PO) may be about 10% to about 90%. In another implementation, the triblock copolymer of PEO-PPO-PEO may have a Mw of about 2,500 to about 5,000 g/mol and a ratio of ethylene oxide (EO % (w/w)) of about 30% to about 60%. In still another implementation, the triblock copolymer of PEO-PPO-PEO may have an average molar mass of about 2,500 to about 3,500 g/mol. Maintaining the Mw at about 2,500 to about 5,000 g/mol and the EO content in the triblock copolymer of PEO-PPO-PEO at about 30% to about 60% may help ensure that characteristics of filling with copper a trench and/or a hole (e.g., a via hole or a contact hole) having a high aspect ratio in a copper plating process are improved.

The suppressor may be included in the composition for copper plating at a concentration of about 1 mg/L to about 500 g/L. In an implementation, the concentration of the suppressor may be about 10 mg/L to about 10 g/L.

The composition for copper plating may include a leveler for, e.g., reducing a copper deposition rate and/or planarizing an upper face or a top face of a copper plating layer. Examples of the leveler may include sulfoproylated polyethyleneimine, Janus Green B (diethyl safranine azo dimethyl aniline), 1-(3-sulfopropyl)pyridinium betaine, 3-formyl-1-(3-sulfopropypl)pyridinium betaine, isoquinoline 1-propanesulfonic acid, 3-pyridinesulfonic acid, nicotinamide N-propylsulfonate, alkyl amine oxide, and combinations thereof.

In an implementation, the leveler may include a betaine compound represented by at least one of Formulae 3 and 4 below.

In Formulae 3 and 4, R7 and R10 may each independently be C1-C20 alkyl, cycloalkyl, or aromatic hydrocarbon, R8, R9, R11, and R12 may each independently be C1-C4 alkyl, and n may be an integer of 1 to about 10.

The betaine compound, e.g., a compound represented by Formulae 3 or 4, may greatly improve flatness of an upper face of a copper plating layer or a copper wiring formed while filling a void in an object, e.g., an insulation layer having a seed layer thereon, during a copper plating process. In an implementation, R7 and R10 may each independently be C6-C20 alkyl (e.g., hexyl, octyl, decyl, dodecyl, tetradecyl, hexadecyl, octadecyl, etc.). R8, R9, R11, and R12 may each independently be methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, tert-butyl, etc. The alkylene chain (—(CH2)n-) may be, e.g., an ethylene chain, a propylene chain, a butylene chain, a hexylene chain, etc.

Examples of the betaine compound may include lauryl dimethyl betaine, lauryl methyl ethyl betaine, lauryl diethyl betaine, hexyl dimethyl betaine, octyl dimethyl betaine, decyl dimethyl betaine, tetradecyl dimethyl betaine, hexadecyl dimethyl betaine, octadecyl dimethyl betaine, cyclohexyl dimethyl betaine, phenyl dimethyl betaine, tolyl dimethyl betaine, lauramidopropyl betaine, octylamidopropyl betaine, decylamidopropyl betaine, tetradecylamidopropyl betaine, hexadecylamidopropyl betaine, lauramidobutyl betaine, lauramidoethyl betaine, lauramidohexyl betaine, decylamidobutyl betaine, decyamidohexyl betaine, cyclohexylamidopropyl betaine, and combinations thereof.

The composition for copper plating may include the leveler at a concentration of about 0.1 mg/L to about 10 g/L. In an implementation, the leveler may be included at a concentration of about 10 mg/L to about 500 mg/L.

The composition for copper plating may include the aqueous electrolyte solution and an additive including at least one of the accelerator, the suppressor, and the leveler. In an implementation, the composition for copper plating may include the aqueous electrolyte solution and one of the accelerator, the suppressor, or the leveler. In another implementation, the composition for copper plating may include the aqueous electrolyte solution and two of the accelerator, the suppressor, and the leveler. In still another implementation, the composition for copper plating may include the aqueous electrolyte solution, the accelerator, the suppressor, and the leveler.

The composition for plating copper may be used in forming a copper wiring of, e.g., a semiconductor device or an integrated circuit device. The composition for copper plating may beneficially reduce the generation of voids in a copper wiring, even if the composition for copper plating is repeatedly used for coating a large number of, e.g., substrates of wafers, with copper. A high quality copper structure may be obtained using the composition for copper plating, because the composition may sufficiently fill with copper a trench and/or a hole, e.g., a via hole or a contact hole, having a high aspect ratio while suppressing the generation of voids in the copper structure. Further, the composition for copper plating may also advantageously enhance surface flatness of a copper plating layer filling a trench or a hole.

FIGS. 1 through 4 illustrate cross-sectional views of stages in a method of forming a copper wiring according to an embodiment. Referring to FIG. 1, an insulation layer 110 may be formed on a substrate 100. A mask pattern 120 may be formed on the insulation layer 110. Conductive structures (not illustrated) may be formed on the substrate 100. The conductive structures may include, e.g., a contact region doped with impurities (i.e., an impurity region), a gate electrode, a capacitor, a contact, a plug, a pad, a wiring, etc. The substrate 100 may include, e.g., a silicon wafer, a silicon-germanium substrate, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, a metal oxide single-crystalline substrate, etc.

The insulation layer 110 may be formed on the substrate 100 using an insulation material, e.g., oxide, nitride, oxynitride, etc. In an implementation, the insulation layer 110 may be formed using a silicon oxide, e.g., phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin on glass (SOG), tetraethyl orthosilicate (TEOS), plasma enhanced-TEOS (PE-TEOS), O3-TEOS, high density plasma-chemical vapor deposition (HDP-CVD) oxide, etc. In another implementation, the insulation layer 110 may be formed using a low-k material having a dielectric constant lower than that of silicon oxide. The low-k material may improve a resistance-capacitance (RC) delay time to thereby greatly reduce a signal delay in a circuit. Examples of the low-k material may include carbon-doped silicon oxide, carbon-doped hydrogenated silicon oxide, silicon oxynitride, hydrogenated silicon oxide, black diamond, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), fluorinated silicate glass (FSG), organic silicate glass (OSG), etc. In an implementation, the insulation layer 110 may have a multi-layered structure including, e.g., an oxide layer, a nitride layer, and/or an oxynitride layer.

Referring to FIG. 1, a mask pattern 120 may be formed on the insulation layer 110. The mask pattern 120 may be an etching mask for an etching process for partially etching the insulation layer 110. Therefore, the mask pattern 120 may be formed using a material having an etching selectivity relative to the insulation layer 110. The mask pattern 120 may include, e.g., a photoresist or a hardmask. For example, a photoresist film may be formed on the insulation layer 110 and then an exposure process and a developing process may be performed on the photoresist film to form the mask pattern 120 on the insulation layer 110.

Referring to FIG. 2, a recess 130 may be formed in the insulation layer 110 by etching a portion of the insulation layer 110. The recess 130 may be, e.g., a via hole, a contact hole, an opening, a trench, etc. When the conductive structure, e.g., a contact region formed in the substrate, a gate, a pad, a plug, a wiring, etc., is positioned under the insulation layer 110, the recess 130 may be an opening that exposes the conductive structure.

The recess 130 formed in the insulation layer 110 may have an aspect ratio being defined as a ratio of a height (H) to a width (W) of the recess 130. The recess 130 may have an aspect ratio (H:W) less than or equal to about 30:1. For example, the aspect ratio (H:W) of the recess 130 may be about 1:1,000 to about 30:1, or about 1:10 to about 20:1. In an implementation, the aspect ratio (H:W) of the recess 130 may be at least about 1:2, 1:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 10:1 or 15:1. The recess 130 may have a width of about 5 nm to about 1 μm . In an implementation, the recess 130 may have a width of about 10 nm to about 500 nm. In another implementation, the width of the recess 130 may be about 100 nm or less (e.g., about 90 nm, about 70 nm, about 40 nm or about 30 nm).

Referring to FIG. 3, a copper layer 140 may be formed on the insulation layer 110 to fill the recess 130. The copper layer 140 may be formed by, e.g., performing an electroplating process using the composition for copper plating according to an embodiment. The electroplating process using the composition for copper plating may fill the recess 130 having a high aspect ratio with the copper layer 140 without generation of undesirable voids, may improve surface flatness of the copper layer 140, and may also reduce the number of voids even if the number of, e.g., substrates or wafers, on which the copper electroplating process is performed is large.

The electroplating process may be carried out using a plating apparatus that may include a plating bath containing the plating composition, a substrate holder for supporting the substrate 100 acting as a cathode, an anode, and a current source for providing current. During the electroplating process, the substrate 100 may rotate at a predetermined speed. For example, the substrate 100 may rotate at a speed of about 0.1 to about 3000 rpm. The composition may be provided onto the substrate 100 at a flow rate of, e.g., about 0.1 to about 300 L/min. A current density of the electroplating process may be, e.g., about 0.1 to about 300 mA/cm2.

A diffusion barrier layer (not illustrated) may be formed on a bottom and sidewalls of the recess 130 and/or an upper face of the insulation layer 110 prior to forming the copper layer 140 on the insulation layer 110. The diffusion barrier layer may prevent copper atoms of the copper layer 140 from diffusing into the insulation layer 110 or other adjacent structures. The diffusion barrier layer may be a single layer formed of, e.g., titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, tantalum silicide nitride, titanium silicide nitride, etc., or a multi-layer including at least two of the above-mentioned materials.

A seed layer (not illustrated) may be formed on the bottom and sidewalls of the recess 130 and/or an upper face of the insulation layer 110 prior to forming the copper layer 140 on the insulation layer 110. The seed layer may improve a deposition rate of copper during the electroplating process. The seed layer may be formed by, e.g., a CVD process or a PVD process. The seed layer may include, e.g., copper (Cu), gold (Au), silver (Ag), platinum (Pt), and/or ruthenium (Ru). In an implementation, the seed layer may be formed on the diffusion barrier layer.

Referring to FIG. 4, an upper portion of the copper layer 140 may be removed until the insulation layer 110 is exposed. As a result, a copper wiring 150 may be formed in the recess 130 of the insulation layer 110. The upper portion of the copper layer 140 may be removed by performing a planarization process, e.g., a chemical mechanical polishing (CMP) process.

The copper wiring 150 may be, e.g., a pad to fill a hole or a line or a bar to fill a trench extending along a predetermined direction. The copper wiring 150 may be electrically connected to other conductive structures, e.g., an impurity region, a gate electrode, a capacitor, a contact, a plug, a pad and/or a wiring, etc., formed on the substrate 100.

FIGS. 5 through 10 illustrate cross-sectional views of stages in a method of forming a copper wiring according to another embodiment. Referring to FIG. 5, a substrate 200 having a conductive structure 205 thereon may be prepared. The conductive structure 205 may be, e.g., a contact region, which may be a portion of the substrate 200 doped with impurities. The contact region may be formed by, e.g., implanting impurities into a portion of the substrate 200. In an implementation, the conductive structure 205 may be, e.g., a contact, a plug, a pad, a lower wiring, a gate electrode, or a capacitor electrode, which may be a component of a semiconductor device or an integrated circuit device.

A first etching stop layer 210, a first insulation layer 215, a second etching stop layer 220, and a second insulation layer 225 may be sequentially formed on the substrate 200 having the conductive structure 205. The first etching stop layer 210 and the second etching stop layer 220 may be formed using a material having an etching selectivity relative to the first insulation layer 215 and the second insulation layer 225, respectively. The first etching stop layer 210 and the second etching stop layer 220 may include, e.g., silicon nitride, silicon oxynitride, silicon carbide, silicon carbon-nitride, and/or silicon oxide, etc.

The first insulation layer 215 and the second insulation layer 225 may be formed using an insulation material, e.g., an oxide, a nitride and/or an oxynitride, etc. The first insulation layer 215 and the second insulation layer 225 may be formed using the same material or different materials from one another. The first and the second insulation layer 215 and 225 may each independently include, e.g., PSG, BPSG, USG, SOG, TEOS, PE-TEOS, O3-TEOS, HDP-CVD oxide, etc. In an implementation, the first and the second insulation layer 215 and 225 may be formed using a low-k dielectric material, e.g., carbon-doped silicon oxide, carbon-doped hydrogenated silicon oxide, hydrogenated silicon oxide, SiOCH, SiOC, SiOH, HSQ, MSG, FSG, OSG, black diamond, etc.

Referring to FIG. 5, a first mask pattern 230 may be formed on the second insulation layer 225. The first mask pattern 230 may be an etching mask for partially etching the first and second insulation layer 215 and 225 and the first and the second etching stop layer 210 and 220. The first mask pattern 230 may include a material having an etching selectivity relative to the second insulation layer 215. The first mask pattern 230 may be, e.g., a photoresist pattern or a hardmask pattern. When the first mask pattern 230 includes a hardmask material, the first mask pattern 230 may be formed by patterning a hardmask material layer using a photoresist pattern formed on the hardmask material layer.

Referring to FIG. 6, the second insulation layer 225, the second etching stop layer 220, the first insulation layer 215, and the first etching stop layer 210 may be partially etched to form a first opening 235 exposing the conductive structure 205. The first opening 235 may be, e.g., a contact hole exposing a contact region or a doped portion of a substrate or a via hole exposing a contact, a pad, a plug, a lower wiring, a gate electrode, or a capacitor electrode.

After forming the first opening 235 exposing the conductive structure 205 through the second insulation layer 225, the second etching stop layer 220, the first insulation layer 215, and the first etching stop layer 210, a second mask pattern 237 may be formed on the second insulation layer 225. The second mask pattern 237 may be an etching mask for partially etching the second insulation layer 225.

Referring to FIG. 7, the second insulation layer 225 and the second etching stop layer 220 may be partially etched to form a second opening 240 exposing the first opening 235. The second opening 240 may partially expose the first insulation layer 215. The second opening 240 may be, e.g., a trench having a line shape or a bar shape and/or a hole having a dimension larger than a dimension of the first opening 235.

As described above, the second opening 225 may be formed in the second insulation layer 225 after forming the first opening 235 in the first and the second insulation layer 215 and 225. The method of forming the first opening 235 and the second opening 240 in the first and the second insulation layer 215 and 225 is not limited thereto. In an implementation, the second opening 240 exposing a portion of a first insulation layer 215 may be formed by partially etching the second insulation layer 225 and then the first opening 235 exposing the conductive structure 205 may be formed by partially etching an exposed portion of the first insulation layer 215.

Referring to FIG. 8, a diffusion barrier layer 245 and a seed layer 250 may be sequentially formed on bottoms and sidewalls of the first opening 235 and the second opening 240 and an upper face of the second insulation layer 225. The diffusion barrier layer 245 may be a single layer or a multi-layer. The diffusion barrier layer 245 may include, e.g., titanium; titanium nitride, tantalum, tantalum nitride, tungsten nitride, tantalum silicide nitride, titanium silicide nitride, etc. The seed layer 250 may include, e.g., copper, gold, silver, platinum, ruthenium, etc. The seed layer 250 may be formed by, e.g., a CVD process.

Referring to FIG. 9, a copper layer 255 may be formed on the seed layer 250. The copper layer 255 may be formed by performing an electroplating process using the composition for copper plating according to an embodiment. The electroplating process may form the copper layer 255 in the first opening 235 and the second opening 240 without generation of voids, may improve surface flatness of the copper layer 255, and may also reduce the generation of voids in the copper layer 255, even if the composition for copper plating is repeatedly used for coating a larger number of, e.g., substrates or wafers, with copper.

Referring to FIG. 10, an upper portion of the copper layer 255 may be removed until the second insulation layer 225 is exposed. As a result, a copper wiring 260 may be formed in the first opening 235 and the second opening 240. Removing the upper portion of the copper layer 255 may be performed by a planarization process, e.g., a CMP process. The copper wiring 260 may include, e.g., a contact pad or a contact plug in the first opening 235 connected to a contact region of the substrate 200 and/or a conductive line in the second opening 240 extending in a predetermined direction. In another implementation, the copper wiring 260 may include a pad or a via contact in the first opening 235 connected to a contact, a plug, a pad, a lower wiring, a gate electrode, or a capacitor electrode and/or a conductive line in the second opening 240 extending in a predetermined direction.

Example embodiments will be described with reference to Examples and Comparative Examples of preparation of compositions for copper plating. These are illustrative of example embodiments and are not intended to be limiting.

Preparation of Composition for Copper Plating Example 1

An aqueous solution including copper sulfate pentahydrate (CuSO4·5H2O) at a concentration of about 50 g/L, sulfuric acid (H2SO4) at a concentration of about 10 g/L, and hydrochloric acid (HCl) at a concentration of about 50 mg/L was prepared as an electrolyte solution. After adding a disulfide compound (as an accelerator) to a concentration of about 25 mg/L, a triblock copolymer of PEO-PPO-PEO (as a suppressor) to a concentration of about 100 mg/L, and Janus Green B (diethyl safranine azo dimethyl aniline) (as a leveler) to a concentration of about 10 mg/L into the aqueous electrolyte solution, the admixture was sufficiently stirred to prepare a composition for copper plating. Pluronic L62 ((EO)5(PO)30(EO)5), which has a Mw of about 2,200 g/mol and an EO content (EO %) of about 20% (w/w), was used as the suppressor. Bis(3-sulfo-3-methylpropyl) disulfide dipotassium salt (Me-SPS) was used as the accelerator.

Comparative Example 1

A composition for copper plating was prepared by substantially the same method as that of Example 1, except that bis(3-sulfopropyl) disulfide disodium salt (SPS) was used as the accelerator instead of using Me-SPS.

Example 2

A composition for copper plating was prepared by substantially the same method as that of Example 1, except that Pluronic L64 ((EO)13(PO)30(EO)13) having a Mw of about 2,900 g/mol and an EO content (EO %) of about 40% (w/w) was used as the suppressor instead of using Pluronic L62.

Example 3

A composition for copper plating was prepared by substantially the same method as that of Example 1, except that Pluronic L44 ((EO)10(PO)23(EO)10) having a Mw of about 2,200 g/mol and an EU content (EO %) of about 40% (w/w) was used as the suppressor instead of using Pluronic L62.

Example 4

A composition for copper plating was prepared by substantially the same method as that of Example 1, except that Pluronic P84 ((EO)19(PO)39(EO)19) having a Mw of about 4,000 g/mol and an EO content (EO %) of about 40% (w/w) was used as the suppressor instead of using Pluronic L62.

Example 5

A composition for copper plating was prepared by substantially the same method as that of Example 1, except that Pluronic P85 ((EO)26(PO)40(EO)26) having a Mw of about 4,800 g/mol and an EO content (EO %) of about 50% (w/w) was used as the suppressor instead of using Pluronic L62.

Example 6

A composition for copper plating was prepared by substantially the same method as that of Example 2, except that sulfopropylate polyethyleneimine was used as the leveler instead of Janus Green B.

Example 7

An aqueous solution including copper sulfate pentahydrate (CuSO4·5H2O) at a concentration of about 50 g/L, sulfuric acid (H2SO4) at a concentration of about 10 g/L, and hydrochloric acid (HCl) at a concentration of about 50 mg/L was prepared as an electrolyte solution. After adding a disulfide compound (as an accelerator) to a concentration of about 25 mg/L, a triblock copolymer of PEO-PPO-PEO (as a suppressor) to a concentration of about 100 mg/L, and lauryl dimethyl betaine (as a leveler) to a concentration of about 10 mg/L into the aqueous electrolyte solution, the admixture was sufficiently stirred to prepare a composition for copper plating. Pluronic L62 ((EO)5(PO)30(EO)5), which has a Mw of about 2,200 g/mol and an EO content (EO %) of about 20% (w/w), was used as the suppressor. Bis(3-sulfopropyl) disulfide disodium salt (SPS) was used as the accelerator.

Example 8

A composition for copper plating was prepared by substantially the same method as that of Example 7, except that lauramidopropyl dimethyl betaine was used as the leveler instead of lauryl dimethyl betaine.

Comparative Examples 2 and 3

Compositions for copper plating was prepared by substantially the same method as that of Example 7 except the type of the leveler. In Comparative Example 2,1-(3-sulfonpropyl)pyridinium betaine was used as the leveler instead of lauryl dimethyl betaine. In Comparative Example 3, a commercially-available leveler (Lugalvan G35 (polyethyleneimine), manufactured by BASF) was used instead of lauryl dimethyl betaine.

Fabrication of a Copper Wiring and Evaluation of Stability of an Accelerator

A copper wiring was formed by performing an electroplating process using each of the compositions prepared in Example 1 and Comparative Example 1. In particular, a silicon oxide layer was formed on a silicon wafer and then a via hole having an aspect ratio of about 1:1 and a bottom width of about 400 nm was formed in the silicon oxide layer. A titanium nitride diffusion barrier layer and a copper seed layer, each having a small thickness, were formed on the silicon oxide layer and a bottom and sidewalls of the via hole. The composition of Example 1 and Comparative Example 1 were each poured into a plating bath and then the prepared silicon wafer was dipped in the plating bath. A copper electroplating process was carried out using the silicon wafer as a cathode. The copper electroplating process was performed at room temperature. A rotational speed of the wafer was about 20 rpm and a current density was about 6.4 mA/cm2. By performing the copper electroplating process, a copper layer, i.e., a copper wiring, was formed on the seed layer to fill the via hole.

To evaluate stability of the accelerator, the process for forming the copper wiring was repeatedly and continuously performed on a large number of wafers using the compositions prepared in Example 1 and Comparative Example 1. The ratio of voids generated in the initially formed copper wiring was counted, and the ratio of voids in the copper wiring formed after using the composition for about 6 hours and about 24 hours was also measured. The ratio of voids denotes a ratio of the number of the copper wirings having a void relative to the total number of copper wirings formed. The results regarding the void ratio are shown in Table 1 below.

TABLE 1 Ratio of voids Composition for copper plating Initial After 6 hours After 24 hours Example 1 Me-SPS 0%  0%  0% Comparative Example 1 SPS 0% 18% 27%

As shown in Table 1, no void was observed in the copper wirings formed using the composition of Example 1 at the initial time and after using the composition for about 6 hours and about 24 hours. When the composition of Comparative Example was used for forming a copper wiring, no void was observed in the initially formed copper wiring. However, the copper wiring formed after about 6 hours usage had voids at a ratio of about 18%. Further, the copper wiring formed after about 24 hours usage had voids at a ratio of about 27%.

It appears that initial performance of the composition of Example 1 including Me-SPS as an accelerator and the composition of Comparative Example 1 including SPS may be similar from the observation of no voids. After repeatedly and continuously using the composition for copper plating for at least about 6 hours, the two compositions exhibited substantially different abilities to suppress generation of voids in the copper wiring. Excellent performance of the composition of Example 1 may be due to the outstanding stability of Me-SPS, as compared to the stability of SPS. It may be seen that SPS is more easily decomposed in the plating composition, thereby decreasing the usable life span of the composition, as compared with Me-SPS, which includes a methyl substituent on the carbon atom adjacent to the sulfonate group. A substituted sulfoalkylene disulfide compound including a substituent, e.g., an alkyl, at the carbon atom adjacent to the sulfonate group may improve the usable life span of a plating composition and may also reduce generation of defects, e.g., voids, as compared to an unsubstituted sulfoalkylene disulfide compound.

Evaluation of Hole-Filling Characteristics According to Types of Suppressors

Copper wirings were formed by performing electroplating processes using each of the compositions prepared in Examples 1 through 6. In particular, a silicon oxide layer was formed on a silicon wafer and then a via hole having an aspect ratio of about 7:1 and a bottom width of about 40 nm was formed in the silicon oxide layer. A titanium nitride diffusion barrier layer and a copper seed layer, each having a small thickness, were formed on the silicon oxide layer and a bottom and sidewalls of the via hole. A copper electroplating process was performed at room temperature and a current density of about 6.4 mA/cm2. By performing the copper electroplating process, a copper wiring was formed on the seed layer to fill the via hole. After cutting the copper wiring, the ratio of voids generated in the copper wiring was measured in order to evaluate hole-filling characteristics of the composition. The ratio of voids represents a ratio of the number of the copper wirings having a void relative to a total number of the copper wirings formed. The results regarding the void ratio are shown in Table 2 below.

TABLE 2 PEO-PPO-PEO (Mw, EO % (w/w)) Ratio of voids Example 1 L62 (2,200, 20%) 17% Example 2 L64 (2,900, 40%) 0% Example 3 L44 (2,200, 40%) 42% Example 4 P84 (4,000, 40%) 0% Example 5 P85 (4,800, 50%) 0% Example 6 L64 (2,900, 40%) 0%

Referring to Table 2, it may be seen that the ratio of voids in the copper wiring may change as the Mw and the ethylene oxide content (EO %) of PEO-PPO-PEO vary. When Pluronic L62 or L44, which have a Mw of about 2,200 were used, a large ratio of voids was observed. When Pluronic L64, P84, and P85, which have Mws of about 2,900, 4,000, and 4,800, respectively, were used, no voids were observed. Therefore, it may be seen that a copper wiring may be formed in a via hole having a high aspect ratio without generation of voids by selecting a PEO-PPO-PEO copolymer having a Mw of at least about 2,500.

When Pluronic L64, P84, and P85 are compared with each other, voids were not observed in the copper wiring, but the copper wiring did have different film uniformity. Copper wiring formed using Pluronic L64 exhibited excellent properties in film uniformity, surface flatness, and roughness. When Pluronic P84 and P85, which have a Mw greater than that of Pluronic L64, were used in forming the copper wiring, bubbles were generated in the plating bath during the electroplating process and copper wiring having relatively poor surface flatness and uniformity was obtained. Accordingly, it may be noted that uniformity of a copper wiring may be enhanced by selecting a PEO-PPO-PEO copolymer having a Mw of about 3,500 or less.

When Pluronic L62 (Example 1) was used as a suppressor, no voids were observed in the copper wiring formed in the via hole having an aspect ratio of about 1:1, whereas voids were generated in the copper wiring formed in the via hole having a higher aspect ratio of about 7:1.

Evaluation of Surface Flatness of a Copper Wiring according to Types of Levelers

Copper wirings were formed by performing electroplating processes using each of the compositions prepared in Examples 7 and 8 and Comparative Examples 2 and 3. Plating characteristics were evaluated by analyzing surface profiles of copper plating layers. The copper electroplating processes were performed by the same method as that of the evaluation of the stability of the accelerator. The via hole had an aspect ratio of about 1:1 and a bottom width of about 400 nm. A copper wiring was formed to fill the via hole in a silicon oxide layer. A thickness of the copper layer over a top surface of the silicon oxide layer was about 400 nm. Surface flatness of the copper wiring was analyzed by observing a cross-sectioned face of the copper wiring with an electron microscope. The results are shown in Table 3 and FIGS. 11 through 13.

TABLE 3 Leveler Profile of copper wiring Example 7 Lauryl dimethyl betaine Flat surface Example 8 Lauramidopropyl dimethyl Flat surface betaine Comparative 1-(3-Sulfopropyl)pyridinium Protruded portion over Example 2 betaine via hole Comparative Polyethyleneimine Depressed portion over Example 3 via hole

FIGS. 11 through 13 illustrate diagrams of cross-sections of copper wirings formed using the compositions of Example 7 and Comparative Examples 2 and 3, respectively. In FIGS. 11 through 13, a substrate 300, 300′, and 300″, a silicon oxide layer 310, 310′, and 310″ formed on the substrate, a via hole 320, 320′, and 320″ formed in the silicon oxide layer, and a copper layer 330, 330′, and 330″ formed on the silicon oxide layer to fill the via hole are illustrated.

As shown in Table 3 and FIG. 11, electroplating with a composition including the betaine compounds used in Examples 7 and 8 produced copper layers 330 having flat surfaces without forming protruded or depressed portions of the copper layers 330 over the via hole 320. However, as shown in Table 3 and FIG. 12, electroplating with a composition including the 1-(3-sulfopropyl)pyridinium betaine of Comparative Example 2 generated a protruded portion of a copper layer 330′ over the via hole 320′, because copper deposition occurred more rapidly over the via hole 320′. As shown in Table 3 and FIG. 13, electroplating with a composition including the polyethyleneimine of Comparative Example 3 formed a depressed portion of the copper layer 330″ over the via hole 320″, because the copper deposition proceeded relatively slowly. Accordingly, it may be seen that surface flatness and/or uniformity of a copper wiring may be improved by using an alkyl betaine compound, e.g., lauryl dimethyl betaine, or an amidoalkyl betaine compound, e.g., lauramidopropyl dimethyl betaine, as a leveler in a composition for electroplating copper.

In a process of manufacturing conductive structures, it may be difficult to dry-etch copper, in contrast to aluminum. Thus, a copper structure may be formed by filling with copper a template having a predetermined shape. This is known as a damascene process. The template used in the damascene process may have a recessed portion that may be filled with the copper. Filling the template with copper may be performed by a film deposition process, e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD), or a wet electroplating process. The electroplating process may improve characteristics of filling the recessed portion of the template.

Besides electronic device fabrication, the copper electroplating process has been used in various other industries, e.g., automobile manufacturing, shipbuilding, machine industry, aircraft manufacturing, etc. The electroplating process may typically be performed by flowing current between two electrodes in a plating solution. A substrate on which a plating layer will be formed is used as one electrode. The plating solution may include a sufficient amount of an electrolyte, which electricity may pass through. The plating solution may include dissolved copper ions and other additives. The additives may include, e.g., a suppressor for reducing copper growth or transfer of copper ions, an accelerator (or a brightener) for raising a copper deposition rate as a catalyst of a reduction reaction of copper ions, and/or a leveler for adsorbing to a surface of an electrode (e.g., a cathode) to reduce a deposition rate and current efficiency and to planarize an upper face of a copper plating layer.

In an electroplating process for forming a copper structure, a template having a fine recessed portion may be used. It may be difficult to fill the fine recessed portion of the template with copper without generation of an undesirable void. Efforts to reduce the generation of voids in a fine copper wiring have been made, but development of a copper plating process which may be employed in forming a copper wiring having reduced dimensions is still in demand.

According to an embodiment, a substituted sulfoalkylene disulfide compound used as an accelerator may extend the usable life span of a plating composition and may greatly reduce the generation of voids, despite an increase in the number of processed substrates. By selecting a PEO-PPO-PEO having a proper Mw and EO content as a suppressor, hole (or trench) filling characteristics of a copper plating composition may be improved and generation of voids may be prevented. Further, an alkyl betaine compound or an amidoalkyl betaine compound used as a leveler may enhance surface flatness of a copper wiring.

Exemplary embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

1. A method of forming a copper wiring, the method comprising:

forming an insulation layer having a recessed portion on a substrate; and
forming a copper layer on the insulation layer to fill the recessed portion by performing an electroplating process using a composition that includes an aqueous electrolyte solution containing a copper ion and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO),
wherein: in Formula 1, R1 and R3 are each independently substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, R2 and R4 are each independently hydrogen, C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, Rm and Rn are each independently a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion, in Formulae 3 and 4, R7 and R10 are each independently C1-C20 alkyl, cycloalkyl or aromatic hydrocarbon, R8, R9, R11, and R12 are each independently C1-C4 alkyl, and n is an integer of 1 to about 10, and the triblock copolymer of PEO-PPO-PEO has a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

2. The method as claimed in claim 1, wherein:

the composition includes the disulfide compound represented by Formula 1, and
the disulfide compound is a compound represented by Formula 2,
wherein R5 and R6 are each independently methyl, ethyl, propyl, isopropyl, n-butyl, sec-butyl, tert-butyl or trialkylsilyl, and M1+ and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion.

3. The method as claimed in claim 1, wherein:

the composition includes the PEO-PPO-PEO triblock copolymer, and
the PEO-PPO-PEO triblock copolymer has a weight average molecular weight of about 2,500 to about 3,500 g/mol.

4. The method as claimed in claim 1, wherein:

the composition includes the betaine compound represented by at least one of Formulae 3 and 4, and
in Formulae 3 and 4, R7 and R10 are each independently C6-C20 alkyl.

5. The method as claimed in claim 1, wherein:

the composition includes the betaine compound represented by at least one of Formulae 3 and 4, and
the betaine compound represented by at least one of Formulae 3 and 4 includes at least one of lauryl dimethyl betaine and lauramidopropyl dimethyl betaine.

6. The method as claimed in claim 1, further comprising forming a diffusion barrier layer on the insulation layer having the recessed portion.

7. The method as claimed in claim 1, further comprising forming a seed layer on the diffusion barrier layer, wherein the copper layer is formed on the seed layer to fill the recessed portion.

8. The method as claimed in claim 1, wherein the aqueous electrolyte solution further includes a halide ion.

9. A method of forming a copper wiring, the method comprising:

forming a first insulation layer on the substrate having a conductive structure, the first insulation layer including a first opening exposing the conductive structure;
forming a second insulation layer on the first insulation layer, the second insulation layer including a second opening exposing the first opening;
forming a diffusion barrier layer along the first opening and the second opening;
forming a seed layer on the diffusion barrier layer;
forming a copper layer on the seed layer to fill the first opening and the second opening by performing an electroplating process using a composition that includes an aqueous electrolyte solution containing a copper ion and at least one of a disulfide compound represented by Formula 1, a betaine compound represented by at least one of Formulae 3 and 4, and a triblock copolymer of polyethylene oxide-polypropylene oxide-polyethylene oxide (PEO-PPO-PEO),
wherein: in Formula 1, R1 and R3 are each independently substituted or unsubstituted C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, R2 and R4 are each independently hydrogen, C1-C10 alkyl, cycloalkyl, aromatic hydrocarbon, or alkylsilyl, Rm and Rn are each independently a C1-C10 alkylene chain, a C3-C10 cycloalkylene chain, or a C4-C10 aromatic hydrocarbon chain, and M1+and M2+ are each independently a hydrogen ion, an alkali metal ion, or an ammonium ion, in Formulae 3 and 4, R7 and R10 are each independently C1-C20 alkyl, cycloalkyl or aromatic hydrocarbon, R8, R9, R11, and R12 are each independently C1-C4 alkyl, and n is an integer of 1 to about 10, and
the triblock copolymer of PEO-PPO-PEO has a weight average molecular weight of about 2,500 to about 5,000 g/mol and an ethylene oxide content (EO %, w/w) of about 30% to about 60%.

10. The method as claimed in claim 9, wherein the first opening has a hole shape and the second opening has a trench shape.

11. The method as claimed in claim 9, wherein the conductive structure is a portion of the substrate doped with impurities.

12. The method as claimed in claim 9, wherein the conductive structure is one of a pad or a conductive line formed on the substrate.

13. The method as claimed in claim 9, wherein the composition includes the disulfide compound represented by Formula 1.

14. The method as claimed in claim 9, wherein the aqueous electrolyte solution further includes a halide ion.

15-17. (canceled)

Patent History
Publication number: 20100084277
Type: Application
Filed: Oct 6, 2009
Publication Date: Apr 8, 2010
Inventors: Myung-Beom Park (Hwaseong-si), Hye-Young Jin (Suwon-si), Jin-Seo Lee (Anyang-si), Hye-Jin Cha (Suwon-si), Jung-Sik Choi (Seongnam-si), Jung-Ho Lee (Suwon-si), Ki-Hag Lee (Seoul)
Application Number: 12/588,136
Classifications
Current U.S. Class: Coating Has Specified Thickness Variation (205/95)
International Classification: C25D 5/16 (20060101);