SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor device comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a conductive layer formed on the insulating film, and an etch-stop insulating film formed within the conductive layer to stop etching.
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This application claims priority to Japanese patent application No. 2003-427092, the content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor device which can restrain a microloading effect liable to be produced when a portion of the device to be patterned at a high aspect ratio is etched, and a method of fabricating the same.
2. Description of the Related Art
For example, when a semiconductor substrate is patterned, etching is sometimes carried out simultaneously both for a part where a pattern is dense (hereinafter referred to as “dense pattern part”) and for another part where a pattern is sparse (hereinafter referred to as “sparse pattern part”). In this case, since it is hard fro a radical in the etching to reach a deep part of dense pattern part of a film to be etched, an etching speed in the dense pattern part becomes lower than an etching speed in the sparse pattern part. As a result, the microloading effect results in level differences among patterns etched under the same conditions.
The polycrystalline silicon layer 3 formed on the gate oxide film 2 is further formed with a skirt 3a by the microloading effect when the ONO film 5 and the polycrystalline silicon layer 3 are further etched with the resist 9 patterned on the semiconductor substrate 1 or the like serving as the mask until the gate oxide film 2 is exposed. As a result, electrons charged in a floating gate formed by the polycrystalline silicon layer 3 flows through the skirt 3b between memory cells. In the worst case, there is a possibility that the semiconductor device cannot maintain a normal operation such that failure may occur. To overcome the aforementioned drawback, JP-A-2001-189300 discloses a method of fabricating a semiconductor device, for example. In the disclosed method, the dense pattern part is re-etched with only the sparse pattern part being masked, whereby residue due to the microloading effect is eliminated.
In a semiconductor device to be patterned until the aspect ratio of about 5, pattern formation can be carried out while an adverse effect of the microloading effect is restrained as the result of recent improvement in the semiconductor processing. However, in more recent years, the pattern design has been carried out according to a design rule that a semiconductor device is patterned at a further higher aspect ratio (7 or above, for example). Thus, the semiconductor processing needs to be improved itself. Moreover, the dense pattern part and the sparse pattern part need to be formed individually when the aforesaid process is used. Further, in order that the first polycrystalline silicon layer 3 may serve as a floating gate of a flash memory, a recess 3a is sometimes formed in the first polycrystalline silicon layer 3. The ONO film 5 is formed so as to fill and cover the recess 3a. The polycrystalline silicon layer 6 is formed on the ONO film 5. Further, the WSi film or W film 7, the silicon nitride or silicon oxide 8 and the resist 9 are formed and subsequently, an etching process is carried out nearly to the ONO film 5 so that the dense pattern is not underetched. In this case, when the adverse effect of the microloading is considered, the polycrystalline silicon layer 6 is over-etched as far as the inside of the recess 3a formed by the ONO film 5 and the polycrystalline silicon layer 3.
BRIEF SUMMARY OF THE INVENTIONTherefore, an object of the present invention is to provide a semiconductor device in which occurrence of failure due to the microloading can be reduced even when a part to be patterned at a high aspect ratio is etched and the dense pattern part and the sparse pattern part can be prevented from being formed individually, and a method of fabricating the semiconductor device.
Another object of the invention is to provide a semiconductor device in which a polycrystalline silicon layer is buried in a recess and the recess can be prevented from being over-etched when a part to be patterned at a high aspect ratio is etched, and a method of fabricating the semiconductor device.
The present invention provides a semiconductor device comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a first polycrystalline layer formed on the insulating film, an inter-poly insulating film formed on the first polycrystalline layer, a second polycrystalline layer formed on the inter-poly insulating film, an etch-stopping insulating film formed on the second polycrystalline layer including a silicon oxide film, and a third polycrystalline layer formed on the etch-stopping insulating film.
The invention also provides a method of fabricating a semiconductor device comprising a first step of forming a gate insulating film on a semiconductor substrate, a second step of forming a first polycrystalline silicon layer on the gate insulating film formed by the first step so that a recess is formed, a third process of forming a first insulating film on a surface of the first polycrystalline silicon layer formed by the second step, a fourth step of forming and flattening a second polycrystalline silicon layer so that the recess formed in the first polycrystalline silicon layer is buried in the second polycrystalline silicon layer, a fifth step of forming a second insulating film on the second polycrystalline silicon layer flattened by the fourth step or the first insulating film, the second insulating film being made of a material differing from one for the first insulating film, a sixth step of forming an etched film on the second insulating film formed by the fifth step, a seventh step of etching the etched film so that a surface of the second insulating film is exposed, an eighth step of eliminating the exposed second insulating film, and a ninth step of etching the first polycrystalline silicon layer.
Other objects, features and advantages of the present invention will become clear upon reviewing the following description of the embodiment with reference to the accompanying drawings, in which:
One embodiment of the present invention will be described with reference to
The non-volatile memory 11 has the following structure in the element region Sa. In the element region Sa as shown in
A second polycrystalline silicon conductive layer 17 is formed on the ONO film 16. The second polycrystalline silicon conductive layer 17 corresponds to a lower portion LP4 of a control electrode and has a fourth upper surface US4. The second polycrystalline silicon conductive layer 17 further corresponds to a fifth lower portion LP5 of an upper electrode and has a sixth upper surface US6. A silicon oxide film 18 serving as a first insulating film is formed on the first polycrystalline silicon layer 14. A silicon oxide film 18 (a second insulating film) serving as an etch-stop insulating film is formed on the second polycrystalline silicon layer 17. A third polycrystalline silicon conductive layer 19 is formed on the silicon oxide film 18. The third polycrystalline silicon conductive layer 19 corresponds to a fourth upper surface UP4 of the control electrode and further to a fifth upper portion UP5 of an upper electrode. A tungsten-silicide (WSi) film 20 is formed on the third polycrystalline silicon layer 19. The third polycrystalline silicon layer 17 and the WSi film 20 functions as a control gate electrode of the non-volatile memory 11. A silicon nitride film 21 is formed on the WSi film 20.
Further, in the element isolation region Sb as shown in
The ONO film 16 is formed on the STI 15 in the element isolation region Sb. The ONO film 16 functions as an isolation film of a memory cell of floating gate electrode in the non-volatile memory and electrically isolates the first polycrystalline silicon layer 14 from the first polycrystalline silicon layer 14 adjacent to the former. More specifically, a recess 14c is formed between the first polycrystalline silicon layers 14 adjacent to each other or in a portion encompassed by a third side surface SS3, a fifth side surface SS5 and the first upper surface US1. The ONO film 16 is formed along the recess 14c so as to have a uniform thickness. Thus, the ONO film 16 functions as the isolation film of the floating gate electrode in the non-volatile memory.
The second polycrystalline silicon layer 17 is formed on the ONO film 16 formed in the recess 14c so as to be buried in the recess 14c or so as to fill and cover the recess 14c. The second polycrystalline silicon layer 17 is formed so as to cover the ONO film 16 so that the characteristics of the ONO film 16 as an insulating film in the element region Sa and element isolation region Sb are prevented from being adversely affected by the second polycrystalline silicon layer 17.
Further, the second polycrystalline silicon layer 17 is planarized on the ONO film 16 so that an upper surface (the fourth upper surface US4) of the second polycrystalline silicon layer 17 is substantially co-planar in the element region Sa and the element isolation region Sb. On the second polycrystalline silicon layer 17 are sequentially stacked the silicon oxide film 18, third polycrystalline silicon layer 19, WSi film 20 and silicon nitride film 21 in each of the element region Sa and element isolation region Sb.
Fabrication Method:The non-volatile memory is fabricated as follows. Firstly, the description will deal with initial fabrication steps which do not constitute the characteristics of the embodiment. As shown in
As shown in
Further, as shown in
Subsequently, as shown in
Subsequently, as shown in
Subsequently, as shown in
More specifically, consider a case where both a dense pattern part (see
In other words, even if the recess 14c is formed while the second polycrystalline silicon film 17 constitutes a lower layer relative to the silicon oxide film 18, the flat silicon oxide film 18 functions as an etch-stop, whereupon the second polycrystalline silicon layer 17 buried in the recess 14c can be prevented from being etched. Consequently, adverse effects due to the microloading effect can be restrained or reduced.
Subsequently, as shown in
Subsequently, as shown in
Subsequently, the non-volatile memory is fabricated further through a resist removal step, a wiring step and an inspection step. Since these steps have no relation with the characteristics of the embodiment, the description of these steps is eliminated.
In the above-described embodiment, the surface of the third polycrystalline silicon layer 17 buried in the recess 14c is heat-treated such that the third polycrystalline silicon layer 17 is oxidated so as to cover the ONO film 16, and the silicon oxide film 18 is formed so as to serve as the etch-stop insulating film. After the layers 19 to 21 have been stacked, etching is carried out until the silicon oxide film 18 is exposed. Subsequently, the silicon oxide film 18 is positively etched and then, etching is re-carried out so as to reach the part just over the surface of the gate oxide film 13. Accordingly, even if the etching speed differs in the dense and sparse pattern parts when the dense pattern part whose aspect ratio is about 7 and the sparse pattern part whose aspect ratio is less than 7 are simultaneously etched, etching is carried out so as to reach the same middle position (the silicon oxide film 18) in both dense and sparse pattern parts and thereafter, etching can be carried out so as to reach a part just over the surface of the gate oxide film 13. Consequently, the possibility of resulting in formation of a level difference or a skirt after the etching can be reduced and thus, the adverse effects due to the microloading effect can be restrained or reduced.
Modified Forms:The invention should not be limited by the foregoing embodiment but may be modified or expanded as follows.
The invention may be applied to other memories such SRAM or other semiconductor devices such as microprocessors since these devices encounter the same problem according to a degree of integration.
The second insulating film 18 may be formed at any position between the surface of the gate oxide film 13 and the location where the silicon nitride film 21 is to be formed. Further, the second insulating film 18 may be made of any material which allows the second insulating film 18 to function as the etch stop and which differs from that of the first insulating film 16.
The foregoing description and drawings are merely illustrative of the principles of the present invention and are not to be construed in a limiting sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the invention as defined by the appended claims.
Claims
1. A method of fabricating a semiconductor device comprising:
- (1) forming a gate insulating film on a semiconductor substrate;
- (2) forming a first polycrystalline silicon layer on the gate insulating film so that a recess is formed;
- (3) forming a first insulating film on a surface of the first polycrystalline silicon layer;
- (4) forming and flattening a second polycrystalline silicon layer so that the recess formed in the first polycrystalline silicon layer is buried in the second polycrystalline silicon layer;
- (5) forming a second insulating film on the second polycrystalline silicon layer flattened by (4) or the first insulating film, wherein the second insulating film is made of a material differing from one for the first insulating film;
- (6) forming an etched film on the second insulating film formed by (5);
- (7) etching the etched film so that a surface of the second insulating film is exposed;
- (8) eliminating the exposed second insulating film; and
- (9) etching the first polycrystalline silicon layer.
2. The method according to claim 1, wherein the second polycrystalline silicon layer is formed so as to cover the first insulating film and then flattened in (4), and a surface of the second polycrystalline silicon layer is oxidated by a heat treatment, thereby forming the second insulating film in (5).
3. The method according to claim 1, wherein in (4), the second polycrystalline silicon layer is formed so as to cover the first insulating film and the second polycrystalline silicon layer is etched back by an RIE process so as to be flattened, and in (5), the second insulating film is formed on the second polycrystalline silicon layer flattened by (4).
4. The method according to claim 1, wherein in (4), the second polycrystalline silicon layer is formed so as to cover the first insulating film and the second polycrystalline silicon layer is etched back by an RIE process so as to be flattened, and in (5), a surface of the second polycrystalline silicon layer formed in (4) so as to cover the second insulating film is oxidated by a heat treatment, thereby forming the second insulating film in (5).
5. The method according to claim 1, wherein in (5), the second insulating film is formed so that a film thickness of the first insulating film is prevented from varying.
6. The method according to claim 1, wherein in (5), the second insulating film is formed so that a film thickness of the first insulating film is prevented from varying.
7. The method according to claim 1, wherein an ONO film is formed as the first insulating film in (3).
8. The method according to claim 2, wherein an ONO film is formed as the first insulating film in (3).
9. The method according to claim 1, wherein the first insulating film is etched under a high selective etching condition.
10. The method according to claim 1, which is applied to a method of fabricating a non-volatile memory.
Type: Application
Filed: Dec 8, 2009
Publication Date: Apr 8, 2010
Applicant: KABUSHIKI KAISHA TOSHIBA (Tokyo)
Inventor: Kenji MATSUZAKI (Yokkaichi)
Application Number: 12/632,915
International Classification: H01L 21/336 (20060101);