Gate Insulator Structure Constructed Of Plural Layers Or Nonsilicon Containing Compound Patents (Class 438/591)
  • Patent number: 10964795
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10964716
    Abstract: A semiconductor device comprises a substrate. A plurality of electrode layers and a plurality of insulating layers are formed in an alternating stack above the substrate. A semiconductor column extends through the plurality of electrode layers and the plurality of insulating layers. The semiconductor column comprises a single-crystal semiconductor material on an outer peripheral surface facing the electrode and insulating layers. First insulating films are formed between the semiconductor column and the electrode layers. The first insulating films are spaced from each other along the column length. Each first insulating film corresponds to one electrode layer. A charge storage layer is between each of the first insulating films and the electrode layers. A second insulating film is between the charge storage layer and each of the electrode layers.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinji Mori, Kazuhiro Matsuo, Yuta Saito, Keiichi Sawa, Kazuhisa Matsuda, Atsushi Takahashi, Masayuki Tanaka, Kenichiro Toratani
  • Patent number: 10957545
    Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin
  • Patent number: 10930566
    Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
  • Patent number: 10879370
    Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
  • Patent number: 10879072
    Abstract: First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is performed to increase the temperature of a front surface of a semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. This achieves the activation of the impurities. Subsequently, second irradiation which gradually decreases the emission output from the maximum value over a time period in the range of 3 to 50 milliseconds is performed to maintain the temperature of the front surface within a ±25° C. range around the target temperature for a time period in the range of 3 to 50 milliseconds. This prevents the occurrence of process-induced damage while suppressing the diffusion of the impurities.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: December 29, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kazuhiko Fuse, Shinichi Kato, Kenichi Yokouchi
  • Patent number: 10879393
    Abstract: A method of fabricating a semiconductor device includes forming a dummy gate structure on a substrate, forming gate spacers on sidewalls of the dummy gate structure, and depositing an interlayer dielectric layer around the gate spacers. The method also includes removing the dummy gate structure to form a space between the gate spacers, and forming a gate structure in the space, wherein the gate structure includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. The method further includes removing a portion of the gate electrode layer to form a recess that is surrounded by the gate dielectric layer. In addition, the method includes implanting on the interlayer dielectric layer to form a strained layer for bending the gate dielectric layer and the gate spacers towards the recess.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Jeng-Ya Yeh
  • Patent number: 10868055
    Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 15, 2020
    Inventor: Ming-Chyi Liu
  • Patent number: 10867862
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Patent number: 10847515
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 24, 2020
    Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
  • Patent number: 10840330
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10832974
    Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shiu-Ko JangJian, Chi-Cheng Hung, Horng-Huei Tseng
  • Patent number: 10833088
    Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
  • Patent number: 10825697
    Abstract: There is installed a configuration that includes a process container; a heater chamber exhaust duct configured to discharge an air that has cooled a space at which a heater is installed; a gas box exhaust duct configured to suck and discharge an atmosphere in a gas box; a scavenger exhaust duct configured to suck and discharge an atmosphere in a scavenger; a local exhaust duct configured to suck and discharge an atmosphere in a local exhaust port installed in a transfer chamber; an exhaust damper valve including an opening degree variable mechanism installed in at least one selected from the group of the heater chamber exhaust duct, the gas box exhaust duct, the scavenger exhaust duct, and the local exhaust duct; and a controller configured to remotely control an opening degree of the exhaust damper valve.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: November 3, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Tomoyuki Yamada, Tadashi Kontani, Seiyo Nakashima, Mikio Ohno
  • Patent number: 10790299
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises forming on a substrate a mold structure including a plurality of sacrificial patterns and a plurality of dielectric patterns that are alternately stacked, patterning the mold structure to form a plurality of preliminary stack structures extending in a first direction, forming on the preliminary stack structures a support pattern that extends in a direction intersecting the first direction and extends across the preliminary stack structures, and replacing the sacrificial patterns with conductive patterns to form a plurality of stack structures from the preliminary stack structures. The support pattern remains on the stack structures.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sunil Shim
  • Patent number: 10749011
    Abstract: Embodiments of the present invention are directed to techniques for forming a vertical field effect transistor (VFET) top spacer using an area selective cyclic deposition. In a non-limiting embodiment of the invention, a first semiconductor fin is formed over a substrate. A second semiconductor fin is formed over the substrate and adjacent to the first semiconductor fin. A dielectric isolation region is formed between the first semiconductor fin and the second semiconductor fin. A top spacer is formed between the first semiconductor fin and the second semiconductor fin by cyclically depositing dielectric layers over the dielectric isolation region. The dielectric layers are inhibited from depositing on a surface of the first semiconductor fin and on a surface of the second semiconductor fin during the cyclic deposition process.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Yongan Xu, Yi Song
  • Patent number: 10707132
    Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 7, 2020
    Assignees: International Business Machines Corporation, GlobalFoundries Inc., LAM Research Corporation
    Inventors: Georges Jacobi, Vimal K. Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian
  • Patent number: 10707121
    Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: July 7, 2020
    Assignee: Intel Corporatino
    Inventors: Jun Liu, Mark A. Levan, Gordon A. Haller, Fei Wang, Wei Yeeng Ng, Wesley O. McKinsey, Zhiqiang Xie, Jeremy F. Adams, Hongbin Zhu, Jun Zhao
  • Patent number: 10685977
    Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., .LTD.
    Inventors: Jongwon Kim, Hyeong Park, Hyunmin Lee, Hojong Kang, Joowon Park, Seungmin Song
  • Patent number: 10665685
    Abstract: A method includes forming a gate dielectric layer over a semiconductor substrate, forming a first metal element-containing layer over the gate dielectric layer, and thermal soaking the first metal element-containing layer in a first gas, such that a constituent of the first gas is diffused into the first metal element-containing layer.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ming Lin, Peng-Soon Lim, Zi-Wei Fang
  • Patent number: 10665600
    Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Patent number: 10573565
    Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
  • Patent number: 10546876
    Abstract: Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first and second connection lines that connect the first and second stacks of electrodes. In some embodiments, the first connection lines have a first length and the second connection lines have a second length that is longer than the first length of the first connection lines. In some embodiments, the first connection lines connect inner portions of the first stack of electrodes to inner portions of the second stack of electrodes. In some embodiments, the second connection lines connect outer portions of the first stack of electrodes to outer portions of the second stack of electrodes.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Lee, Woo-Sung Yang, Kwan-Yong Kim
  • Patent number: 10529572
    Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
  • Patent number: 10515979
    Abstract: A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes sequentially stacked on the substrate, vertical structures penetrating the stack structure, and cell contact plugs connected to end portions of the gate electrodes in the contact region. Upper surfaces of the end portions of the gate electrodes have an acute angle with respect to an upper surface of the substrate in the cell array region.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JoongShik Shin, Jihoon Park, Yong-Hoon Son, Jongho Woo, Euntaek Jung, Junho Cha
  • Patent number: 10490452
    Abstract: A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsan-Chun Wang, Chung-Feng Nieh, Chiao-Ting Tai
  • Patent number: 10475898
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Patent number: 10438774
    Abstract: An etching method is provided for processing a substrate that includes a first region having an insulating film arranged on a silicon layer and a second region having the insulating film arranged on a metal layer. The etching method includes a first step of etching the insulating film into a predetermined pattern using a plasma generated from a first gas until the silicon layer and the metal layer are exposed, and a second step of further etching the silicon layer after the first step using a plasma generated from a second gas including a bromide-containing gas.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: October 8, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Hayato Hishinuma, Hisashi Hirose
  • Patent number: 10418284
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Woong Lee, Hanseung Kwak, Youngmook Oh
  • Patent number: 10410858
    Abstract: Embodiments of the invention provide selective film deposition in a recessed feature of a substrate using halogen deactivation. A substrate processing method includes a) providing a substrate containing a field area and a recessed feature having a sidewall and a bottom, b) exposing the substrate to a first precursor gas to form a first precursor layer on the substrate, c) exposing the substrate to a plasma-excited halogen-containing gas to deactivate or at least partially remove the first precursor layer on the field area of the substrate and the bottom of the recessed feature, and d) exposing the substrate to a second precursor gas that reacts with the first precursor layer to form a material layer on the sidewall of the recessed feature but not on the field area and the bottom of the recessed feature that has been deactivated by the plasma-excited halogen-containing gas.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Takaaki Tsunomura
  • Patent number: 10403731
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 3, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak
  • Patent number: 10347496
    Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a base including first, second, third, and fourth regions, used for first, second, third, and fourth transistors, respectively. A gate dielectric layer is on the first, second, third and fourth regions of the base. A first material layer is on the gate dielectric layer. A second material layer is on the first material layer above the fourth region. A third material layer is on the first material layer above the third region and on the second material layer above the fourth region. A fourth material layer is on the third material layer above the third and fourth regions and on the first material layer on the second region. The first material layer above the first region is used as a first work function layer for the first transistor.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xin He
  • Patent number: 10332786
    Abstract: A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 25, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua-Feng Chen, Kuo-Hua Pan
  • Patent number: 10319734
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Akifumi Gawase, Kei Watanabe, Shinya Arai
  • Patent number: 10304746
    Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
  • Patent number: 10304745
    Abstract: A semiconductor apparatus has an N-type Metal Oxide Semiconductor (NMOS) device. The NMOS device includes a substrate and a gate structure overlying the substrate. The gate structure includes a metal gate, an N-type work function metal layer on the bottom and sides of the metal gate and including a first N-type work function metal layer having a first Ti content greater than a first Al content, and a high K dielectric layer directly contacting a bottom and the sides of the N-type work function metal layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 28, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10297668
    Abstract: A method of forming a plurality of vertical fin field effect transistors is provided. The method includes forming a first vertical fin on a first region of a substrate and a second vertical fin on a second region of the substrate, forming an isolation region between the first region and the second region, forming a gate dielectric layer on the vertical fins, forming a first work function layer on the gate dielectric layer, removing an upper portion of the first work function layer from the vertical fin on the first region and the vertical fin on the second region, and forming a second work function layer on the first work function layer and the exposed upper portion of the gate dielectric layer, wherein the first work function layer and second work function layer forms a first combined work function layer with a step in the second work function layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Brent A. Anderson, Injo Ok, Soon-Cheon Seo
  • Patent number: 10283618
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Hsuan Chang, Yao-Hsien Chung, Fu-Yu Tsai
  • Patent number: 10269659
    Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an NMOS region and a PMOS region; forming a first high-K gate dielectric layer on the NMOS region of the substrate; forming an interfacial layer on the PMOS region of the substrate; forming a second high-K gate dielectric layer on the interfacial layer and the first high-K gate dielectric layer; forming a metal layer on the second high-K gate dielectric layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10263009
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-hyun Lee, Jin-taek Park, Young-woo Park
  • Patent number: 10249488
    Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chun-Ya Chiu, Chin-Hung Chen, Chi-Ting Wu, Yu-Hsiang Lin
  • Patent number: 10224329
    Abstract: Methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region. The gate layer is etched using the remaining inner vertical layers and the spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a smaller gate length than a gate length of the second gates.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10204788
    Abstract: A method of forming a high dielectric constant (high-k) dielectric layer by atomic layer deposition includes the following steps. Cycles are performed one after another, and each of the cycles sequentially includes performing a first oxygen precursor pulse to supply an oxygen precursor to a substrate disposed in a reactor; performing a first oxygen precursor purge after the first oxygen precursor pulse; performing a chemical precursor pulse to supply a chemical precursor to the substrate after the first oxygen precursor purge; and performing a chemical precursor purge after the chemical precursor pulse. The first oxygen precursor pulse, the first oxygen precursor purge, the chemical precursor pulse, and the chemical precursor purge are repeated by at least 3 cycles. A second oxygen precursor pulse is performed to supply an oxygen precursor to the substrate after the cycles. A second oxygen precursor purge is performed after the second oxygen precursor pulse.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shan Ye, Shih-Cheng Chen, Tsuo-Wen Lu, Tzu-Hsiang Su, Po-Jen Chuang
  • Patent number: 10186519
    Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongwon Kim, Hyeong Park, Hyunmin Lee, Hojong Kang, Joowon Park, Seungmin Song
  • Patent number: 10164049
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Sheng-Chi Shih, Yi-Jen Chen
  • Patent number: 10134861
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
  • Patent number: 10115808
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li
  • Patent number: 10096468
    Abstract: A method is for improving adhesion between a semiconductor substrate and a dielectric layer. The method includes depositing a silicon dioxide adhesion layer onto the semiconductor substrate by a first plasma enhanced chemical vapor deposition (PECVD) process, and depositing the dielectric layer onto the adhesion layer by a second PECVD process. The first PECVD process is performed in a gaseous atmosphere comprising tetraethyl orthosilicate (TEOS) either in the absence of O2 or with O2 introduced into the process at a flow rate of 250 sccm or less.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 9, 2018
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Kathrine Crook, Stephen R Burgess, Andrew Price
  • Patent number: 10043818
    Abstract: Semiconductor devices are provided. A semiconductor device includes first and second stacks of electrodes. Moreover, the semiconductor device includes first and second connection lines that connect the first and second stacks of electrodes. In some embodiments, the first connection lines have a first length and the second connection lines have a second length that is longer than the first length of the first connection lines. In some embodiments, the first connection lines connect inner portions of the first stack of electrodes to inner portions of the second stack of electrodes. In some embodiments, the second connection lines connect outer portions of the first stack of electrodes to outer portions of the second stack of electrodes.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Lee, Woo-Sung Yang, Kwan-Yong Kim
  • Patent number: 10014380
    Abstract: A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 3, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Chun Chen, Unsoon Kim, Mark Ramsbey, Kuo Tung Chang, Sameer Haddad, James Pak