With An Insulated Gate (epo) Patents (Class 257/E21.409)

  • Patent number: 10340383
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 2, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Patent number: 10332877
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
    Type: Grant
    Filed: August 21, 2016
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 10249630
    Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10177145
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a device region, an isolation region, and a transition region between the device region and the isolation region, forming a plurality of fin structures on the device region of the substrate, forming a plurality of dummy fin structures on the transition region of the substrate, and forming an isolation structure on the device region, the isolation region, and the transition region of the substrate. The isolation structure further covers a portion of sidewall surfaces of the fin structures and the dummy fin structures. Moreover, the method includes forming a plurality of semiconductor devices on the fin structures in the device region after forming the isolation structure.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 8, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10170480
    Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10164010
    Abstract: Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hsien-Ching Lo, Haiting Wang, Yanping Shen, Yi Qi, Yongjun Shi, Hui Zang, Edward Reis
  • Patent number: 10103246
    Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10050030
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 10050143
    Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10043712
    Abstract: A semiconductor structure includes a substrate, at least two gate spacers, a gate stack, an insulating structure, and at least one sacrificial layer. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. The gate stack is disposed between the gate spacers and covers the semiconductor fin. The insulating structure is disposed between the gate spacers and adjacent to the gate stack. The sacrificial layer is disposed between at least one of the gate spacers and the insulating structure.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Fang Hsu, Pei-Lin Wu, Chun-Sheng Liang
  • Patent number: 10038074
    Abstract: The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first lightly doped offset region between the first source and the drain, and locating the second channel region and the second lightly doped offset region between the second source and the drain, and forming the first overlapping region and the second overlapping region respectively between the drain and the gate and between the second source and the gate, thus, the paths of the current flowing from the first, the second sources to the drain and the current flowing from the drain to the first, the second sources are the same. Namely, the current path from source to the drain and the current path from the drain to the source are the same. According, the symmetry of the TFT structure is realized.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shipeng Chi
  • Patent number: 10026727
    Abstract: A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wun-Jie Lin, Ching-Hsiung Lo, Jen-Chou Tseng
  • Patent number: 10014208
    Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Min-Choul Kim, Baik-Min Sung, Sang-Hyun Woo
  • Patent number: 9991269
    Abstract: The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 5, 2018
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventor: Syang-Ywan Jeng
  • Patent number: 9966416
    Abstract: A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube thin film transistor stacked with each other. The p-type carbon nanotube thin film transistor includes a first semiconductor carbon nanotube layer, a first drain electrode, a first source electrode, a functional dielectric layer, and a first gate electrode. The n-type carbon nanotube thin film transistor includes a second semiconductor carbon nanotube layer, a second drain electrode, a second source electrode, a first insulating layer, and a second gate electrode. The first drain electrode and the second drain electrode are electrically connected with each other. The first gate electrode and the second gate electrode are electrically connected with each other.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: May 8, 2018
    Assignees: Tsinghua Univeristy, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Qun-Qing Li, Xiao-Yang Xiao, Guan-Hong Li, Yuan-Hao Jin, Shou-Shan Fan
  • Patent number: 9960278
    Abstract: To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 1, 2018
    Inventors: Yuhei Sato, Keiji Sato, Toshinari Sasaki, Tetsunori Maruyama, Atsuo Isobe, Tsutomu Murakawa, Sachiaki Tezuka
  • Patent number: 9953880
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate layer on the fin-shaped structure and the STI; removing part of the gate layer, part of the fin-shaped structure, and part of the STI to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-yu Chen, Shou-Wei Hsieh
  • Patent number: 9935104
    Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Wei Zhao, Hong Yu, Xusheng Wu, Hui Zang, Zhenyu Hu
  • Patent number: 9917103
    Abstract: Methods of forming a diffusion break are disclosed. The method includes forming a diffusion break after source/drain formation, by removing a gate stack of the dummy gate to a buried insulator of an SOI substrate, creating a first opening; and filling the first opening with a dielectric to form the diffusion break. An IC structure includes the diffusion break in contact with an upper surface of the buried insulator. In an optional embodiment, the method may also include simultaneously forming an isolation in an active gate to an STI in the SOI substrate.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George R. Mulfinger, Jin Z. Wallner
  • Patent number: 9917176
    Abstract: A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate. Two cells adjacent to each other are formed on the semiconductor fin. A gate conductor is formed on a top of the semiconductor fin at a common boundary that is shared by the two cells. A gate spacer is formed to peripherally enclose the gate conductor. The gate conductor and the semiconductor fin are etched to form an air gap, thereby dividing the semiconductor fin into two portions of the semiconductor fin. A dielectric cap layer is deposited into the air gap to cap a top of the air gap.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: March 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 9899388
    Abstract: An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated circuit device, a plurality of grooves are formed in the inter-device isolation region of a substrate, a recess is formed by partially removing a surface of the substrate between the plurality of grooves, at least one fin-type active area is formed in a device region by etching the substrate in the device region and the inter-device isolation region, and the double-humped protrusion is formed from the surface of the substrate in the inter-device isolation region.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Il Kim, Jung-gun You, Gi-gwan Park
  • Patent number: 9887192
    Abstract: Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Edward J. Nowak, Brent A. Anderson
  • Patent number: 9876115
    Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has a dielectric portion extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The dielectric portion divides the semiconductor fin into two portions of the semiconductor fin.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 9824884
    Abstract: A method of depositing silicon nitride films on semiconductor substrates processed in a micro-volume of a plasma enhanced atomic layer deposition (PEALD) reaction chamber wherein a single semiconductor substrate is supported on a ceramic surface of a pedestal and process gas is introduced through gas outlets in a ceramic surface of a showerhead into a reaction zone above the semiconductor substrate, includes (a) cleaning the ceramic surfaces of the pedestal and showerhead with a fluorine plasma, (b) depositing a halide-free atomic layer deposition (ALD) oxide undercoating on the ceramic surfaces, (c) depositing a precoating of ALD silicon nitride on the halide-free ALD oxide undercoating, and (d) processing a batch of semiconductor substrates by transferring each semiconductor substrate into the reaction chamber and depositing a film of ALD silicon nitride on the semiconductor substrate supported on the ceramic surface of the pedestal.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 21, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: James S. Sims, Jon Henri, Ramesh Chandrasekharan, Andrew John McKerrow, Seshasayee Varadarajan, Kathryn Merced Kelchner
  • Patent number: 9793273
    Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: October 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9768074
    Abstract: A method of forming a transistor can include forming a gate mask on a substrate having a vertical location aligned with that of a transistor control gate; implanting first conductivity type dopants with the gate mask as an implant mask to form a first shallow halo region; implanting first conductivity type dopants with at least the gate mask as an implant mask to form a first deep halo region having a peak dopant concentration profile at a greater substrate depth than the first shallow halo region; forming an epitaxial layer on top of the substrate; forming a first control gate structure on the epitaxial layer; and forming a first source or drain region, of a second conductivity type, in at least the epitaxial layer to a side of the first control gate, and over the first shallow halo region and the first deep halo region.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 19, 2017
    Inventor: Samar K. Saha
  • Patent number: 9711619
    Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wen-Pin Peng, Min-hwa Chi
  • Patent number: 9680018
    Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek
  • Patent number: 9673227
    Abstract: The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate uses a connection semiconductor (42) that is formed in a semiconductor layer and is subjected to N-type heavy doping to connect a first semiconductor (41) and a second semiconductor (43) so as to connect the first TFT and the second TFT in series. The N-type heavily doped connection semiconductor (42) substitutes a connection electrode that is formed in a second metal layer in prior art techniques for preventing the design rules of the connection electrode and the second metal layer from being narrowed due to the connection electrode being collectively present on the second metal layer with signal lines of a data line and a voltage supply line and for facilitating increase of an aperture ratio and definition of a display panel.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: June 6, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Longqiang Shi, Baixiang Han
  • Patent number: 9659946
    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 23, 2017
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chien-Sheng Su, Jeng-Wei Yang, Yueh-Hsin Chen
  • Patent number: 9647122
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Hsin-Chieh Huang, Cheng-Chien Li
  • Patent number: 9627542
    Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-Ho Kwon, Cheol Kim, Ho-Young Kim, Se-Jung Park, Myeong-Cheol Kim, Bo-Kyeong Kang, Bo-Un Yoon, Jae-Kwang Choi, Si-Young Choi, Suk-Hoon Jeong, Geum-Jung Seong, Hee-Don Jeong, Yong-Joon Choi, Ji-Eun Han
  • Patent number: 9614035
    Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Ju-Youn Kim, Min-Choul Kim, Baik-Min Sung, Sang-Hyun Woo
  • Patent number: 9595597
    Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material. At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region. The embedded source/drain regions have a symmetrical shape and a uniform embedded interface.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: March 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9553089
    Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Hyung-Jong Lee, Sung-Min Kim, Chong-Kwang Chang
  • Patent number: 9502446
    Abstract: Provided are a poly-silicon thin film transistor (TFT), a poly-silicon array substrate and a preparing method thereof, and a display device for solving the problems of excessive mask plates, complicated process and high costs in a conventional technology. The method of preparing the poly-silicon TFT comprising a doped region comprises steps: forming a poly-silicon layer on a substrate, forming an active layer by a patterning process; forming a first insulating layer; forming, by a patterning process, via holes exposing the active layer, the source electrode and the drain electrode being connected through the via holes to the active layer; doping the active layer through the via holes by a doping process to form a doped region; forming a source-drain metal layer, and forming the source electrode and the drain electrode by a patterning process.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 22, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Fangzhen Zhang
  • Patent number: 9478642
    Abstract: A semiconductor structure, such as a FinFET, etc., includes a bi-portioned junction. The bi-portioned junction includes a doped outer portion and a doped inner portion. The dopant concentration of the outer portion is less than the dopant concentration of the inner portion. An electrical connection is formed by diffusion of the dopants within outer portion into a channel region and diffusion of the dopants within the outer portion into the inner region. A low contact resistance is achieved by a contact electrically contacting the relatively higher doped inner portion while device shorting is limited by the relatively lower doped outer portion.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9455334
    Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor FinFET is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 9449881
    Abstract: A method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a mask layer above the dielectric material. The mask layer has an opening defined therein. At least one etching process is performed to remove a portion of the at least one dielectric material exposed by the opening so as to expose a top surface portion and sidewall surface portions of at least one fin in the plurality of fins. The at least one dielectric material remains above the substrate adjacent the at least one fin. An etching process is performed to remove the at least one fin.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 20, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Ruilong Xie
  • Patent number: 9449882
    Abstract: In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and second semiconductor layers. A cover layer is formed on a bottom part of the fin structure so as to cover side walls of the bottom portion of the fin structure and a bottom part of side walls of the upper portion of the fin structure. An insulating layer is formed so that the fin structure is embedded in the insulating layer. A part of the upper portion is removed so that an opening is formed in the insulating layer. A third semiconductor layer is formed in the opening on the remaining layer of the second semiconductor layer. The insulating layer is recessed so that a part of the third semiconductor layer is exposed from the insulating layer, and a gate structure is formed.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chen Wang, Kai-Hsuan Lee, Sai-Hooi Yeong, Chia-Ta Yu
  • Patent number: 9431396
    Abstract: Methods of forming a SDB with a partial or complete insulator structure formed over the SDB and resulting devices are provided. Embodiments include forming a SDB with a first width in a substrate; forming a first metal gate in an ILD on top of the SDB, with a second width larger than the first width; forming second and third metal gates in the ILD on the substrate on opposite sides of the first metal gate, the second and third metal gates laterally separated from the first metal gate; forming a photoresist over the second and third gates; removing the first metal gate down to the SDB, forming a cavity; removing the photoresist; and filling the cavity with an insulator layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Bingwu Liu
  • Patent number: 9425255
    Abstract: Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: August 23, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sylvain Barraud, Yves Morand
  • Patent number: 9419097
    Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: August 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Michael A. Guillorn, Balasubramanian Pranatharthiharan, George S. Tulevski
  • Patent number: 9406676
    Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hong Yu, HongLiang Shen, Zhenyu Hu, Jin Ping Liu
  • Patent number: 9391195
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 9287399
    Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
  • Patent number: 9276002
    Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 1, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Qizhi Liu, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9040393
    Abstract: A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 26, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy