Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

Abstract: A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.

Abstract: A semiconductor device includes a first universal device formed over a substrate, an isolation structure over the first universal device, and a second universal device over the isolation structure. The first universal device includes a first source/drain (S/D) region formed over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region. The second universal device includes a third S/D region positioned over the isolation structure, a second channel region over the third S/D region, a fourth S/D region over the second channel region. The first universal device is one of a first n-type transistor according to first applied bias voltages, and a first p-type transistor according to second applied bias voltages. The second universal device is one of a second n-type transistor according to third applied bias voltages, and a second p-type transistor according to fourth applied bias voltages.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A method of forming an ultrasonic transducer device includes bonding a membrane to seal a transducer cavity with at least a portion of a getter material layer being exposed, the getter material layer comprising a portion of a bilayer stack compatible for use in damascene processing.

Abstract: A device includes a semiconductive substrate, a semiconductive fin, a stop layer, a fin isolation structure, and a spacer. The semiconductive fin is over the substrate. The stop layer is between the semiconductive substrate and the semiconductive fin. The fin isolation structure is in contact with the semiconductor fin and over the stop layer. A topmost surface of the fin isolation structure is higher than a topmost surface of the semiconductive fin. The spacer at least partially extends along a sidewall of the fin isolation structure.

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

Abstract: A semiconductor device includes a substrate that includes peripheral and logic cell regions, a device isolation layer that defines a first active pattern on the peripheral region and second and third active patterns on the logic cell region, and first to third transistors on the first to third active patterns. Each of the first to third transistors includes a gate electrode, a gate spacer, a source pattern and a drain pattern. The second active pattern includes a semiconductor pattern that overlaps the gate electrode. At least a portion of a top surface of the device isolation layer is higher than a top surface of the second and third active patterns. A profile of the top surface of the device isolation layer includes two or more convex portions between the second and third active patterns.

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer.

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.

Abstract: According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

Abstract: Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Abstract: A semiconductor device including an active region defined in a substrate; at least one channel layer on the active region; a gate electrode intersecting the active region and on the active region and surrounding the at least one channel layer; and a pair of source/drain regions adjacent to both sides of the gate electrode, on the active region, and in contact with the at least one channel layer, wherein the pair of source/drain regions includes a selective epitaxial growth (SEG) layer, and a maximum width of each of the pair of source/drain regions in a first direction is 1.3 times or less a width of the active region in the first direction.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a metal layer; and a conductive layer positioned between the silicon carbide layer and the metal layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×1017 cm?3 or less.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

Abstract: Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region arranged along a first direction, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate coving the first doped layer, the second doped layer, and sidewalls of the first gate structure, first trenches in the first dielectric layer at the first region and the third region respectively, a first conductive layer in the first trenches, a second conductive layer on a surface of the first conductive layer at the second sub-regions after forming the first conductive layer, and a third conductive layer on the contact region of the first gate structure.

Abstract: Techniques for forming gate last VFET devices are provided. In one aspect, a method of forming a VFET device includes: forming a stack on a wafer including: i) a doped bottom source/drain, ii) sacrificial layers having layers of a first sacrificial material with a layer of a second sacrificial material therebetween, and iii) a doped top source/drain; patterning trenches in the stack to form individual gate regions; filling the trenches with a channel material to form vertical fin channels; selectively removing the layers of the first sacrificial material forming first cavities in the gate regions; forming gate spacers in the first cavities; selectively removing the layer of the second sacrificial material forming second cavities in the gate regions; and forming replacement metal gates in the second cavities. A VFET device is also provided.

Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

Abstract: A display apparatus is provided which may include a substrate including a display area and a non-display area adjacent to the display area, a first thin-film transistor disposed on the substrate and including a first semiconductor layer including an oxide semiconductor material, and a second thin-film transistor disposed on the substrate and including a second semiconductor layer including a silicon semiconductor material, wherein a surface roughness of the first semiconductor layer is increased by plasma treatment. A method of manufacturing the display apparatus is also provided.

Abstract: A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

Abstract: The present invention provides a self-healing field-effect transistor (FET) device comprising a self-healing substrate and a self-healing dielectric layer, said substrate and said layer comprising a disulfide-containing poly(urea-urethane) (PUU) polymer, wherein the dielectric layer has a thickness of less than about 10 ?m, a gate electrode, at least one source electrode, and at least one drain electrode, said electrodes comprising electrically conductive elongated nanostructures; and at least one channel comprising semi-conducting elongated nanostructures. Further provided is a method for fabricating the FET device.

Abstract: The invention provides a contact plug structure. The contact plug structure comprises a substrate and a dielectric layer, and a first contact hole located in the dielectric layer and penetrating into the substrate, the first contact hole has a first through hole portion located in the dielectric layer and a first groove located in the substrate, and the first through hole portion is communicated with the first groove, the maximum width of the first groove is larger than that of the first through hole portion in the direction parallel to the substrate surface. A barrier layer at least partially covering the sidewall of the first groove. A conductive pad layer is located on the bottom surface of the first groove. The conductive core layer is arranged on the conductive pad layer, and the barrier layer wraps the conductive pad layer and the conductive core layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

Abstract: Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: A device includes a fin extending from a substrate; a gate stack over and along sidewalls of the fin; a gate spacer along a sidewall of the gate stack; an epitaxial source/drain region in the fin and adjacent the gate spacer, the epitaxial source/drain region including a first epitaxial layer on the fin, the first epitaxial layer including silicon and arsenic; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin; and a contact plug on the second epitaxial layer.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.