Abstract: A vertical tunneling field-effect transistor and a method for its manufacture are provided. According to methods herein disclosed, oppositely doped source and drain regions are formed, and an APAM delta layer is formed in the surface of the transistor substrate, beneath a metal gate, in electrical contact with, e.g., the source region. A dielectric layer intervenes between the substrate surface and the metal gate. An epitaxial cap layer directly over the APAM layer forms a dielectric layer interface with a dielectric layer, which is located between the epitaxial cap layer and the metal gate. A vertical channel is defined for tunneling between the APAM delta layer and an induced conduction channel adjacent to the dielectric layer interface that is formed in operation, and that is in electrical contact with, e.g., the drain region.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Abstract: Methods, systems and apparatus for managing capacitors in memory devices, e.g., three-dimensional (3D) memory devices are provided. In one aspect, a capacitor includes: a first terminal, a second terminal conductively insulated from the first terminal, and a capacitance structure that includes a plurality of layers sequentially stacked together. At least one layer includes: one or more first conductive parts and one or more second conductive parts that are conductively insulated in the layer, the one or more first conductive parts being conductively coupled to the first terminal, the one or more second conductive parts being conductively coupled to the second terminal. The at least one layer is configured such that at least one of the one or more second conductive parts forms at least one subordinate capacitor with at least one adjacent first conductive part.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n?1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n?1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

Abstract: A semiconductor device with high reliability is provided. A first step of forming a metal oxide containing indium over a substrate and a second step of performing microwave treatment from above the metal oxide are included. The first step is performed by a sputtering method using an oxide target containing indium. The second step is performed using a gas containing oxygen under reduced pressure, and by the second step, a defect in which hydrogen has entered an oxygen vacancy (VoH) in the metal oxide is divided into an oxygen vacancy (Vo) and hydrogen (H).

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: Provided is a physical quantity sensor including: a movable body; a base body; and a lid body, in which the movable body is accommodated in a space between the base body and the lid body, the space is sealed with a melt portion obtained by melting a through hole provided in the lid body, the lid body and the melt portion contain silicon, and the melt portion has a continuous curved surface having unevenness.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A method for forming an ultra-shallow junction includes the following operations: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, providing a dopant and implanting the dopant into the epitaxial layer and a part of the semiconductor substrate, and removing the epitaxial layer, to form the ultra-shallow junction.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.

Abstract: A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact. The etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

Abstract: A photoelectric conversion apparatus includes a semiconductor substrate having a first surface and a second surface, a plurality of photoelectric conversion regions including an impurity of a first conductivity type and arranged at the semiconductor substrate, a trench arranged between the photoelectric conversion regions, an impurity region including an impurity of a second conductivity type opposite to the first conductivity type and arranged along a sidewall of the trench, and a first film arranged at the first surface of the semiconductor substrate and the sidewall of the trench. The impurity region includes a first region with an impurity concentration of a first concentration and a second region with an impurity concentration of a second concentration lower than the first concentration, and a distance between the first surface and the first region is smaller than a distance between the first surface and the second region.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable display device is provided. The semiconductor device includes a first conductive layer, a first insulating layer, a semiconductor layer, and a pair of second conductive layers. The first insulating layer is in contact with a top surface of the first conductive layer. The semiconductor layer is in contact with a top surface of the first insulating layer. The pair of second conductive layers are in contact with a top surface of the semiconductor layer. The pair of second conductive layers are apart from each other in a region overlapping with the first conductive layer.

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Abstract: According to one embodiment, a semiconductor device includes a first insulating film formed of silicon nitride, a second insulating film disposed above the first insulating film and formed of silicon oxide, including a first region and a peripheral region surrounding the first region and thinner than the first region, an oxide semiconductor disposed on the second insulating film and intersecting the first region, a source electrode overlapping the peripheral region and a drain electrode overlapping the peripheral region. The first region is located between the source electrode and the drain electrode and separated from the source electrode and the drain electrode.

Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes a plurality of active areas separated from each other, the active areas extend along a first direction, and each active area includes a bit line contact area and two electrical connection areas located on both sides of the bit line contact area; forming first mask layers, which are separated from each other, on the substrate; forming spacer layers on two opposite side walls of each first mask layer; forming second mask layers between adjacent first mask layers; removing the spacer layers between the first mask layers and the second mask layers; and etching the substrate by using the first mask layers and the second mask layers as masks to form a bit line contact hole.

Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

Abstract: A semiconductor structure including a semiconductor substrate, an active area, a transistor gate, a fuse gate, a first dielectric pattern, a second dielectric pattern and a plurality of metal lines is provided. The active area is disposed in the semiconductor substrate. The transistor gate has a first line segment and a second line segment extending across the active area in a first direction. The fuse gate located between the first line segment and the second line segment extends across the active area in the first direction. The first dielectric pattern is disposed between the active area and the transistor gate. The second dielectric pattern is disposed between the active area and the fuse gate. The metal lines disposed on two opposite sides of the transistor gate are electrically connected to the active device.

Abstract: A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure comprises: providing a substrate comprising a first area for forming a P-channel Metal Oxide Semiconductor (PMOS) transistor and a second area for forming an N-channel Metal Oxide Semiconductor (NMOS) transistor; forming a channel layer on the surface of the first area of the substrate; adjusting the oxidation rate of the channel layer to reduce the difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the surfaces of the channel layer and the second area of the substrate to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.

Abstract: A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.

Abstract: According to an aspect, a display device with a touch detection function includes: a substrate; a drive electrode that extends in a first direction; and a plurality of touch detection electrodes that are metal wirings extending in a second direction different from the first direction. The metal wirings are arranged with a predetermined pitch so as to make capacitive coupling with the drive electrode.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, forming a gate spacer on opposing sides of the sacrificial gate structure, forming an amorphized region in the semiconductor fin not covered by the sacrificial gate structure and the gate spacer, wherein the amorphized region has an amorphous-crystalline interface having a first roughness, forming a stressor layer over the amorphized region, wherein the formation of the stressor layer recrystallizes the amorphous-crystalline interface from the first roughness to a second roughness that is less than the first roughness, and subjecting the amorphized region to an annealing process to recrystallize the amorphized region to a crystalline region, and the crystalline region comprising a dislocation.

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).

Abstract: An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a first base, a thin film transistor layer, and a plurality of pixel electrodes. The thin film transistor layer includes an insulating layer and a plurality of data lines. The data lines are divided into a plurality of first subsections corresponding to the pixel electrodes. A sum of thicknesses of the insulating layer and the first base corresponding to positions of the first subsections is less than a sum of thicknesses of the insulating layer and the first base corresponding to positions of the pixel electrodes.

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

Abstract: Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.

Abstract: Electronic circuits and methods encompassing an RF switch comprising a plurality of series-coupled (stacked) integrated circuit (IC) SOI MOSFETs having a distributed back-bias network structure comprising groups of substrate contacts coupled to a bias voltage source through a resistive ladder. The distributed back-bias network structure sets the common IC substrate voltage at a fixed DC bias but resistively decouples groups of MOSFETs with respect to RF voltages so that the voltage division characteristics of the MOSFET stack are maintained. The distributed back-bias network structure increases the voltage handling capability of each MOSFET and improves the maximum RF voltage at which a particular MOSFET is effective as a switch device, while mitigating loss, leakage, crosstalk, and distortion. RF switches in accordance with the present invention are particularly useful as antenna switches.

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Abstract: An optical device includes an optical modulator formed on a substrate. The optical device includes: a signal electrode for the optical modulator that is formed on the substrate; a ground electrode for the optical modulator that is formed on the substrate; an optical waveguide that is provided in a region between the signal electrode and the ground electrode; a first buffer region that is formed between the optical waveguide and the substrate; and second buffer regions that are formed between the optical waveguide and the signal electrode and between the optical waveguide and the ground electrode. A permittivity of the second buffer regions is higher than a permittivity of the first buffer region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.