ANALOG TO DIGITAL CONVERTER
An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.
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1. Field of the Invention
The present invention relates to an analog to digital converter, and more particularly to an analog to digital converter having high linearity.
2. Description of the Related Art
Consumers increasingly rely on digital resources provided by electronic devices such as cellular telephones, digital cameras, or portable and handheld digital electronic devices. The electronic devices process and/or produce both digital and analog signals. Meanwhile, the demand for faster transmission of digital data is increasing, along with increasing demand for applications such as wireless networks, downloadable digital music devices, digital movie devices, and others.
Electronic devices require the receipt of analog signals, which are then converted to digital signals, referred to as analog to digital (A/D) conversion. The electronic devices include appropriate circuitry to perform the A/D conversion to perform digital signal processing.
The pipelined architecture for Analog-to-Digital Conversion (ADC) rely on the concept of simultaneous data sub-conversion in multiple stages in order to progressively refine the digital representation of an analog signal. There are two fundamental approaches to pipelined ADC: a switched-capacitor, and a switched-current approach. In both of the approaches, the ADC apparatus is negatively influenced when components employed during stages of the pipelined ADC are mismatched.
An embodiment of an analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds a dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.
Another embodiment of a video device is provided. The video device comprises an analog to digital converter and a display unit. The analog to digital converter converts a first analog signal to generate a digital signal. The display unit receives the digital signal to show a corresponding image. The analog to digital converter further comprises a dither signal generator, a first stage, an adder, a second stage and a digital error correction logic. The dither signal generator generates a dither signal. The first stage receives a first analog signal to generate a first digital signal and a second analog signal. The adder is coupled to the first stage to add a dither signal to the second analog signal to generate a third analog signal. The second stage receives the third analog signal to generate a second digital signal. The digital error correction logic receives and corrects the first digital signal and the second digital signal to generate the digital signal.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
By utilizing the dither voltage generator 13 and the adder 18, the linearity of the analog to digital converter 10 can be improved. Although, in
The front-end sample and hold amplifier 11 receives, samples and amplifies the input voltage Vin to generate a first voltage V1. It is noted that the front-end sample and hold amplifier 11 may not amplify the voltage Vin, and only sample the input voltage Vin, and the amplitude of the input voltage Vin is the same as the first voltage V1. The first stage 12 receives the first voltage V1 to generate a second voltage V2 and a first digital code. The first digital code is shown B1+r, wherein r indicates the error bit or redundant bit of the analog-to-digital conversion. In this embodiment, B1 may be one bit value or a plurality of bit values according to the design of the first stage 12. The adder 18 adds the second voltage V2 and the dither voltage Vd to generate a third voltage V3. The dither voltage Vd is generated by the dither voltage generator 13. In one embodiment, amplitude of the dither voltage is between −0.5 LSB and 0.5 LSB, wherein the LSB indicates the smallest sensing voltage of the analog to digital converter 10. In the embodiment, the dither voltage is generated according to a random noise or a white noise. In another embodiment, the dither voltage Vd is time-varied.
The second stage 14 receives the third voltage V3 to generate a second digital code shown as B2+r, and another voltage (not shown in
Please refer to
By utilizing the dither signal generator 513 and the adder 518, the linearity of the analog to digital converter 51 can be improved. Although, in
The front-end sample and hold amplifier 511 receives, samples and amplifies the input analog signal Sa to generate a first analog signal S1. It is noted that the front-end sample and hold amplifier 511 may not amplify the input analog signal Sa, and only sample the input analog signal Sa, and the amplitude of the input analog signal Sa is the same as the first analog signal S1. The first stage 12 receives the first analog signal S1 to generate a second analog signal S2 and a first digital signal. The first digital signal is shown as B1+r, wherein r indicates the error bit or redundant bit of the analog-to-digital conversion. In this embodiment, B1 may be one bit or a plurality of bit according to the design of the first stage 512. The adder 518 adds the second analog signal S2 and the dither signal Sd to generate a third analog signal S3. The dither signal Sd is generated by the dither signal generator 513. In one embodiment, the amplitude of the dither signal Sd is between −0.5 LSB and 0.5 LSB, wherein the LSB indicates the smallest sensing voltage of the analog to digital converter 51. In the embodiment, the dither signal Sd is generated according to a random noise or a white noise. In another embodiment, the dither signal Sd is time-varied.
The second stage 514 receives the third analog signal S3 to generate a second digital code shown as B2+r, and another analog signal (not shown in
For detailed architecture of the first stage 512 or the second stage 514 reference can be made to the drawing and description of
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. An analog to digital converter, comprising:
- a dither voltage generator to generate a dither voltage;
- a first stage receiving a first voltage to generate a first digital code and a second voltage;
- an adder, coupled to the first stage, to add a dither voltage to the second voltage to generate a third voltage;
- a second stage receiving the third voltage to generate a second digital code; and
- a digital error correction logic to receive and correct the first digital code and the second digital code to generate a digital code corresponding to the first voltage.
2. The converter as claimed in claim 1, further comprising:
- a delay unit to receive and delay the first digital code for a preset time period, and transmit the first digital code and the second digital code to the digital error correction logic after receiving the second digital code.
3. The converter as claimed in claim 2, wherein the preset time period is determined based on a generation time of the second digital code of the second stage.
4. The converter as claimed in claim 1, further comprising:
- a front-end sample and hold amplifier to receive and amply an input voltage to generate the first voltage.
5. The converter as claimed in claim 1, wherein the amplitude of the dither voltage is between −0.5 LSB and 0.5 LSB.
6. The converter as claimed in claim 1, wherein the dither voltage is generated according a white noise signal.
7. The converter as claimed in claim 5, wherein the dither voltage is a time-variable value.
8. The converter as claimed in claim 1, wherein the first stage comprising:
- a sub analog to digital convert receiving the first voltage to generate the first digital code; and
- a multiplying digital to analog converter to generate the second voltage.
9. The converter as claimed in claim 8, wherein the multiplying digital to analog converter further comprises:
- a sub digital to analog converter receiving the first digital code to generate a fourth voltage;
- a sample and hold unit to receive and output the first voltage;
- a subtractor to subtract the fourth voltage from the first voltage to generate a voltage difference; and
- an amplifier to amply the voltage difference to generate the second voltage.
10. A video device, comprising:
- an analog to digital converter to convert a first analog signal to a digital signal, comprising: a dither signal generator to generate a dither signal; a first stage receiving a first analog signal to generate a first digital signal and a second analog signal; an adder, coupled to the first stage, to add a dither signal to the second analog signal to generate a third analog signal; a second stage receiving the third analog signal to generate a second digital signal; and a digital error correction logic to receive and correct the first digital signal and the second digital signal to generate the digital signal; and
- a display unit receiving the digital signal to show a corresponding frame.
11. The device as claimed in claim 10, further comprising:
- a delay unit to receive and delay the first digital signal for a preset time period, and transmit the first digital signal and the second digital signal to the digital error correction logic after receiving the second digital signal.
12. The device as claimed in claim 10, wherein the preset time period is determined based on a generation time of the second digital signal of the second stage.
13. The device as claimed in claim 10, further comprising:
- a front-end sample and hold amplifier to receive and amply an input signal to generate the first analog signal.
14. The device as claimed in claim 10, wherein the amplitude of the dither signal is between −0.5 LSB and 0.5 LSB.
15. The device as claimed in claim 10, wherein the dither signal is generated according a white noise signal.
16. The device as claimed in claim 10, wherein the first stage comprising:
- a sub analog to digital convert receiving the first analog signal to generate the first digital code; and
- a multiplying digital to analog converter to generate the second analog signal.
17. The device as claimed in claim 16, wherein the multiplying digital to analog converter further comprises:
- a sub digital to analog converter receiving the first digital signal to generate a fourth analog signal;
- a sample and hold unit to receive and output the first analog signal;
- a subtractor to subtract the fourth analog signal from the first analog signal to generate a fifth analog signal; and
- an amplifier to amply the fifth analog signal to generate the second analog signal.
18. The device as claimed in claim 17, wherein the amplitude of the amplifier is determined according to the number of bits of the first digital signal.
Type: Application
Filed: May 8, 2009
Publication Date: Nov 11, 2010
Applicant: HIMAX MEDIA SOLUTIONS, INC. (Tainan County)
Inventor: Chih-Haur HUANG (Tainan County)
Application Number: 12/437,676
International Classification: H03M 1/20 (20060101); H03M 1/06 (20060101);