Abstract: A phase-shifted sampling circuit is described. The phase-shifted sampling circuit includes a primary sampler circuit, an ADC circuit, and an equalization circuit. The primary sampler circuit includes an analog signal input, a first signal path, and a second signal path. The equalization circuit includes a primary sampler equalizer sub-circuit. The primary sampler equalizer sub-circuit is configured to compensate a mismatch between a transfer function associated with the first signal path and a transfer function associated with the second signal path. Further, a method of determining filter coefficients of an equalization circuit of a phase-shifted sampling circuit is described.

Abstract: Embodiments disclosed herein may reduce or even eliminate spurs introduced into the signals during analog to digital or digital to analog conversions. The spurs may be introduced by components such as clocks of the converter circuits. In an analog to digital conversion, the input signal may be split into two parts: the first portion passing through a first analog to digital converter (ADC) and an inverted second portion passing through a second ADC. A digital subtractor may subtract the output of the second ADC from the output of the first ADC converter thereby reducing the spurs. In digital to analog conversion, a digital input is passed through a first digital to analog converter (DAC) and an inverted digital input is passed through a second DAC. The output of the second DAC is inverted and combined with the output of the first DAC to reduce the spurs.

Abstract: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Abstract: An exemplary random number generation system leverages the r includes at least one solar power panel of a solar power system, at least one sensor and a random number generator. The sensor senses one or more output parameters (e.g., voltage or current) from the solar power system and provides the sensed parameter to the random number generator, which uses the sensed parameter to generate a number that is truly random (i.e., is not deterministic). As an example, the random number generator may receive multiple samples of the measured parameter and generate a random number based on a difference of the multiple samples. If desired, the random number generator may include an algorithm to remove biasing in the random number.

Abstract: A digital-to-analog conversion device which performs integration processing for integrating a difference between an input signal and a first return signal generated based on the input signal, and outputting an integration result, first quantization processing for quantizing the integration result, and outputting a first quantization signal, first return signal output processing for outputting the first return signal by adding to the first quantization signal a correction value delay signal acquired by a correction value signal outputted based on the integration result being delayed, and output processing for outputting output signals including a signal whose pulse width is asymmetrical to center of a processing period, based on the first quantization signal, in which the correction value signal includes a signal indicating a correction value for correcting a difference between a center of the pulse width asymmetrical to the center of the processing period and the center of the processing period.

Abstract: A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering comprises: a first DAC; an auxiliary code generator configured to produce an auxiliary code; an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and summing circuitry to dither LSBs of the first DAC with the auxiliary code. The auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

Abstract: A synchronization detection device includes: a correction unit configured to correct sampled data of a waveform on which a dither signal is superimposed, for each period of a reference signal in accordance with a period of the dither signal; a multiplication unit configured to multiply the corrected sampled data by a weight coefficient that is different for each level of the reference signal and associated with a timing of the reference signal; and an averaging unit configured to derive, as a detection result, an average of a result of the multiplication of the corrected sampled data by the weight coefficient.

Abstract: Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.

Abstract: Computations in Artificial neural networks (ANNs) are accomplished using simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. Crossbar arrays may be used to represent one layer of the ANN with Non-Volatile Memory (NVM) elements at each crosspoint, where the conductance of the NVM elements may be used to encode the synaptic weights, and a highly parallel current summation on the array achieves a weighted sum operation that is representative of the values of the output neurons. A method is outlined to transfer such neuron values from the outputs of one array to the inputs of a second array with no need for global clock synchronization, irrespective of the distances between the arrays, and to use such values at the next array, and/or to convert such values into digital bits at the next array.

Abstract: Disclosed is an electronic device which includes an audio processing block for voice recognition in a low-power mode. The electronic device includes a digital microphone that receives a voice signal from a user and converts the received voice signal into a PDM signal, and a DMIC interface circuit. The DMIC interface circuit includes a PDM-PCM converting block that converts the PDM signal into a PCM signal, a maxscale gain tuning block that tunes a maxscale gain of the PCM signal received from the PDM-PCM converting block based on a distance information indicating a physical distance between the user and the electronic device acquired in advance of the converting of the PDM signal, and an anti-aliasing block that performs filtering for acquiring voice data of a target frequency band associated with a PCM signal output from the maxscale gain tuning block.

Abstract: Improved dither detection, measurement, and voltage bias adjustments for an electro-optical modulator are described. The electro-optical modulator generally includes RF electrodes and phase heaters interfaced with semi-conductor waveguides on the arms of Mach-Zehnder interferometers, where a processor is connected to output a bias tuning voltage to the electro-optical modulator for controlling optical modulation. A variable gain amplifier (VGA) can be configured with AC coupling connected to receive a signal from a transimpediance amplifier (TIA) that is configured to amply a photodetector signal from an optical tap that is used to measure an optical signal with a dither signal. The analog to digital converter (ADC) can be connected to receive output from the VGA. The processor can be connected to receive the signal from the ADC and to output the bias tuning voltage based on evaluation of the signal from the tap.

Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

Abstract: Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

Abstract: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Abstract: An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.

Abstract: Techniques to implement subtractive dither in a multi-stage ADC. Subtractive dither involves adding a first dither signal at a first node and adding a second dither signal at a second node (which can be the same as the first node), where the first and second dither signal combine and sum to approximately zero. By utilizing subtractive dither in a multi-stage ADC, the headroom requirements of a loop filter in a main loop of the ADC and the range requirements of a feedback DAC in the main loop can both be relaxed.

Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

Abstract: A signal processor is provided, comprising a data variable delay circuit that delays data signals, a clock variable delay circuit that delays a clock signal indicating timing to acquire the data signals, a jitter signal supplying unit that supplies, to the data variable delay circuit and the clock variable delay circuit, a jitter signal to change an amount of delay in a same direction, and a re-timing circuit that outputs a jitter-applied data signal obtained by re-timing the data signals delayed by the data variable delay circuit with the clock signal delayed by the clock variable delay circuit.

Abstract: There is provided a temperature measurement apparatus that differentiates temperature-measurement resolutions and temperature-calculation accuracies in accordance with the difference of the temperature-measurement range so as to make it possible to universalize temperature-calculation processing among two or more models having different temperature-measurement ranges. In a temperature measurement apparatus, for respective identifiers indicating models of an A/D conversion circuit, a temperature calculation circuit stores corresponding polynomials whose powers and the coefficients of the powers are different from one another, and calculates a temperature by use of the polynomial having the powers and the coefficients of the powers corresponding to the identifier for the A/D conversion circuit that is actually provided.

Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

Abstract: A multi-stage analog-to-digital converter includes a signal input terminal, a first stage analog-to-digital converter, a digital-to-analog converter; a second stage analog-to-digital converter, and dither circuitry. The first stage analog-to-digital converter includes an input coupled to the signal input terminal. The digital-to-analog converter includes an input coupled to an output of the first stage analog-to-digital converter, and an input coupled to the signal input terminal. The second stage analog-to-digital converter includes a first input coupled to an output of the digital-to-analog converter. The dither circuitry is coupled to a second input of the second stage analog-to-digital converter, and is configured to provide a dither signal to the second stage analog-to-digital converter during selection of fewer than all bits of a digital value of a residue signal received from the digital-to-analog converter.

Abstract: Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

Abstract: The present disclosure relates to a method for demodulating a frequency modulated signal of a PMA standard wireless charging device, including: (1) reading coil signals, sampling the coil signals, and counting cycles; (2) extracting a frequency change according to a change in a cycle count; (3) determining data according to the frequency change and a frequency duration and outputting the data; and (4) splicing the outputted data. With the method, a demodulation part does not require a complex analog circuit, and the highest frequency desired at a digital circuit part is only 4 MHz. Moreover, at this frequency, there is only a simple addition operation, and the main operating frequency is below 236 KHz.

Abstract: The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.

Abstract: An apparatus for measuring a measured variable, wherein a first inductance and at least one measurement inductance are coupled, and wherein dithering is used to increase accuracy.

Abstract: A digital-to-analog converter (DAC) for an audio system in a media device, such as a portable media device or smart phone, may be operated to turn off portions of the DAC to reduce power consumption. Segments of a segment-able DAC may be powered off when the output level of the DAC is lower than the full scale output of the DAC. For example, DAC elements within a finite impulse response (FIR) DAC may be turned off when a desired output level can be obtained with less than all DAC elements of the FIR DAC.

Abstract: An analog-to-digital converter has first and second comparators and an interpolation comparator. The first comparator receives an input signal and a comparison signal, and generates an output as a function of the input signal and the comparison signal. The second comparator receives the input signal and a second comparison signal (different from the first comparison signal), and generates a second output as a function of the input signal and the second comparison signal. The interpolation comparator, operatively connected to the first and second comparators, receives the first and second outputs, and generates a third output based on relative timing of the first and second outputs.

Abstract: An electronic device may include an electronic display to display an image, based in part on display image data that indicates target luminance of the image using a first bit-depth, and a display pipeline. The display pipeline may include dither processing circuitry to determine a pixel cluster of multiple pixel groups of input image data that indicates target luminance using a second bit-depth greater than the first bit-depth. The dither processing circuitry may also determine a phase combination which associates a different dither phase to each of the pixel groups. The dither processing circuitry may also determine and apply a dither pattern and a dither phase to each pixel group to generate dithered image data corresponding with the display image data with the first bit-depth. The dither pattern may be based in part on the least significant bits of input image data of the pixel groups.

Abstract: System and method for beamspace nonlinear equalization in a plurality of parallel channels includes: receiving M parallel signals for transmission by N channels, respectively, wherein M is an integer greater than or equal to 1 and N is an integer greater than 1; performing a linear transfer function on each of the M parallel signal by a finite impulse response (FIR) filter; adding FIR filter tap outputs to each M parallel signals, respectively; phase shifting an output of a respective FIR filter per each of the M parallel signals to generate M intermediate channelized output signals per each of the N channels; summing, by a single summer, the M intermediate channelized output signals across the N channels to produce M channelized polyphase output signals; serializing the M channelized polyphase output signals to generate serialized M polyphase output signals; and equalizing the serialized M polyphase output signals to produce a linearized signal in beamspace.

Abstract: Improvements in analog-to-digital converter (ADC) circuit accuracy are described that can utilize a digital-to-analog converter (DAC) circuit with one or more redundant unit elements, or one or more bits redundancy or non-binary weighted capacitors, and can reuse the existing DAC circuit for noise reduction to save power and die area. An ADC circuit can use redundancy bit(s), e.g., one or more DAC unit elements of a main DAC, and the remaining lower bits of the main DAC for repeated bit trials, and can average the data from the repeated bit trials to suppress noise from conversions.

Abstract: In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

Abstract: A speech recognition system includes a phone classifier and a boundary classifier. The phone classifier generates combined boundary posteriors from a combination of auditory attention features and phone posteriors by feeding phone posteriors of neighboring frames of an audio signal into a machine learning algorithm to classify phone posterior context information. The boundary classifier estimates boundaries in speech contained in the audio signal from the combined boundary posteriors.

Abstract: A method and system for data conversion includes an analog noise generator to generate a random, non-deterministic, analog noise signal. An adder adds the analog noise signal to an analog RF signal to produce a dithered analog signal. A first quantizer converts the analog noise signal to digital to produce a digital noise signal. A second quantizer converts the dithered analog signal to a digital equivalent signal. A digital dither adjustment module removes amplitude measurements of the digital noise signal from the digital equivalent signal to obtain a linearized digital representation of the analog RF signal.

Abstract: An interface circuit in an electronic device may receive samples of wireless signals in one or more time intervals, where the wireless signals are associated with the second electronic device. For example, the samples of the wireless signals may include one or more of: time samples, spatial samples and/or frequency samples. Then, the interface circuit may split the samples of the wireless signals into parallel channels for sub-band processing that improves a resolution and/or a signal-to-noise ratio of the samples of the wireless signals. The sub-band processing may include filtering and decimation. Moreover, the sub-band processing may include a super-resolution technique, such as a multiple signal classification (MUSIC) technique and/or a linear-prediction super-resolution technique. Next, the interface circuit may combine outputs from the parallel channels to estimate a time of arrival of the wireless signals and/or a distance between the electronic device and the second electronic device.

Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract: Disclosed are a multi-carrier superposition method and device. First, input carrier signals are superposed, and gain reduction processing is conducted during the superposition process, and then CFR processing and increase processing are conducted on the superposed carrier signals. Thus, under the circumstance of multi-carrier superposition, it can be effectively ensured that signals cannot overflow, and meanwhile the requirement for precision of a system during processing is met.

Abstract: This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (SPWM) where the pulse-width modulated signal is synchronized to a first clock signal (CLK1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (SPWM) at a first node (304) based on the input signal (SIN) and a feedback signal (SFB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronized to the first clock signal (CLK1).

Abstract: According to some examples, systems and methods are provided for voltage sampling using one or more analog-to-digital converters (ADCs) to sense divided portions of a sampled voltage (e.g., of an output signal), using the one or more analog-to-digital converters to provide a plurality of digital values representative of those divided portions, and combining the plurality of digital values to produce a total digital value representative of the sampled voltage. Such systems and methods can achieve a high resolution for the total digital value while permitting use of ADCs that have a resolution lower than would otherwise be required to achieve the high resolution.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

Abstract: Devices and methods for digital to analog conversion (DAC) are provided, in which the analog outputs of an even number of digital to analog converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analog outputs are subtracted. Dither and filtering techniques may also be employed.

Abstract: An example capacitive digital-to-analog converter (CDAC) includes: a first plurality of capacitors consisting of M?1 capacitors, where M is an integer greater than one, the first plurality of capacitors including top plates coupled to a first node; a second plurality of capacitors consisting of M?1 capacitors, the second plurality of capacitors including top plates coupled to a second node; a first plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the first plurality of capacitors, the first plurality of switches further coupled to a third node providing a supply voltage and a fourth node providing a ground voltage; a second plurality of switches consisting of M?1 switches coupled to bottom plates of the respective M?1 capacitors of the second plurality of capacitors, the second plurality of switches coupled to the third node and the fourth node; and a control circuit including an input consisting of M bits for receiving an M bit code and an output c

Abstract: The present disclosure relates to a compressive encoding apparatus, a compressive encoding method, a decoding apparatus, a decoding method, and a program which can provide a lossless compression technology having a higher compression rate. An encoding unit of the compressive encoding apparatus converts M bits of a ??-modulated digital signal into N bits (M>N) with reference to a first conversion table, and when the M bits are not able to be converted into the N bits with the first conversion table, converts the M bits into the N bits with reference to a second conversion table. When the number of bit patterns of the N bits is P, the first conversion table is a table storing (P?1) number of codes having higher generation frequencies for past bit patterns, and the second conversion table is a table storing (P?1) number of codes having higher generation frequencies for past bit patterns, which follow those of the first conversion table.

Abstract: The present disclosure relates to a method and system for tone signal removal from a noisy signal that includes a desired signal in combination with the tone signal. The method and system provides an artificial or estimated undesired tone signal with the same frequency as the undesired tone signal, which, in combination with an estimated phasor, is available to filter or subtract a noisy component from the noisy signal and to provide the filtered or clean desired signal.

Abstract: A system and method of converting an analog input signal to a linearized digital representation of the analog input signal. A measure of the analog input signal is compared to a threshold associated with a maximum dynamic range of a quantizer. A maximum amplitude of a random, analog dither signal is dynamically varied for perturbing quantization of the analog input signal in response to the comparison. The dynamically varied dither signal and the analog input signal are combined to obtain a dithered input signal. The quantizer converts the dithered input signal into the linearized digital representation of the analog input signal.

Abstract: A system and method of converting an analog input signal to a digital output signal includes coupling an analog input signal to a plurality of analog-to-digital converters (ADCs) arranged in a parallel configuration. Pseudo-random discrete valued complementary offset voltage levels that span an input voltage range of the sum of the plurality of ADCs are generated. An amount of continuous, analog dither that randomly varies at values between the discrete offset voltage levels is generated, the analog dither being less than steps between the discrete offset voltage levels. On different clock cycles, different discrete offset voltage levels are coupled to at least some of the ADCs. At each ADC, the respectively coupled analog input, discrete offset voltage level, and continuous analog dither are quantized to obtain a digital output. The respective digital outputs are combined to obtain a linearized digital representation of the analog input signal.

Abstract: A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Abstract: According to an embodiment, a sensor circuit includes a sigma-delta analog to digital converter (ADC), a dithered clock coupled to the sigma-delta ADC, and a supply voltage circuit coupled to the sigma-delta ADC. The sigma-delta ADC is configured to be coupled to a low frequency transducer, and the dithered clock is configured to control of the sigma-delta ADC based on a dithered clock signal.

Abstract: An interleaved DAC configured to generate a set of second digital inputs responsive to a set of first digital inputs. Each second digital input is obtained by subtracting the other second digital inputs in the set from the corresponding first digital input. Two consecutive first digital inputs are shifted by a phase of T=1/fs. The second digital inputs are supplied to a set of sub-DACs arrange in parallel. Each sub-DAC operates at a frequency of fs/R, and drives an analog output responsive to each second digital input for a duration of R×T. Clock signals used by two sub-DACs for converting two consecutive second digital inputs are offset by a phase of T. In each interval of T, summation of the analog signals output from the set of sub-DACs produces an analog value of a single first digital input, thereby achieving a data conversion speed of fs.