Converter Compensation Patents (Class 341/118)
  • Patent number: 11128307
    Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: September 21, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rui Wang, Yu-Shen Yang, Shan Chen, Min Qu
  • Patent number: 11121717
    Abstract: An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: September 14, 2021
    Inventor: Masayoshi Todorokihara
  • Patent number: 11105836
    Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 31, 2021
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Dino Costanzo, Cheng Pan Cai, Xi Yu Xu
  • Patent number: 11101810
    Abstract: Analog to digital conversion errors caused by non-linearities or other sources of distortion in an analog-to-digital converter are compensated for by use of a machine learning system, such as a neural network. The machine learning system is trained based on simulation or measurement data, which utilizes a filtered output of the analog-to-digital converter that has less distortion errors than the unfiltered output of the analog-to-digital converter. The effect on the analog to digital conversion errors by Process-Voltage-Temperature parameters may be incorporated into the training of the machine learning system.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 24, 2021
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Patent number: 11095299
    Abstract: An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 17, 2021
    Assignee: SITRUS TECHNOLOGY CORPORATION
    Inventors: Michael Q. Le, Mrunmay Talegaonkar
  • Patent number: 11090431
    Abstract: To detect air in a fluid delivery line of an infusion system, infusion fluid is pumped through a fluid delivery line adjacent to at least one sensor. A signal is transmitted and received using the at least one sensor into and from the fluid delivery line. The at least one sensor is operated, using at least one processor, at a modified frequency which is different than a resonant frequency of the at least one sensor to reduce an amplitude of an output of the signal transmitted from the at least one sensor to a level which is lower than a saturation level of the analog-to-digital converter to avoid over-saturating the analog-to-digital converter. The signal received by the at least one sensor is converted from analog to digital using an analog-to-digital converter. The at least one processor determines whether air is in the fluid delivery line based on the converted digital signal.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 17, 2021
    Assignee: ICU Medical, Inc.
    Inventors: John Hicks Dumas, III, Paul T. Kotnik, Kunal Sur, Anatoly S. Belkin, Timothy L. Ruchti
  • Patent number: 11082057
    Abstract: An apparatus such as an electronic circuit includes an input operable to receive an input signal; a dynamic common mode adjustor operable to: i) derive a differential signal from the received input signal, and ii) control an offset of the differential signal as a function of the received input signal to produce an offset differential signal; and an output operable to output the offset differential signal. In one arrangement, the offset differential signal outputted from the output includes a first signal and a second signal; a difference between the second signal and the first signal proportionally varies with respect to the received input signal.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Holm Hansen, Mikkel Hoyerby
  • Patent number: 11082058
    Abstract: The present disclosure addresses a concept for capacitor scaling. A first capacitor is provided with a first signal capacitance between a first electrode and a second electrode of the first capacitor and with a first parasitic capacitance between the first capacitor's first electrode and AC ground. A sum of the first signal capacitance and the first parasitic capacitance yields a first total capacitance. A second capacitor is provided with a second signal capacitance between a first electrode and a second electrode of the second capacitor and with a second parasitic capacitance between the second capacitor's first electrode and AC ground. A sum of the second signal capacitance and the second parasitic capacitance yields a second total capacitance. While the first signal capacitance differs from the second signal capacitance, the first total capacitance equals the second total capacitance.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 3, 2021
    Assignee: Apple Inc.
    Inventors: Davide Ponton, Antonio Passamani
  • Patent number: 11075641
    Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 27, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Ting-Hao Wang
  • Patent number: 11073951
    Abstract: A mobile device has a proximity sensor. A compensation value of the proximity sensor is determined. The compensation value is compared to a reference compensation value to determine validity of the compensation value. A capacitance of the proximity sensor is measured. A value of the capacitance of the proximity sensor is adjusted based on the compensation value. A coefficient defining a relationship between a capacitance of the proximity sensor and a temperature of the mobile device is calculated. A temperature sensor is coupled to the proximity sensor. The temperature of the mobile device is measured. A value of the capacitance of the proximity sensor is adjusted based on the coefficient and the temperature of the mobile device. The adjusted capacitance value is compared to a threshold capacitance value to determine proximity of an object to the mobile device. A radio frequency signal is adjusted by detecting proximity.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: July 27, 2021
    Assignee: Semtech Corporation
    Inventors: Chaouki Rouaissia, Jerald G. Ott, III
  • Patent number: 11075643
    Abstract: Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: July 27, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Jialin Zhao, Hajime Shibata, Hao Luo
  • Patent number: 11075617
    Abstract: A DC-removing cascaded integrator-comb (CIC) filter circuit (40) includes N series-coupled integrator stages (401-405), a rate changer (406), and N series-coupled comb stages (407-411) which are configured to receive a CIC filter digital input signal and to generate a CIC filter digital output signal, wherein the N integrator stages include a first integrator stage (401) which includes a summation element (41) having first input for receiving a first input signal, a second input for receiving a second input signal, and an output coupled through a feedback delay element (42) to a multiplier element (43) which multiplies a DC-removing filter coefficient with an output of the feedback delay element to generate a product output that is provided to the second input of the summation element (41), thereby embedding a DC-removing filter in the N series-coupled integrator stages.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 27, 2021
    Assignee: NXP USA, Inc.
    Inventor: Sammy Johnatan Carbajal Ipenza
  • Patent number: 11075644
    Abstract: A method is described that is performed by a calibration system. The method includes determining a set of perturbation values for configuring an analog-to-digital converter of the calibration system; generating a set of digital test values for determining the accuracy of the analog-to-digital converter; and applying the set of perturbation values to the set of digital test values to generate a set of modified test values, wherein the set of perturbation values are digital values that are applied to the set of digital test values in the digital domain.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: July 27, 2021
    Assignee: NEWRACOM, Inc.
    Inventors: Ryunwoo Kim, Seungyun Lee, Jaeyoung Ryu, Jeongki Choi, Jonghoon Park, Changhun Song
  • Patent number: 11054877
    Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Dorit Shapira, Anand K. Enamandram, Daniel Cartagena, Krishnakanth Sistla, Jorge P. Rodriguez, Efraim Rotem, Nir Rosenzweig
  • Patent number: 11050431
    Abstract: A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 29, 2021
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Chao-Hsien Ma, Soon-Jyh Chang, Hao-Sheng Wu
  • Patent number: 11043956
    Abstract: An analog-to-digital converting system includes multiple stages of analog-to-digital converters (ADCs) and a skew calibration circuit. The multiple stages of ADCs are configured to sample a test signal according to multiple interleaved clock signals, respectively, so as to respectively generate multiple stages of quantized outputs. The analog-to-digital converting system has a sampling frequency resulting from operations of the multiple stages of ADCs. The test signal has a first frequency and the sampling frequency is N times the first frequency, and N is an odd number larger than 1. The skew calibration circuit is configured to sequentially analysis, for every N stages, the multiple stages of quantized outputs to generate multiple digital codes. The skew calibration circuit is further configured to calibrate a time skew of the analog-to-digital converting system according to a comparison result between the multiple digital codes and a reference code.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 22, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Hua Wan, Ting-Hao Wang, Yu-Chu Chen
  • Patent number: 11038522
    Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: June 15, 2021
    Assignee: NXP B.V.
    Inventors: Johan Frederik Witte, Lucien Johannes Breems, Robert Rutten, Muhammed Bolatkale, Johannes Hubertus Antonius Brekelmans, Shagun Bajoria, Albertus Willibrordus Oude Essink
  • Patent number: 11032501
    Abstract: An image sensing system and methods for operating the same are disclosed. An image sensing system includes a plurality of pixel circuits, a multiplexer configured to select one of the pixel circuit and provide analog pixel data without sampling, and a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the analog pixel data into digital data. The SAR ADC includes a capacitive digital-to-analog converter (CDAC) configured to convert contents of the SAR into a corresponding analog signal for comparison, by a comparator, with the analog pixel data. The CDAC includes a two-dimensional array of circuit elements. A control circuit in the image sensing system is configured to cause random ones of the circuit elements of the CDAC to be selected for generation of the corresponding analog signal and add a dithering signal so a CDAC output and shuffle a multiplexer switch sequence to improve fixed pattern noise.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 8, 2021
    Assignee: Apple Inc.
    Inventors: Dusan Stepanovic, Sedigheh Hashemi, Mansour Keramat, Hyunsik Park
  • Patent number: 11031947
    Abstract: An RF receiver including: a low noise amplifier adapted to be coupled to an antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit including: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
  • Patent number: 11025262
    Abstract: The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to ?1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 1, 2021
    Inventors: Yuanjun Cen, Xing Zhu, Jinda Yang
  • Patent number: 11018679
    Abstract: An integrated circuit includes an on-chip PLL response measurement capability. The PLL response is determined in terms of PLL bandwidth and PLL peaking. A digital phase offset is inserted to a digital representation of a first clock signal to create a phase step. A phase and frequency detector of a phase-locked loop (PLL) supplies a phase error signal indicative of a difference between the first clock signal and a second clock signal. The elapsed time between the phase step insertion and the first zero crossing of the phase error as the PLL tries to deal with the is used to determine PLL bandwidth. The maximum phase error overshoot resulting from insertion of the digital phase offset is determined for use in determining PLL peaking.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 25, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Kannanthodath V. Jayakumar
  • Patent number: 11005469
    Abstract: A method of controlling a comparator includes during a first time period, enabling an auto-zero loop to provide an initial offset calibration of a differential preamplifier that includes differential memory capacitors; and during a second time period after the first window, enabling a self-calibrating circuit to provide an offset calibration of the differential preamplifier, and minimizing an output offset of a dynamic latch. Wherein the dynamic latch is configured to latch an output of the differential preamplifier at a sampling frequency, the auto-zero loop including an auxiliary amplifier configured to inject a correction signal into the differential preamplifier based on a voltage across the differential memory capacitors, and the self-calibrating circuit including a charge pump configured to adjust the voltage across the differential memory capacitors based on an output of the dynamic latch.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 11, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Sayyed Mahdi Kashmiri, Rainer Blechschmidt
  • Patent number: 10979066
    Abstract: The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 13, 2021
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Zhengbo Huang, Ting Li, Yong Zhang, Ruzhang Li, Guangbing Chen, Yabo Ni
  • Patent number: 10979064
    Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Martin Kinyua
  • Patent number: 10979061
    Abstract: An analog-to-digital conversion device includes: a switch connected to input units through signal lines to receive external voltages selecting and outputting one external voltage; an S/H circuit holding a voltage corresponding to an output of the switch; a converter performing AD conversion based on the voltage; and a controller determining the external voltage selected by the switch and performing a disconnection determination whether a disconnection occurs in the signal line. In the disconnection determination, the controller controls the switch to select a reference voltage different from the external voltage before controlling the switch to select the external voltage to be determined, and performs the disconnection determination based on a voltage difference between the reference voltage and the external voltage after controlling the switch to select the external voltage.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 13, 2021
    Assignee: DENSO CORPORATION
    Inventor: Yusuke Shibata
  • Patent number: 10972119
    Abstract: An analog-to-digital converter (ADC) including input circuitry to receive an input analog signal having an analog signal level. Sampling circuitry couples to the input circuitry and includes first and second capacitor circuits to sample the received input analog signal. The first and second capacitor circuits exhibit a relative charge imbalance as a result of the sampling that corresponds to the analog signal level. Regulated charge sharing circuitry regulates charge sharing transfers during multiple charge sharing transfer sequences with the first and second capacitor circuits. A digital output generates multiple bit values based on the charge sharing transfer sequences.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 6, 2021
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Alan Fredenburg, Yuxiang Mu, Noman Hai
  • Patent number: 10965310
    Abstract: A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Meghna Agrawal
  • Patent number: 10965299
    Abstract: A digital-to-analog converter (DAC) includes a current array having a plurality of unit cells in a plurality of rows and a plurality of columns, an arbitrary switch box and processing circuitry configured to randomly select a subset of rows among the plurality of rows based on a plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells, randomly select one row among the plurality of rows based on a plurality of second row selection signals, select a subset of columns among the plurality of columns based on column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and generate an analog output signal corresponding to a digital input signal based on the first unit cells and the second unit cells.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungho Kim, Michael Choi, Byungwoo Koo, Hyungdong Roh, Sunghan Do, Youngjae Cho
  • Patent number: 10958285
    Abstract: A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: March 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bradford Lawrence Hunter, Xiaopeng Li
  • Patent number: 10948933
    Abstract: A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gautam Salil Nandi, Mit Bhattacharya
  • Patent number: 10944414
    Abstract: An apparatus and method for sampling an analog signal with analog-to-digital converters (ADCs) is disclosed. The ADCs may be separated into a group of interleaved ADCs and a spare ADC. The interleaved ADCs can sample the analog signal according to an interleaving sequence. An interleaved ADC controller can monitor the inactivity of the spare ADC and can replace one of the interleaved ADCs in the interleaving sequence with the spare ADC based on the inactivity.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 9, 2021
    Assignee: Xilinx, Inc.
    Inventors: Bruno Miguel Vaz, Bob W. Verbruggen, Christophe Erdmann
  • Patent number: 10938397
    Abstract: Examples of recording channels and methods for biopotential signal acquisition and/or recording are described. Recording channels described herein may implement any combination of techniques described herein including multiplexing of multiple electrode inputs, delta encoding of biopotential signals, and common mode suppression.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 2, 2021
    Assignee: University of Washington
    Inventors: William Anthony Smith, Visvesh Sathe
  • Patent number: 10938362
    Abstract: Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (211), each path respectively comprising, an input terminal (221), an output terminal (231), a node (241) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND).
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Mohsen Naghed
  • Patent number: 10931297
    Abstract: A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 23, 2021
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 10921164
    Abstract: A MEMS sensor generates an output multiscale reading signal supplied to a full scale adjustment stage. The full scale adjustment stage includes a signal input configured to receive the reading signal, a saturation assessment block, and a full scale change block. The saturation assessment block is coupled to the signal input and configured to generate a scale increase request signal upon detection of a saturation condition. The full scale change block is coupled to the saturation assessment block and configured to generate a full scale change signal upon reception of the scale increase request signal.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Matteo Quartiroli
  • Patent number: 10897264
    Abstract: An analog signal processing module includes a processor and a comparator circuit module having a comparator circuit input and a comparator circuit output, the comparator circuit module being configured to receive a first analog signal at the comparator circuit input and generate a digital output, wherein the comparator circuit output is connected to the processor. A digital-to-analog converter (DAC) module is configured to receive a digital output from the processor and convert the digital output to a second analog signal. An operational amplifier (OpAmp) circuit module has an OpAmp circuit input and an OpAmp circuit output, the OpAmp circuit module being configured to receive the second analog signal at the OpAMp circuit input. A feedback loop is formed by the processor, the DAC module, and the OpAMp circuit module, and is configured to implement an amplification function or attenuation function performed by the OpAmp circuit module.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 19, 2021
    Assignee: BOOZ ALLEN HAMILTON INC.
    Inventor: Keith A. Blanks
  • Patent number: 10897262
    Abstract: Methods and apparatus for determining non-linearity in analog-to-digital converters are disclosed. An example apparatus includes a signal interface to receive an output of an analog-to-digital converter (ADC), the output corresponding to a periodic signal transmitted to the ADC; a signal transformer to determine at least one of a harmonic phase or a harmonic amplitude corresponding to the output; and an integral non-linearity (INL) term calculator to determine the INL of the ADC based on a characteristic of the periodic signal and the at least one of the harmonic phase or the harmonic amplitude.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akhilesh Kesavanunnithan, Sharat Chandra Rudrasamudram, Henry Manoj D'Souza, Vivek Varier
  • Patent number: 10892769
    Abstract: A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 12, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Stefan Wlodzimierz Wiktor, Brian Thomas Lynch
  • Patent number: 10886937
    Abstract: Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: January 5, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Abhishek Bandyopadhyay, Akira Shikata, Keith Anthony O'Donoghue
  • Patent number: 10873341
    Abstract: The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 22, 2020
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Xiaofeng Guo, Haigang Feng, Jon Sweat Duster, Yulin Tan, Ning Zhang
  • Patent number: 10873336
    Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 22, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Ahmed Mohamed Abdelatty Ali, Frank Murden, Peter Delos, Ralph D. Moore
  • Patent number: 10868550
    Abstract: A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayawardan Janardhanan, Christopher Andrew Schell, Sinjeet Dhanvantray Parekh
  • Patent number: 10862501
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: December 8, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10848169
    Abstract: Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. To meet high performance requirements, the input circuitry is typically implemented with power hungry circuitry in a different semiconductor technology from the analog-to-digital converter that the input circuitry is driving. With suitable optimization techniques, performance requirements on the input circuitry can be reduced while meeting target performance of the receiver signal chain. Specifically, optimization techniques can compensate for input frequency-dependent properties and/or amplitude-dependent properties of the input circuitry. In some cases, reducing performance requirements on the input circuitry means that the input circuitry can be implemented in the same semiconductor technology as the analog-to-digital converter.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 24, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Gabriele Manganaro, Nevena Rakuljic
  • Patent number: 10840931
    Abstract: A digital-to-analog converter (DAC) is described having a digital input, an analogue output, and two capacitors. The DAC has a controller. The controller is configured to generate a switching sequence including at least two switch cycles dependent on the input value received on the digital input. If the input value corresponds to an odd number, in a first switch cycle during a switch cycle first phase, the controller switchably couples a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couples a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors. During a switch cycle second phase, the controller switchably couples a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 17, 2020
    Assignee: NXP B.V.
    Inventor: Xavier Albinet
  • Patent number: 10840935
    Abstract: A passive conjunction circuit for an analog-to-digital converter (ADC) is disclosed. In one aspect, the passive conjunction circuit includes a first input node receiving an analog input signal to be converted by the ADC and a second input node receiving a reference voltage other than a ground voltage of the ADC. The passive conjunction circuit also includes a first output node to be connected to a first differential input of the ADC (20) and a second output node to be connected to a second differential input of the ADC. The passive conjunction circuit further includes a first voltage divider interconnected between the first input and output nodes and a second voltage divider interconnected between the second input and output nodes.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 17, 2020
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Juergen Fritz, Thomas Korherr
  • Patent number: 10840891
    Abstract: An apparatus performs interpolation/decimation in a digital circuit that receives an input signal and includes upsampling/downsampling and filtering stages. First and second paths include distinct first and second portions of the upsampling/downsampling and filtering stages. The first path consumes less quiescent state power. A selection circuit uses the first or second path and turns off the unused first or second path based on input signal spectral content or level. A mode includes applying a front-end digital/analog gain and a corresponding back-end analog/digital attenuation in conjunction with the first path being used and the second path being turned off. A cross-fader uses the first and second paths in a weighted mix manner while making a transition between using the first and second paths. The second path has higher filtering performance (e.g., superior stopband attenuation, passband ripple, transition band, e.g., via higher order or greater bit-width filtering).
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: November 17, 2020
    Inventors: Aniruddha Satoskar, John L. Melanson, Siva Venkata Subbarao Bonasu
  • Patent number: 10833689
    Abstract: The present invention corresponds to a method and a circuit for compensating the offset voltage of electronic circuits, where the circuit implementing the method comprises: a dynamic comparator (1); a phase detector (6) connected to the dynamic comparator (1), the phase detector (6); a finite-state machine (9) connected to the phase detector (4), a first digital-analog converter (12) connected to an output of the finite-state machine (9); a second digital-analog converter (13) connected to another output (11) of the finite-state machine (9); a polarization block (14) with a first input (15) connected to the output of the first digital-analog converter (12) and a second input (16) connected to the output of the second digital-analog converter (13); where the polarization block (14) polarizes an electronic circuit (17) and the dynamic comparator (1), the phase detector (6), and the finite-state machine (9) are connected to a clock signal (3).
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 10, 2020
    Assignee: UNIVERSIDAD INDUSTRIAL DE SANTANDER
    Inventors: Andrés Felipe Amaya Beltrán, Rodolfo Villamizar Mejía, Élkim Felipe Roa Fuentes
  • Patent number: 10833690
    Abstract: An analog-to-digital converter (ADC) includes a comparator, a voltage reference circuit, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a plurality of capacitors. Each of the capacitors of the first CDAC includes a top plate coupled to a first input of the comparator, and a bottom plate switchably coupled to an output of the voltage reference circuit. The second CDAC includes a plurality of capacitors. Each of the capacitors of the second CDAC includes a top plate coupled to a second input of the comparator, and a bottom plate switchably coupled to a ground reference.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yujendra Mitikiri, Minkle Eldho Paul, Anukruti Chakraborty
  • Patent number: 10826513
    Abstract: An analog to digital converter includes a coarse ADC circuit composed of L offset-adjustable comparators and a fine ADC circuit composed of M offset-adjustable comparators. Each offset-adjustable comparator in the coarse ADC circuit has a constant embedded offset. Each offset-adjustable comparator in the fine ADC circuit has an adaptive embedded offset digitally determined by outputs of the coarse ADC circuit. With the constant and adaptive embedded offsets, the analog to digital converter requires no resistor ladder. Therefore, power consumption and area of the analog to digital converter is reduced, and faster conversion speed is achieved.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 3, 2020
    Assignee: National Cheng Kung University
    Inventors: Chung-Ming Yang, Tai-Haur Kuo