Abstract: A calibration system includes a jitter-capturing analog-to-digital converter (ADC), a calibration value generating circuit and a first calculation circuit. The jitter-capturing ADC is configured to sample a to-be-sampled clock signal according to an operating clock signal to generate a first quantized output. The calibration value generating circuit is configured to receive the first quantized output and a second quantized output of a to-be-calibrated ADC to generate a calibration value. The operating clock signal is for driving the to-be-calibrated ADC to sample, and the calibration value is related to a phase noise of the operating clock signal. The first calculation circuit is coupled with the calibration value generating circuit, and configured to subtract the calibration value from the second quantized output to generate a third quantized output.

Abstract: A semiconductor device includes an analog-to-digital converter configured to perform a process of sampling an analog input signal and a successive-approximation process, execute an AD conversion process, and output a digital output signal. The AD converter includes an upper DAC, a redundant DAC, a lower DAC, a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC, a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on the comparison result of the comparator, and generate a digital output signal, and a correction circuit. The correction circuit includes an error correction circuit configured to correct an error of the upper bit with the redundant bit, and an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.

Abstract: A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.

Abstract: Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

Abstract: A sensor interface circuit includes a continuous-time capacitance-to-voltage (C/V) converter having C/V input and output ends, the C/V input end being configured for electrical connection with first and second sense nodes of a capacitive sensor. A filter circuit is electrically coupled to the C/V output ends. The filter circuit has first and second resistors at corresponding first and second filter input ends of the filter circuit, a capacitor connected between first and second filter output ends of the filter circuit, and a chopper circuit interposed between the first and second filter input ends and the first and second filter output ends. A buffer circuit is electrically coupled with the first and second filter output ends of the filter circuit. The filter circuit applies low pass filtering of sense signals from the capacitive sensor before sampling and demodulation operations to reduce high-frequency interference in the sense signals.

Abstract: The present disclosure relates to a constant current source calibration circuit, a constant current source drive circuit, a drive chip, and an electronic device. The current calibration circuit includes a resistor and a calibration circuit connected to the resistor for adjusting a voltage drop across two ends of the resistor; and a selector or a switch connected to the two ends of the resistor, and configured to select one end of the resistor to be connected to a constant current source output channel and the corresponding other end to be supplied with a first bias voltage VD. Since the first bias voltage VD is a fixed constant, the voltage drop across the two ends of the resistor is adjusted.

Abstract: A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate an analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.

Abstract: Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

Abstract: In some implementations, a magnetic sensor may apply an electrical signal across a tunnel barrier layer of a tunnel magnetoresistive (TMR) sensing element. The electrical signal may have a first signal level during a first time period and a second signal level during a second time period. The second signal level may be different from the first signal level. The magnetic sensor may generate an offset-corrected sensor signal based on a sensor signal that results from applying the electrical signal across the tunnel barrier layer of the TMR sensing element.

Abstract: An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules.

Abstract: A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

Abstract: An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.

Abstract: A current test circuit can include a sampling resister array with a control end connected with a main control component, a first end is connected with a power conversion circuit, and a second end configured to be connected with a component to be tested. The sampling resistor array includes at least two sampling branches, each having an analog switch and a sampling resistor connected serially. In the test, the main control component can generate a control signal according to the operating state of the component and gate at least one sampling branch of the sampling resistor array through the control signal, obtain voltage values at two ends of the sampling resistor array through a voltage test assembly, and determine the current of the component according to the voltage values at two ends of the sampling resistor array and resistance values of the sampling resistor array.

Abstract: A physical quantity detection circuit includes: an analog/digital conversion circuit performing analog/digital conversion processing on an analog signal based on an output signal from a physical quantity detection element and outputting a first digital signal; a digital arithmetic circuit having the first digital signal inputted thereto, performing arithmetic processing on the first digital signal, and outputting a second digital signal; and a regulator circuit supplying a power-supply voltage to the analog/digital conversion circuit and the digital arithmetic circuit. The digital arithmetic circuit does not perform an arithmetic processing start operation to start the arithmetic processing and an arithmetic processing end operation to end the arithmetic processing, during an analog/digital conversion period when the analog/digital conversion is performed.

Abstract: An analog-to-digital converting device includes N-stage first analog-to-digital converters (ADCs), a second ADC, a first calibration circuit, a data recovery circuit and an output circuit. The N-stage first ADCs has a first sampling frequency that is (N+1)/N times of a second sampling frequency, and converts an input signal into first quantized outputs. The second ADC has the second sampling frequency, and converts the input signal into a second quantized output. The first calibration circuit calibrates offsets of the first quantized outputs and the second quantized output to generate third quantized outputs and a fourth quantized output. The data recovery circuit outputs, by the second sampling frequency, one of the third quantized outputs as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate output data. The output circuit generates an output signal according to the third quantized outputs and the output data.

Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

Abstract: Examples of clock generators with very low duty cycle distortion (DCD) are provided. A clock source and driver generate a main clock signal and a complementary clock signal that are input to a chopper circuit, which also receives complementary chopper control signals from a non-overlapping generator circuit. The chopper circuit is controlled to pass the main clock signal as a first output signal when the chopper circuit is in a first state, and pass the complementary clock signal as a second output signal when the chopper circuit is in a third state. In a second state, which occurs during each of the falling edges of the main clock signal, the chopper circuit holds the previous state, and does not transmit the falling edges of the main clock signal. The rising edges of the main clock signal is used to derive the rising and falling edges of the output signals.

Abstract: An AD converter includes: an integration unit that uses an input voltage as an initial value and repeats an operation of integrating one or both of two types of unit voltages with the input voltage, thereby generating an integrated voltage; a switching threshold voltage unit that includes two types of threshold voltages causing the operation of integrating to be terminated; a comparator that compares the integrated voltage with the threshold voltages; an integration determination unit that, before the operation of integrating is started, causes the comparator to compare the input voltage with a rough adjustment threshold voltage corresponding to a larger one of the unit voltages; a unit voltage switching control unit that, when the rough adjustment threshold voltage is larger than the input voltage, controls the integration unit to generate the integrated voltage by using the two types of unit voltages; and a single unit voltage control unit that, when the rough adjustment threshold voltage is smaller than th

Abstract: The concept described herein relates to a device and a method for determining the transfer function of an angle sensor in the course of operation. For this purpose, a sequence of angle output signals of the angle sensor is received during at least one time interval in which the angle sensor is exposed to a rotating magnetic field. Furthermore, the transfer function of the angle sensor is determined on the basis of the sequence of angle output signals. The method can be carried out during regular operation of the angle sensor.

Abstract: An analog-to-digital (ADC) converter system and method of using the system that can be used in low power situations. The converter can periodically or recurrently turn off a reference standard in order to conserve power and instead using a stable supply source as a reference voltage. A precise conversion for signal from the analog to the digital domain while maintaining a low quiescent current.

Abstract: This document describes techniques and apparatuses directed at detecting and preventing light-based injection attacks. In aspects, a computing device includes executable instructions of an input manager, an audio sensor having subtracting circuitry, and a light sensor. One or more processors executing instructions of the input manager is configured to receive and analyze signals generated by the audio sensor, the light sensor, and the subtracting circuit. Upon analysis, the input manager can detect and prevent light-based injection attacks.

Abstract: A failure determination device: acquires a second digital value indicating a difference between an analog electrical output generated by inputting a first digital value incremented at a first time interval to a DA conversion circuit and a target output indicated by the first digital value at a second time interval; and determines whether the DA conversion circuit has a failure based on a signal strength in a predetermined frequency of the second digital value that is a discrete signal.

Abstract: An ADC device includes a DAC circuit, a comparator circuit, a SAR decision circuit, an oscillator circuit having a delay unit, and a processing circuit. The oscillator circuit is used for generating the clock signal according to a reset signal and a delay of the delay unit. The processing circuit is used for sequentially generating multiple bit conversion signals associated with multiple different bits of the decision signal, for generating at least one guard signal which follows the multiple bit conversion signals, and then for comparing the at least one guard signal with the reset signal to adjust the delay generated by the delay unit of the oscillator circuit.

Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Abstract: A biopotential measurement device includes: a branching section that branches a biopotential into plural analog potentials; a first conversion section that converts one of the analog potentials branched by the branching section into a digital potential on the basis of a designated first conversion condition; and a second conversion section that converts the other of the analog potentials branched by the branching section into a digital potential on the basis of a second conversion condition. The amount of data obtained after a conversion with the second conversion condition is smaller than the amount of data obtained after a conversion with the first conversion condition.

Abstract: A circuit for measuring an unknown resistance of a resistive element comprises a sensor circuit to generate a differential voltage dependent on the resistance of the resistive element and a reference circuit to generate a differential reference voltage and a sigma-delta converter comprising a first stage, wherein a first capacitor is selectively coupled to one of the output terminals of the sensor circuit and a second capacitor is coupled to one of the output terminals of the reference circuit. The circuit generates logarithmically compressed values.

Abstract: An integrated circuit includes a capacitance element to be tested and a test circuit in the same semiconductor substrate, the test circuit includes a capacitance element for testing, and a comparison circuit for comparing a voltage of a node with a voltage of a signal, electrically connects another end of the capacitance element to be tested to the node, applies the voltage of the signal to the node in a first period, changes the voltage of the node based on a capacitance ratio of the capacitance element to be tested and the capacitance element for testing, and tests a capacity size of the capacitance element to be tested based on a comparison result of the comparison circuit in a second period after the first period.

Abstract: Embodiments included herein generally relate to managing low frequencies of an output signal. For example, a method may include: measuring a sound pressure level (SPL) of a speaker; dynamically selecting a cutoff frequency for operating a first filter configured to provide a first bass component of a bass element of an output signal and a second filter configured to provide a second bass component of the bass element; providing the cutoff frequency to the first filter to configure the first filter to generate the first bass component based on the cutoff frequency; providing the cutoff frequency to the second filter to configure the second filter to generate the second bass component based on the cutoff frequency; and generating an output signal based on at least one of the first and second bass components.

Abstract: An integrated circuit connectable to a sensor includes a transconductance element and a current-input analog-to-digital converter (I-ADC). The transconductance element is connectable to the sensor and is configured to generate a current signal representative of an output of the sensor. The I-ADC is configured to sample and quantize the current signal to generate a corresponding digital sensor signal. The I-ADC includes a continuous-time (CT) integrator stage, a discrete-time (DT) integrator stage, and a feedback digital-to-analog converter (FB-DAC). The CT integrator stage is configured to receive the current output and the I-ADC is configured to generate the digital sensor signal based on an output of the CT integrator stage and an output of the DT integrator stage. The FB-DAC is configured to provide a feedback signal based on the digital sensor signal for adding to the current signal.

Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.

Abstract: A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2(K+1) steps, each of which has a value equal to an integer multiplying 2(?K) of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2(K+1) number of N-bit digital signals based on the at least 2(K+1) steps of the digitally controlled offset voltage, summing the at least the 2(K+1) number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

Abstract: The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

Abstract: In accordance with the present invention a system and method for calibration of the current steering DAC is elaborated which helps to reduce design complexity and reduce silicon area required in the design. Present invention is utilising a clocked comparator and plurality of switch transistors 405,305 and AUX DAC in conjunction with digital estimator and digital compensator blocks to estimate the errors in the current sources 406 and compensate the errors using same AUX DAC during normal operation mode.

Abstract: A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

Abstract: Analog calibration (ACAL) circuits supporting iterative measurement of an input signal from a measured circuit, and related methods are disclosed. The ACAL circuit includes a voltage reference generation circuit and a comparator circuit. The voltage reference generation circuit is configured to provide an input reference voltage. The comparator circuit is configured to compare the input reference voltage to an input circuit voltage of a measured circuit and generate a digital measurement signal based on the comparison. To provide for the ACAL circuit to more precisely measure the input circuit voltage, the voltage reference generation circuit is programmable and is configured to a generate the input reference voltage based on a programmed reference voltage selection. In this manner, the ACAL circuit can be used to measure the input circuit voltage in an iterative manner based on different programmed input reference voltages for a more precise measurement of the input circuit voltage.

Abstract: An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Abstract: An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.

Abstract: An image sensor includes: a pixel outputting a pixel signal; a ramp voltage generation circuit suitable for generating a ramp voltage that changes at a first slope in a first section and generating the ramp voltage that changes at a second slope having a greater absolute value than the first slope in a second section following the first section; an operation amplifier suitable for comparing the pixel signal with the ramp voltage during the first section and the second section; and a counter circuit suitable for generating a digital code corresponding to the pixel signal in response to an output of the operation amplifier.

Abstract: A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

Abstract: An apparatus includes a plurality of signal processing stages configured to convert a digital baseband signal into an analog radio frequency signal for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one signal processing stage of the plurality of signal processing stages is configured to generate an analog voltage signal which comprises a voltage level that is outside of a voltage range defined by the positive supply voltage and the negative supply voltage.

Abstract: The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC) A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

Abstract: The present invention provides a wide-area sample-based reader design which serves as a diagnostic detection device for bio-particles.

Abstract: An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

Abstract: A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.

Abstract: An A/D conversion circuit includes a comparison-reference-signal generator section configured to generate a comparison reference signal synchronized with a sampling clock signal, a comparator configured to compare a voltage of an input signal and a voltage of the comparison reference signal to thereby generate a trigger signal, a time to digital converter configured to calculate a first time digital value, and a digital-signal generator section configured to generate, based on the first time digital value and a second time digital value, a digital signal corresponding to the voltage of the input signal.

Abstract: A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.