Converter Compensation Patents (Class 341/118)
  • Patent number: 10411726
    Abstract: A quantizer includes: a quantizer capacitor having a first end and a second end; an input calculator that receives input voltages, sums the input voltages, and outputs the summed result to the first end of the quantizer capacitor; a scaler that receives reference voltages and a scale code, generates a scale voltage from the reference voltages depending on the scale code, and outputs the scale voltage to the second end of the quantizer capacitor; and a latch that stores an output voltage of the first end of the quantizer capacitor.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Woo Kim, Dai Shi, Eun Seok Shin
  • Patent number: 10403225
    Abstract: A display apparatus and a driving method for the display apparatus are provided. The display apparatus includes a display panel and a first source driver. The display panel has a pixel array. The first source driver sequentially supplies a first overdrive voltage and a driving voltage to a pixel in the pixel array. The first overdrive voltage has a plurality of voltage levels according to positions of pixels in the pixel array.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 3, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Li-Tang Lin, Keko-Chun Liang
  • Patent number: 10402166
    Abstract: Various aspects of a system and method to process data in an adder based circuit, such as an integrated circuit, are disclosed herein. In accordance with an embodiment, a first addend is encoded as a first unary number. The first unary number comprises a token bit. A second addend is encoded as a second unary number. A first shift operation is performed on the token bit in the first unary number based on the second unary number. The first shift operation is performed to generate an output unary number. The generated output unary number is decoded to a number representation that corresponds to the number representation of the first addend and/or the second addend. The decoded number representation indicates a summation of the first addend and the second addend.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 3, 2019
    Assignee: SONY CORPORATION
    Inventors: Jeremy Chatwin, Jacob Adams Wysocki
  • Patent number: 10402354
    Abstract: The disclosure provides a method for determining link delay. The method includes: according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and, according to the second LMFC, writing respectively the data of each data lane into a corresponding buffer; and according to a SYSREF signal and a preset LMFC interval, generating a third LMFC, and, according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer. The period of the second LMFC is the same as the period of the third LMFC. The disclosure also provides an apparatus, a communication device and a storage medium for implementing the method.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: September 3, 2019
    Assignee: Sanechips Technology Co., Ltd.
    Inventors: Lining Yang, Peng Hao, Can Huang
  • Patent number: 10401608
    Abstract: An image acquisition apparatus including: a stage on which a specimen is mounted; an objective lens that collects light from the specimen; a stage driving part that drives the stage; an image capturing unit that acquires an image by photographing the light collected by the objective lens; an image-generating unit that generates a pasted image by pasting the captured image acquired by the image capturing unit; a storage unit that stores the pasted image; a color-difference calculating unit that calculates a degree of dissimilarity between a color of the pasted image and a color of the captured image prior to pasting; and a color-difference correcting unit that corrects the color of the captured image so as to match the color of the pasted image, on the basis of the calculated degree of dissimilarity.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: September 3, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Masayuki Nakatsuka
  • Patent number: 10393800
    Abstract: The invention relates to a circuit arrangement comprising a control device, an input circuit for applying an input signal, a conditioning circuit electrically connected to the input circuit for converting the input signal into a measured signal, an analog-to-digital converter electrically connected to the conditioning circuit for converting the measured signal into a digital value, and a reference source that outputs a known reference signal. In this respect, a first switching apparatus is provided that selectively separate the input signal from the conditioning circuit or supplies it to the conditioning circuit and a second switching apparatus is provided that selectively supplies the reference signal to the input circuit or separates it from the input circuit, wherein the control device is configured to determine an offset error and to determine a gain error of the circuit arrangement.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: August 27, 2019
    Assignee: SICK AG
    Inventor: Igor Bogomolni
  • Patent number: 10374731
    Abstract: An over-the-air measurement system for testing the over-the-air characteristics of a device under test is described, comprising several antenna units for receiving and transmitting radio frequency signals, several remote radio units that convert radio frequency signals into digital signals or vice versa, and a baseband unit for generating and analyzing baseband signals. The baseband unit is connected to the remote radio units, the baseband unit having at least one physical layer control unit that is configured to adapt the over-the-air measurement system with regard to the physical layer. The several antenna units are connected to the remote radio units. Further, a method for testing the over-the-air characteristics of a device under test is described.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Corbett Rowell, Vincent Abadie, Daniel Markert, Adam Tankielun
  • Patent number: 10371573
    Abstract: A method to measure and report electromagnetic radiation power includes receiving electromagnetic radiation and generating an electrical signal having a magnitude based on the power of the electromagnetic radiation. An adjustable gain may be applied to the electrical signal to generate an amplified electrical signal that may be sampled to generate a digital sample. The adjustable gain may be controlled based on the value of the digital sample and the digital sample may be associated with a gain value. One or more calibration factors may be selected based on the gain value associated with the digital sample and the selected calibration factor(s) may be used to calculate the power of the electromagnetic radiation.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: August 6, 2019
    Assignee: FINISAR CORPORATION
    Inventor: Lucy G. Hosking
  • Patent number: 10374622
    Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 6, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Zhang
  • Patent number: 10367515
    Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 30, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Gaurav Chandra, Tao Zeng, Shantha Murthy Prem Swaroop, Jianyu Zhu
  • Patent number: 10355704
    Abstract: Amplifier circuitry has sampling circuitry which samples an input voltage, a quantizer which quantizes an output voltage of the sampling circuitry and outputs an output code, a differential amplifier which amplifies a differential voltage between the output voltage of the sampling circuitry and a reference voltage and performs offset adjustment according to the output code of the quantizer, and a first capacitor which is connected between an output node of the differential amplifier and an output node of the sampling circuitry.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Yoshioka, Tetsuro Itakura
  • Patent number: 10355655
    Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Chakravartula Nallani, Georgios Asmanis, Faouzi Chaahoub, Alfred Sargezisardrud, Tony Shuo-Chun Kao
  • Patent number: 10340932
    Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 2, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Abhishek Bandyopadhyay, Dan Boyko, Eric G. Nestler
  • Patent number: 10338185
    Abstract: A method for calibrating a test instrument having an initial output voltage level and an open output relay can include programming the test instrument for a certain current level, starting a timer, and stopping the timer (responsive to the test instrument entering compliance) to determine a time interval. The method can also include determining whether the time interval is within a desired range.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 2, 2019
    Assignee: Keithley Instruments, LLC
    Inventor: Martin J. Rice
  • Patent number: 10333538
    Abstract: The present disclosure is directed to a method and system for compensating mismatches among sub-converters in a time interleaved analog digital converter structure. A digital finite impulse response (FIR) equalization filtering unit is coupled to outputs of the sub-converters. The FIR filtering unit includes a digital FIR filter dedicated to each sub-converter. The FIR filtering coefficient is adapted specifically for each sub-converter to achieve a compensation for sub-converter mismatches and inter-symbol interference (ISI) equalization.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 25, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Stefano Valle, Edoardo Lauri, Angelo Poloni
  • Patent number: 10333544
    Abstract: Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a DAC circuit includes multiple DAC stages, each of which may be configured to generate one or more DAC analog signals corresponding to selected resistances within the DAC stage. Each DAC stage is configured to receive a corresponding top and bottom voltage. Each DAC stage is configured to generate a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, as well as on the selected resistance of the DAC stage. Each DAC stage includes an adjusting circuit comprising a resistance configured to adjust a resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjusting circuit and a resistance of a next DAC stage is maintained at an ideal resistance level.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Burt Lee Price
  • Patent number: 10330710
    Abstract: The present disclosure provides a power management apparatus of a vehicle and a method of controlling the same, for determining whether a power circuit of a vehicle controller is abnormal. The power management apparatus includes a battery, a battery sensor configured to acquire voltage information of the battery, and a controller configured to receive the voltage information of the battery, to compare a second voltage and a third voltage with preset reference information, and to determine whether power is abnormal, wherein a first voltage is measured by the controller, the second voltage is adjusted by converting the first voltage into a digital signal, and the third voltage is measured by the battery sensor.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 25, 2019
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Woo Kuen Kim, Jin Gu Kwon, Myoung Soo Park
  • Patent number: 10326463
    Abstract: Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Hao Liu, Yongjian Tang
  • Patent number: 10312925
    Abstract: This invention discloses a multiplying digital-to-analog converter (MDAC) applied to a pipelined analog-to-digital converter (pipelined ADC). The MDAC includes an operational amplifier. The MDAC samples a differential input signal in a sampling phase and performs subtraction and multiplication operations in an amplification phase according to a first reference voltage and a second reference voltage. The common-mode voltage of the first reference voltage and the second reference voltage is not substantially equal to the common-mode voltage of the differential input signal; and/or the voltage difference between the first reference voltage and the second reference voltage is not substantially equal to one half of an allowed maximum peak-to-peak value of the differential input signal. One of the first reference voltage and the second reference voltage can be ground.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 4, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Lung Chen, Ying-Cheng Wu, Shih-Hsiung Huang
  • Patent number: 10312932
    Abstract: The resolution of a successive approximation analog-to-digital converter is varied in a wide range. Provided is a successive approximation analog-to-digital converter including a digital-to-analog converter that generates an analog voltage based on a digital code, a comparator to which the analog voltage as the output of the digital-to-analog converter is inputted, a DAC control circuit that generates the digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on the output of the comparator, a delay circuit that starts the determination of the comparator by signal transition generated by delaying the signal state change of the output of the comparator, a clock generation circuit that generates a signal starting the determination of the comparator, and a selector circuit that selects a signal generated by the delay circuit or a signal generated by the clock generation circuit to feed the selected signal to the comparator.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: June 4, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yohei Nakamura, Taizo Yamawaki
  • Patent number: 10295383
    Abstract: A measuring amplifier (103) with background calibration and adjustment amplifies, digitizes and processes at least one measurement signal (111) from at least one measuring transducer (102) with the aid of at least one amplifier arrangement (108). This can be intermittently replaced by an additional amplifier arrangement (107), which enables interruption-free direct calibration and, if necessary, adjustment of the amplifier arrangement. In the calibration, both a zero point error and an amplification error of the amplifier arrangement are reliably determined. A high accuracy is achieved without measurement interruption. Only one additional amplifier arrangement is generally required, even for a measuring amplifier with plural channels.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 21, 2019
    Assignee: Hottinger Baldwin Messtechnik GmbH
    Inventors: Marco M. Schaeck, Herbert Kitzing
  • Patent number: 10298250
    Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) that has a configurable capacitor array. Based on measurements of differential nonlinearity (DNL) and/or integral nonlinearity (INL) error by an external test computer system, an order for use of the DAC's capacitors can be determined so as to reduce DNL error aggregation, also called INL. The DAC includes a switch matrix that can be programmed by programming data supplied by the test computer system.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 21, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Fuchs, Rudiger Kuhn, Bernhard Wolfgang Ruck
  • Patent number: 10298248
    Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 21, 2019
    Assignee: XILINX, INC.
    Inventors: Bruno Miguel Vaz, Christophe Erdmann, Bob W. Verbruggen, John E. McGrath, Ali Boumaalif
  • Patent number: 10298246
    Abstract: Methods and systems are provided for circuits. One method is for increasing device threshold voltage distribution of a plurality of devices of a circuit. The method includes adjusting a device threshold voltage of the plurality of devices by different amounts; and selecting a subset of the plurality of devices with adjusted device threshold voltage by a device selection module for performing a function associated with the circuit. In one aspect, a system for device threshold voltage adjustment is provided. The system includes a sensor module for sensing one or more of temperature and voltage values of a die having a plurality of devices for a circuit; and a threshold temperature and voltage compensation module for receiving an input value from the sensor module to compensate variation in a device threshold voltage caused by changes of one or more of temperature and voltage of the die.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 21, 2019
    Inventor: Frank R. Dropps
  • Patent number: 10292111
    Abstract: A gain control circuit in a wireless distribution system (WDS) is provided. The gain control circuit generates a combined digital communications signal based on a number of received radio frequency (RF) communications signals. The combined digital communications signal has a digital amplitude(s) representing a summed analog power level(s) of the RF communications signals in a predefined number of binary bits. When the summed analog power level(s) exceeds a maximum analog power level represented by the digital amplitude(s) in the predefined number of binary bits, the gain control circuit determines a selected RF communications signal(s) causing the summed analog power level to exceed the maximum analog power level and attenuates the selected RF communications signal(s) to reduce the summed analog power level to below the maximum analog power level. As such, it is possible to achieve a calculated balance between performance, complexity, and cost in the gain control circuit.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 14, 2019
    Assignee: Corning Optical Communications LLC
    Inventor: Dror Harel
  • Patent number: 10291439
    Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
  • Patent number: 10291252
    Abstract: An ADC, including a DAC which receives an analog input voltage and a digital input word from SAR logic, and generates a first voltage based on the analog input voltage and the digital word. The ADC also includes a comparator, which receives the first voltage and a reference voltage, and generates a second voltage based on the first voltage and on the reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The ADC also includes the SAR logic circuit which receives the second voltage from the comparator. The SAR logic generates a digital output word based on a second voltages received from the comparator. A difference between the minimum input voltage on the maximum input voltage is substantially equal to two times a difference between reference voltage and the minimum input voltage.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 14, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Mohamed Aboudina, Hassan Elwan
  • Patent number: 10284216
    Abstract: A calibration circuit and calibration method for a successive approximation register analog-to-digital converter (SAR ADC) are disclosed. The SAR ADC includes a comparator and generates a digital code. The calibration method includes the following steps: (a) creating a voltage difference between two inputs of the comparator, with the absolute value of the voltage difference being smaller than or equal to the absolute value of the voltage corresponding to the least significant bit (LSB) of the digital code; (b) updating a count value according to whether a timer of the SAR ADC issues a time-out signal, the timer issuing the time-out signal after a delay time has elapsed; (c) repeating steps (a) through (b) a predetermined number of times; (d) calculating a probability based on the predetermined number of times and the count value; and (e) adjusting the delay time according to the probability.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 7, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kuo-Sheng Chung, Shih-Hsiung Huang, Jie-Fan Lai
  • Patent number: 10284802
    Abstract: A system and method is provided for image sensing. The image sensing system includes a comparator for comparing an input signal representing a sensed light signal from at least one pixel of the image sensing system and a reference signal. The comparator includes at least one digital transistor.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 7, 2019
    Assignee: Cista System Corp.
    Inventor: Guangbin Zhang
  • Patent number: 10284219
    Abstract: A comparator includes a first input stage coupled to a first signal input and a first reference input, wherein the first input stage is coupled between a first node and a second node. A second input stage is coupled to a second signal input and a second reference input, wherein the second input stage is coupled between a third node and the second node. An output stage generates at least one output signal in response to the first and second input signals. First switching circuitry is coupled between the first node and the output stage. The first switching circuitry is for coupling the first node to a fourth node in response to a reset signal. Second switching circuitry is coupled between the third node and the output stage. The second switching circuitry is for coupling the third node to a fifth node in response to the reset signal.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rishi Soundararajan
  • Patent number: 10277245
    Abstract: A digital to analog converter circuit, a display panel and a display device are provided. The digital to analog converter circuit includes a voltage dividing unit, a first segmenting unit, a second segmenting unit and a third segmenting unit.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 30, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Tangxiang Wang
  • Patent number: 10277210
    Abstract: A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Hyo Gyuem Rhew, Adesh Garg, Meisam Honarvar Nazari, Jiawen Zhang, Ali Nazemi, Jun Cao
  • Patent number: 10277843
    Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: April 30, 2019
    Assignee: Rambus Inc.
    Inventors: Craig M. Smith, Michael Guidash, Jay Endsley, Thomas Vogelsang, James E. Harris
  • Patent number: 10256784
    Abstract: A system and method for setting analog front end in a serial receiver. The serial receiver includes a decision feedback equalizer. During initialization, taps of the decision feedback equalizer other than the zeroth tap are disabled, and the zeroth tap is used to estimate the amplitude of the signal at the output of the analog front end. The analog front end gain is iteratively adjusted until the estimated value of the zeroth tap is within a set range.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gaurav Malhotra, Amir Amirkhany
  • Patent number: 10256832
    Abstract: A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 9, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Noriyuki Murashima
  • Patent number: 10256824
    Abstract: A D/A converter includes a decoder, a voltage selection circuit, and a voltage selection circuit. The voltage selection circuit includes a plurality of stages of selector blocks in which output of a selector of the selector block at the previous stage is input to a selector of the selector block at the subsequent stage. A plurality of voltages are input to the selector block at the first stage, and the selector block at the final stage outputs a D/A-converted voltage. Each of the plurality of stages of selector blocks includes a plurality of transistors and, of the plurality of transistors forming the selector block, a second transistor on a far side from a power source node is set to a lower threshold voltage than that of a first transistor on a near side from the power source node.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 9, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Shigenori Isozaki
  • Patent number: 10256831
    Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 9, 2019
    Assignee: Analog Devices Global
    Inventors: Sandeep Monangi, Mahesh Madhavan
  • Patent number: 10250273
    Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Texas Instruments Incorporation
    Inventors: Sthanunathan Ramakrishnan, Sashidharan Venkatraman, Chandrasekhar Sriram, Jawaharlal Tangudu
  • Patent number: 10250208
    Abstract: A circuit for amplifying signals from a Micro Electro-Mechanical System (MEMS) capacitive sensor is provided. First and second input nodes receive a sensing signal applied differentially between the input nodes. A first amplifier stage and a second amplifier stage, respectively, produce a differential output signal between first and second output nodes. A common mode signal is detected at the output nodes. A voltage divider having an intermediate tap node is coupled between the first output node and the second output node. A feedback stage is coupled between the tap node of the voltage divider and the inputs of the first amplifier stage and the second amplifier stage, where the feedback line is sensitive to the common mode signal at the output nodes.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 2, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Edoardo Marino
  • Patent number: 10250277
    Abstract: The present invention relates to a successive approximation register (SAR)-type analog-digital converter (ADC), which can amplify a residual voltage without a non-linearity problem caused by an output voltage of a residual voltage amplifier, thereby performing high-resolution analog-digital conversion at low power consumption.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 2, 2019
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae Yoon Sim, Seungnam Choi
  • Patent number: 10236901
    Abstract: A circuit for asynchronous clock generation is described. The circuit comprises a first comparator configured to receive an analog input signal; a second comparator configured to receive the analog input signal; and a clocking circuit coupled to the first comparator and the second comparator; wherein the clocking circuit generates a first asynchronous clock signal for the first comparator and a second asynchronous clock signal for the second comparator. A method of providing asynchronous clock generation is also described.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 19, 2019
    Assignee: XILINX, INC.
    Inventor: Pedro W. Neto
  • Patent number: 10236902
    Abstract: An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuitry. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: March 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shridhar More, Rahul Vijay Kulkarni
  • Patent number: 10236903
    Abstract: A charge compensation circuit for use in an analog-to-digital converter (ADC) includes at least one capacitor and at least one logic circuit. A first terminal of the capacitor is coupled to a reference voltage of the analog-to-digital converter. The logic circuit is configured to adjust a voltage at a second terminal of the capacitor according to a control signal. The control signal is determined according to at least one output bit from the analog-to-digital converter.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 19, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ying-Zu Lin, Rong-Sing Chu
  • Patent number: 10224946
    Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: March 5, 2019
    Assignee: MAXLINEAR, INC.
    Inventors: Gaurav Chandra, Tao Zeng, Shantha Murthy Prem Swaroop
  • Patent number: 10223483
    Abstract: A methodology for defining resistance-capacitance (RC) design targets based on radio-frequency (RF) simulation is provided. In particular, the method may involve first determining capacitance targets and then determining resistance targets. To compute the capacitance targets, integrate circuit design and simulations tools may run transient analysis to identify critical nodes, perform small signal and sensitivity analysis for the capacitance on the critical nodes, revise original RF specifications by allocating additional margin, and perform interpolation among multiple capacitance values to obtain capacitive design targets that meet the revised specifications.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Tat Hin Tan, William Walter Fergusson, Chieu Fung Tan
  • Patent number: 10225070
    Abstract: A method for processing a digital audio broadcast signal in a radio receiver, includes: receiving a hybrid broadcast signal; demodulating the hybrid broadcast signal to produce an analog audio stream and a digital audio stream; and using a normalized cross-correlation of envelopes of the analog audio stream and the digital audio stream to measure a time offset between the analog audio stream and the digital audio stream. The time offset can be used to align the analog audio stream and the digital audio stream for subsequent blending of an output of the radio receiver from the analog audio stream to the digital audio stream or from the digital audio stream to the analog audio stream.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 5, 2019
    Assignee: Ibiquity Digital Corporation
    Inventors: Brian W. Kroeger, Paul J. Peyla
  • Patent number: 10218373
    Abstract: An ADC calibration system includes a clock generating circuit, under test ADCs, a standard ADC, and a calibration circuit. The clock generating circuit generates operation clocks according to a system clock, and generates a calibration clock according to the system clock and a selection signal. The under test ADCs sample an input signal according to the operation clocks to output under test sampling results. The standard ADC samples the input signal according to the calibration clock to output a standard sampling result. The calibration circuit makes the phases of the calibration clock and a first operation clock received by a first ADC to be the same. The calibration circuit compares the standard sampling result with a first under test sampling result to generate calibration information corresponding to the first under test sampling result, and calibrates the first under test sampling result according to the calibration information.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 26, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Hao Wang, Shih-Chun Lo
  • Patent number: 10204666
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 12, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shuichi Tsukada
  • Patent number: 10200041
    Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Analog Devices Global
    Inventors: Jeremy R. Gorbold, Christian Steffen Birk, Gerard Mora Puchalt, Colin Charles Price, Michael C. W. Coln, Mahesh Madhavan Kumbaranthodiyil
  • Patent number: 10193564
    Abstract: A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: January 29, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Zhenyong Zhang