DIGITAL-TO-ANALOG CONVERTER (DAC) WITH REFERENCE-ROTATED DAC ELEMENTS
In accordance with at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated data weighted averaging (RRDWA) is applied to the DAC element array.
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Digital-to-analog converters (DACs) are implemented in many electronic devices. The process of outputting an analog signal that corresponds to a digital input relies on imperfect components. Accordingly, DAC design often accounts for such imperfections. As an example, oversampling and Dynamic Element Matching (DEM) are two techniques that may be used improve DAC performance. DEM refers to selecting different DAC elements to represent a given digital code at different times, thereby translating element mismatches (DC error) into a wideband high-pass-shaped noise. The shaped mismatch noise which resides at high frequency can then be filtered out. Data-weighted averaging (DWA) is a practical DEM technique albeit still imperfect. In DWA, DAC elements participating in digital-to-analog conversion are sequentially selected from a DAC array, beginning with the next available unused DAC element. Several variations of DWA have been developed such as dithered DWA, incremental DWA (IDWA), bi-directional DWA (Bi-DWA), partitioned DWA (P-DWA), rotated DWA (RDWA), randomized DWA (RnDWA), and pseudo DWA. Although DWA techniques are effective for overcoming issues such as DAC element mismatches, existing DWA techniques do not overcome flicker noise in DAC elements. As transistor processes (e.g., complementary metal-oxide semiconductor (CMOS) processes) for DACs are reduced in size, flicker noise in DAC elements increases.
SUMMARYIn at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated data weighted averaging (RRDWA) is applied to the DAC element array.
In at least some embodiments, a digital-to-analog converter (DAC) comprises a plurality of DAC elements, wherein each DAC element is selectable as a reference element. The DAC further comprises element selection logic coupled to the plurality of DAC elements. The element selection logic rotates DAC elements selected as reference elements.
In at least some embodiments, a digital-to-analog converter (DAC) method comprises operating a plurality of DAC elements at a predetermined frequency. The DAC method further comprises rotatively selecting each of the plurality of DAC elements as a reference element.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
DETAILED DESCRIPTIONThe following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
Embodiments of the disclosure are directed to a reference-rotated data-weighted average (“RRDWA”) technique for overcoming flicker noise in DAC elements. As used herein, RRDWA refers to dynamically rotating, among a plurality of DAC elements, which DAC element (or elements) is used as a reference element. Accordingly, various features of the RRDWA concept are described herein. Further, an RRDWA simulation circuit and simulation results are provided.
As shown in
In at least some embodiments, the array index circuitry 206 provides a control signal to element selection logic 208 for dynamic rotation of DAC elements and REF elements in the DAC element array 108. In addition, the array index circuitry 206 may provide control signals to the element selection logic 208 for selection of DAC elements in the DAC element array 108 as positive output DAC elements or negative output DAC elements. The combined operation of the array index circuitry 206 and the element selection logic 208 correspond to the RRDWA algorithm 110 of
In accordance with various embodiments, the array index circuitry 206 and the element selection logic 208 may be implemented in different ways. The purpose of the array index circuitry 206 is to implement a reference element selection scheme that causes each DAC element in the DAC element array 108 to be selected as a reference element approximately equally during DAC operation. In at least some embodiments, the reference element selection scheme may be described as a plurality of sequential selection cycles, where each DAC element in the DAC element array 108 is selected once for each selection cycle. Once a selection cycle is complete, a new selection cycle begins. The selection pattern for each selection cycle may be either random or predetermined.
In at least some embodiments, the array index circuitry 206 models an index corresponding to the DAC elements of the DAC element array 108. The index model may be based on hardware, software, or a combination thereof. With the index model, the array index circuitry 206 is able to track reference element selection parameters such as which DAC elements were previously selected as a reference element for a given selection cycle, which DAC elements are currently selected as a reference element for the given selection cycle and/or which DAC elements have not yet been selected as a reference element for the given selection cycle. Based on a determination of such reference element selection parameters, the array index circuitry 206 outputs a control signal to the element selection logic 208, which may correspond to a switch array. In addition to dynamically selecting DAC elements of the DAC element array 108 as reference elements, the element selection logic 208 also causes each DAC element that is not selected as a reference element to be selected as either a positive output DAC element or a negative output DAC element. The selection of DAC elements as either a positive output DAC element or a negative output DAC element may be based on a control code received by the RRDWA DAC 200. The output (“d[n]”) of the RRDWA DAC 200 may be provided to a low-pass filter or other circuitry.
In
Another RRDWA feature is that the average noise for RRDWA, assuming a high reference amplifier bandwidth, is zero. In other words, RRDWA may be implemented to cancel flicker noise regardless of the bandwidth of the op amp 302. To prove this conclusion, assume selection of the 5 transistors of the DAC element array 306 as the reference element is rotated at a clock frequency of 6 MHz. Also, assume only one of the 5 transistors has noise. In such case, the noisy transistor is selected as the reference element 1 out of 5 times for each selection cycle. For the analysis, superposition may be used with the final result being multiplied by sqrt(5). Since the loop bandwidth is high (i.e., the loop bandwidth is much greater than 6 Mhz), the noise will be corrected upon selection of the noisy transistor as the reference element. Therefore, the gate of the noisy transistor will develop a voltage of −in/(Gm) when the noisy transistor is selected as the reference element and a voltage of 0 otherwise.
In
In
An analytical analysis of RRDWA further support the simulation results described herein. A noisy DAC element can be described as having two noise components. The first noise component is when the DAC element directs noise flow into the P output or M output. The second noise component is when the DAC element is part of the REF output by modulation of the gate voltage of the line after filtering by the unity gain frequency (UGF) of the REF amp (e.g., op amp blocks 402, 502, etc.). The first noise component can be modeled as in
Accordingly, the combined first and second noise components can be modeled as in
The method 700 may comprise additional steps that are added individually or in combination. As an example, the method 700 may additionally receiving a control code for each DAC operation cycle and causing DAC elements that are not selected as a reference element to provide a positive output or a negative output based on the control code.
In conclusion, simple DWA does not eliminate flicker noise of DAC elements. The flicker noise of a reference element for simple DWA does not result in a while noise floor for any signal amplitude. Meanwhile, the flicker noise of DAC elements for simple DWA results in a white noise floor for any signal amplitude. RRDWA operates to whiten flicker noise of DAC elements such that the flicker noise does not appear around the desired signal. The flicker noise whitening provided by RRDWA is independent of the REF amp bandwidth. Further, thermal noise in both RRDWA and simple DWA are substantially the same assuming the number of reference elements and DAC elements are equal.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims
1. An electronic device, comprising:
- a digital-to-analog converter (DAC) having a DAC element array, wherein reference-rotated data weighted averaging (RRDWA) is applied to the DAC element array;
- wherein said RRDWA whitens DAC element flicker noise into thermal noise levels and eliminates distortions due to DAC element mismatches.
2-7. (canceled)
8. A digital-to-analog converter (DAC), comprising:
- a plurality of DAC elements, wherein each DAC element is selectable as a reference element;
- element selection logic coupled to said DAC elements, wherein the element selection logic rotates DAC elements selected as reference elements; and
- wherein the element selection logic causes each DAC element that is not selected as a reference element to be selected as one of positive output DAC element and a negative output DAC element.
9. The DAC of claim 8 wherein the element selection logic implements a reference element selection scheme that causes each DAC element to be selected as a reference element approximately equally during DAC operation.
10. The DAC of claim 9 wherein the reference element selection scheme selects each DAC element as a reference element once for each of a plurality of selection cycles.
11. The DAC of claim 10 wherein a random selection pattern is implemented for each selection cycle.
12. The DAC of claim 10 wherein a predetermined selection pattern is implemented for each selection cycle.
13. (canceled)
14. The DAC of claim 8 wherein the element selection logic selects DAC elements as positive output DAC elements and negative output DAC elements based on a control code.
15. A digital-to-analog converter (DAC) method, comprising:
- operating a plurality of DAC elements at a predetermined frequency;
- rotatively selecting each of the plurality of DAC elements as a reference element; and
- receiving a control code for each DAC operation cycle and causing DAC elements that are not selected as a reference element to provide a positive output or a negative output based on the control code.
16. The DAC method of claim 15 wherein said rotatively selecting comprises selecting each of the plurality of DAC elements as a reference element approximately equally during DAC operation.
17. The DAC method of claim 15 wherein said rotatively selecting comprises selecting each DAC element as a reference element once for each of a plurality of selection cycles.
18. The DAC method of claim 17 further comprising implementing a random selection pattern is implemented for each selection cycle.
19. The DAC method of claim 17 further comprising implementing a predetermined selection pattern for each selection cycle.
20. (canceled)
Type: Application
Filed: Oct 5, 2009
Publication Date: Apr 7, 2011
Applicant: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventor: Ganesh K. BALACHANDRAN (Irving, TX)
Application Number: 12/573,378
International Classification: H03M 1/66 (20060101);