CURVATURE-COMPENSATED BAND-GAP VOLTAGE REFERENCE CIRCUIT
A band-gap reference voltage is developed by a phase-clocked band-gap circuit including a single PN junction through which first and second constant currents are alternately directed. A current proportional to absolute temperature is selectively added to one of the first and second constant currents to curvature-compensate the developed band-gap reference voltage. The band-gap circuit is calibrated at any desired temperature by interrupting the curvature compensation current and trimming the one constant current to bring the un-compensated band-gap reference voltage into correspondence with a nominal band-gap voltage functionally related to the calibration temperature and circuit component values.
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The present invention relates to voltage reference circuits, and more particularly to a low-cost high-precision curvature-compensated band-gap voltage reference circuit.BACKGROUND OF THE INVENTION
Band-gap voltage reference circuits are routinely used in integrated circuit applications that require a reference voltage that is reasonably precise and stable over a range of temperatures. Fundamentally, a band-gap voltage reference circuit includes two bipolar base-emitter junctions operating at different current densities. The reference voltage is obtained by summing one of the base-emitter voltages with a scaled difference of the two base-emitter voltages. Since the base-emitter voltage is inversely proportional to temperature and the scaled difference voltage is directly proportional to temperature, their sum is temperature independent to the first order. However, the reference voltage still exhibits some second and higher order nonlinearity (curvature) with temperature, and various techniques have been developed to compensate for these nonlinearities. For example, the circuitry of the reference generator can be trimmed or calibrated at a number of different temperature settings, and/or various non-linear waveforms can be used to cancel out the non-linearity of the reference. Also, special steps must be taken to minimize stresses caused by the circuit packaging because package stress non-uniformity can introduce additional voltage instability over time.
Conventional approaches for addressing the curvature compensation and package stress issues typically result in a component cost that is too high for many applications. Accordingly, what is needed is a high-precision curvature-compensated band-gap voltage reference circuit that is low in cost, easily calibrated, and substantially insensitive to packaging stresses.SUMMARY OF THE INVENTION
The present invention is directed to an improved high-precision voltage reference circuit featuring a novel way of generating a curvature-compensated band-gap reference voltage that is substantially insensitive to package stress, and a novel calibration technique that can be carried out at any desired temperature. A band-gap reference voltage is developed by a phase-clocked band-gap circuit including a single PN junction through which first and second constant currents are alternately directed. A current proportional to absolute temperature is selectively added to one of the first and second constant currents to curvature-compensate the developed band-gap reference voltage. The band-gap circuit is calibrated at any desired temperature by interrupting the curvature compensation current and trimming the one constant current to bring the un-compensated band-gap reference voltage into correspondence with a nominal band-gap voltage functionally related to the calibration temperature and circuit component values.
Referring to the drawings, and particularly to
The main band-gap circuit 20, described in detail below in reference to
The voltage boost circuit 22, described in detail below in reference to
For the sake of discussion, it is initially assumed that the CALIB switch 76 is open. Under this condition, the current IC flows through diode 60 when clock signal φ2 is high, and the current IC·(1+α) flows through diode 60 when clock signal φ1 is high. When φ2 is high, the amplifier 62 is un-coupled from the output terminal 56, and the output voltage is held by filter capacitor 68. Also, capacitor 64 is discharged by switch 74. The voltage across diode 60 under this condition is designated herein as VBE1, and amplifier 62 operates as a voltage-follower, developing a corresponding voltage at its output (and across capacitor 66). When φ1 is high, the output of amplifier 62 is coupled to output terminal 56, and capacitors 64 and 66 operate as a voltage divider. The voltage across diode 60 under this condition is designated herein as VBE2, and amplifier 62 develops voltage at its output based on VBE2 and the capacitance ratio C2/C1. Due to the alternately differential current flowing in diode 60, and the operation of phase-clocked amplifier 62, an uncompensated band-gap reference voltage VUBG is developed at output terminal 56, according to equation (1) below:
where VG0 is the silicon band-gap voltage of diode 60, γ is a process constant, T is an actual temperature (in ° K), T0 is a reference temperature, E is a constant, VT=k·T/q, q is the electron charge, and k is the Boltzmann constant.
When the CALIB switch 76 is in its normally closed state, the scaled PTAT current β·IT flows through diode 60 along with the scaled and un-scaled constant currents IC and α·IC when the clock signal φ1 is high. The scaled PTAT current β·IT produces a VBE2 component having a quadratic (i.e., second-order) relationship with temperature that curvature-compensates the uncompensated band-gap reference voltage VUBG for second-order non-linearity with temperature. While third and higher order non-linearities remain, they are relatively small in magnitude for temperatures between −50° C. and +150° C. In fact, testing has shown that the curvature-compensated band-gap reference voltage VBG exhibits a voltage variation as low as 0.1 percent over this 200° C. range of temperatures. The curvature-compensated band-gap reference voltage VBG is given by the following equation:
where, f=β·k1, k1=k·ln(m)/(q·R1), m is the current density ratio of bipolar transistors 24 and 26 in auxiliary band-gap circuit 14, and R1 is the resistance of resistor 28 in auxiliary band-gap circuit 14.
The voltage boost circuit 22 of
When φ2 is high, the voltage boost circuit 22 is isolated from the main band-gap circuit 20, and the switches 88 and 90 discharge the capacitors 92 and 94. When φ1 is high, switch 82 couples the voltage boost circuit 22 to the main band-gap circuit 20, and capacitor 96 samples the band-gap voltage VBG. The sampled voltage is applied to the inverting input of operational amplifier 98, which controls the conduction of a FET 100 connected between source voltage VDD and output terminal 80. The current sink 102 establishes a small static current flow through FET 100, but the amplifier 98 drives FET 100 to charge the capacitors 92, 94 and 104 until the voltage across capacitor 94 is equal to the sampled band-gap voltage. At this point, the voltage V3P3 at output terminal 80 is equal to VBG·[1+(C4/C3)], where C4 and C3 are the capacitance values of capacitors 94 and 92, respectively. When φ2 becomes high, capacitor 96 holds the previously sampled voltage, switches 88 and 90 discharge the capacitors 92 and 94, and the capacitor 104 holds the previously settled voltage value of amplifier 98 until φ1 becomes high. The capacitor 104 thus filters the dynamic response of the circuit, and the average value of V3P3 is given by the above expression: VBG·[1+(C4/C3)]. The capacitors 92 and 94 are preferably fabricated as surface poly-to-poly integrated circuit devices, which characteristically exhibit very low sensitivity to packaging stress, voltage, and temperature; and the capacitance of capacitor 94 is trimable as described below in reference to the calibration flow diagram of
An important aspect of the present invention is the provision of a calibration procedure whereby errors due to manufacturing process variations are corrected at any one conveniently selected temperature. Prior to calibration, the scaling parameters α and β and the capacitance ratios (C2/C1) and (C4/C3) are set based on theoretical or nominal design considerations. The scaling parameter cc is set to a value that theoretically optimizes the temperature stability of the un-compensated band-gap voltage VUBG, based on equations (1-2), for example. The scaling parameter β and the capacitance ratio (C2/C1) are set to values that theoretically provide optimal curvature compensation of VUBG, based on equation (2), for example. And finally, the capacitance ratio (C4/C3) is set to a value that theoretically provides the desired value of output voltage V3P3. In the calibration procedure, the scaling parameter cc and the capacitance C4 are trimmed to account for any deviation between theoretical and actual considerations.
The flow diagram of
The calibration of scaling parameter α is illustrated by blocks 114, 116, 118, 120 and 122. The CALIB switch 76 of main band-gap circuit 20 is opened to suppress the curvature correction, and the actual voltage at output terminal 56 (designated as VBG_ACT) is measured. If VBG_ACT is not equal to the nominal un-compensated band-gap voltage VUBG, the scaling parameter α is trimmed until equality is achieved. When VBG_ACT is equal to VUBG, the CALIB switch 76 of main band-gap circuit 20 is closed to reapply the curvature correction.
An optional calibration of the scaling parameter 13 is illustrated by blocks 124, 126 and 128. The actual voltage VBG_ACT is re-measured and compared to the nominal curvature-compensated band-gap voltage VBG determined at block 112. If VBG_ACT is not equal to VBG, the scaling parameter β is trimmed until equality is achieved.
The calibration of capacitance C4 is illustrated by blocks 130, 132 and 134. The actual voltage at output terminal 80 of voltage boost circuit 22 (V3P3_ACT) is measured, and compared to its nominal or target value V3P3_TARGET. If V3P3_ACT is not equal to V3P3_TARGET, the capacitance C4 is trimmed until equality is achieved. The calibration of capacitance C4 is completed when V3P3_ACT is equal to V3P3_TARGET.
In summary, the present invention provides a high-precision curvature-compensated band-gap voltage reference circuit that is low in cost compared to other known circuits, easily calibrated at a single user-selected temperature, and substantially insensitive to packaging stresses. While the present invention has been described with respect to the illustrated embodiment, it is recognized that numerous modifications and variations in addition to those mentioned herein will occur to those skilled in the art. For example, the illustrated circuit elements may be implemented in various ways (e.g., as discrete devices and/or up-integrated devices), and so on. Accordingly, it is intended that the invention not be limited to the disclosed embodiment, but that it have the full scope permitted by the language of the following claims.
1. A band-gap voltage reference circuit, comprising:
- a PN junction;
- a phase-clocked input circuit receiving first and second input currents that are substantially constant and a third input current that is proportional to absolute temperature, and alternately supplying first and second output currents to said PN junction during successive clock phases to alternately establish first and second VBE voltages across said PN junction; and
- a phase-clocked amplifier circuit responsive to the first and second VBE voltages established during said successive clock phases for producing a curvature-compensated band-gap reference voltage.
2. The band-gap voltage reference circuit of claim 1, further comprising:
- an auxiliary band-gap reference generator circuit for producing said first, second and third input currents.
3. The band-gap voltage reference circuit of claim 1, where:
- said first output current is said first input current; and
- said second output current is a sum of said first, second and third input currents.
4. The band-gap voltage reference circuit of claim 1, where:
- said first and second input currents are related by a scaling parameter; and
- said phase-clocked input circuit includes a calibration switch that suppresses said third input current in a calibration mode, during which said scaling parameter is trimmed to bring an output of said phase-clocked amplifier circuit into correspondence with a first nominal design value.
5. The band-gap voltage reference circuit of claim 4, where:
- said first nominal design value is a function of temperature during said calibration mode.
6. The band-gap voltage reference circuit of claim 4, where:
- said calibration switch is closed following the trimming of said scaling parameter, and said third input current is then trimmed to bring said curvature-compensated band-gap reference voltage into correspondence with a second nominal design value.
7. The band-gap voltage reference circuit of claim 6, where:
- said second nominal design value is a function of temperature during said calibration mode.
8. The band-gap voltage reference circuit of claim 4, where:
- the trimming of said scaling parameter at any one temperature calibrates said curvature-compensated band-gap reference voltage.
9. The band-gap voltage reference circuit of claim 1, further comprising:
- a voltage boost circuit for boosting said curvature-compensated band-gap reference voltage to form an output voltage, including a trimable device that is adjusted in value to bring said output voltage into correspondence with a target value.
International Classification: G05F 1/10 (20060101);