CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER
A voltage converter is switched among two or more modes to produce an output voltage matching a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. The output voltage is compared with the reference voltage to determine whether to adjust the mode.
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The benefit of the filing date of U.S. Provisional Patent Application Ser. No. 61/265,454, filed Dec. 1, 2009, entitled “Continuously Variable Switched Capacitor DC-DC Supply,” is hereby claimed, and the specification thereof is incorporated herein in its entirety by this reference. U.S. patent application Ser. No. ______, filed ______, entitled “VOLTAGE CONVERSION METHOD IN A CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER,” is related.
BACKGROUNDOne type of device that converts one DC voltage level to another is commonly known as a DC-to-DC converter (or “DC-DC” converter). DC-DC converters are commonly included in battery-operated devices such as mobile telephones, laptop computers, etc., in which the various subsystems of the device require several discrete voltage levels. In some types of devices, such as a mobile telephone that operates in a number of different modes, it is especially desirable to supply certain elements, such as power amplifiers, with a supply voltage at the most efficient level for the mode of operation, rather than waste power and accordingly drain the battery prematurely. In such devices, it is desirable to employ a DC-DC converter that can generate a greater number of discrete voltage levels.
Several types of DC-DC converters are known, including switched-mode DC-DC converters and DC-DC converters that employ pulse-width modulation (PWM). Switched-mode DC-DC converters convert one DC voltage level to another by storing the input energy momentarily in inductors or capacitors and then releasing that energy to the output at a different voltage. The switching circuitry thus continuously switches between two states or phases: a first state in which a network of inductors or capacitors is charging, and a second state in which the network is discharging. The switching circuitry can be configured to generate an output voltage that is a fixed fraction of the battery voltage, such as one-third, one-half, two-thirds, etc., where a mode selection signal is provided as an input to the switching circuitry to control which of the fractions is to be employed. Different configurations of the network of inductors or capacitors can be selected by manipulating switches in the network using the mode selection signal.
The number of discrete output voltages that a switched-mode DC-DC converter can generate is related to the number of inductors or capacitors. In a portable, handheld device such as a mobile telephone it is desirable to minimize size and weight. A DC-DC converter having a large number of inductors or capacitors is not conducive to minimizing the size and weight of a mobile telephone. A PWM-based DC-DC converter can generate a larger number of discrete voltages than a switched-mode DC-DC converter without employing significantly more inductors, capacitors or other elements. However, a PWM-based DC-DC converter can generate a large spectrum of spurious output signals that can adversely affect the operation of a mobile telephone or other frequency-sensitive device. Filters having large capacitances or inductances can be included in a PWM-based DC-DC converter to minimize these spurious signals, but large filter capacitors or inductors are undesirable for the same reasons described above.
SUMMARYEmbodiments of the invention relate to a switching voltage converter that can produce an output signal of not only any of a number of discrete voltage levels but also of intermediate values between the discrete voltage levels, by switching between two or more selectable modes, each corresponding to one of the discrete voltage levels. In an exemplary embodiment, the voltage converter is a switched-capacitor voltage converter having a two or more capacitors, a switch matrix, comparator logic, and control logic. A reference signal is input to the comparator logic, which also receives the output signal as feedback. In each mode, the switch matrix interconnects the capacitors in a different configuration. Each mode or mode configuration has two phase configurations: one in which the capacitor circuit is charged and another in which the capacitor circuit is discharged. The switch matrix switches between the two phase configurations of a selected mode configuration in response to a clock signal. As a result of this switching, the voltage converter produces an output signal having a voltage that corresponds to a selected mode configuration. By alternately switching between two of the modes, the voltage converter can produce an output voltage having a level that corresponds to the reference signal voltage in an instance in which the reference signal voltage lies between two of the discrete voltage levels corresponding to those modes.
In the exemplary embodiment, the comparator logic compares the output signal with the reference signal and produces a direction comparison signal indicating which of the output signal and the reference signal is greater in magnitude than the other. The comparison signal thus indicates whether the control logic is to cause the output signal voltage to increase or decrease to match the reference signal.
In the exemplary embodiment, the control logic uses one or more signals from the comparator logic, including the direction comparison signal, to select the mode. If the direction comparison signal indicates that the reference signal is greater than the output signal, the control logic can switch the mode to one that corresponds to an output signal voltage that is greater than the reference signal. Changing the mode in this manner causes the output signal voltage to increase. However, if the direction comparison signal indicates that the output signal is greater than the reference signal, the control logic can switch the mode to one that corresponds to an output signal voltage less than the reference signal. Changing the mode in this manner causes the output signal voltage to decrease.
Other systems, methods, features, and advantages of the invention will be or become apparent to one with skill in the art upon examination of the following figures and detailed description.
The invention can be better understood with reference to the following figures. The components within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.
As illustrated in
Switch matrix 16 can assume one of several mode configurations, described below, in which capacitors 12 and 14 are interconnected in different configurations. In each mode configuration, switch matrix 16 can assume either a first phase configuration, in which the capacitor circuit defined by the interconnected capacitors 12 and 14 is charging, or a second phase configuration, in which the capacitor circuit defined by the interconnected capacitors 12 and 14 is discharging. Switch matrix 16 provides the output of the capacitor circuit at an output node 26. In operation, switch matrix 16 alternately switches between the first and second phase configurations in response to the clock signal. Filter circuitry, such as a capacitor 28, can be connected to output node 26 to filter the output voltage signal.
As described in further detail below, comparator circuit 18 compares the output voltage signal with the reference voltage signal and, in response, produces a number of comparison signals 30. Control logic 20 includes mode selection logic 32 and switch control logic 34. Mode selection logic 32 receives comparison signals 30 and, in response, produces mode selection signals 36. Switch control logic 34 receives mode selection signals 36 and, in response, produces switch control signals 38.
As illustrated in
Although in the exemplary embodiment switch matrix 16 includes nine switches, which can be arranged as shown, in other embodiments a switch matrix can include any other number of switches arranged in any other suitable manner. Similarly, although the exemplary embodiment includes two capacitors 12 and 14, which switch matrix 16 can interconnect as described below, other embodiments can include more than two capacitors, and a switch matrix can interconnect them in any other suitable configurations.
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The ½B mode variant of the second mode configuration is shown in
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In the exemplary embodiment, mode selection logic 32 of control logic 20 (
Table 80 indicates the “next mode” to which control logic 20 is to cause switch matrix 16 to switch in response to a combination of the outputs of comparators 58-64 (V_UD, V_23, V_12 and V_13, respectively). The modes indicated in table 80 are those described above: the ⅓ mode, the ½A mode, the ½B mode, and the ⅔ mode. Table 80 also indicates whether to “hold” the current mode, i.e., to maintain the current mode as the next mode. Specifically, the outputs of all of comparators 58-64 being low indicates that the current mode is to be held in the (second phase configuration of the) ⅓ mode. In all other instances, table 80 indicates that the mode is to switch. As described below, the mode can switch from the current mode to the next mode on every other clock cycle. It should be noted that a reference herein to “switching” or “changing” modes or to providing a mode control signal is intended to encompass within its scope of meaning not only changing to a different mode but also to maintaining the same mode at the time during which mode switching can occur, i.e., switching or changing from the current mode to the “next” mode in an instance in which both the current mode and next mode are the same. Also note that in the exemplary embodiment table 80 omits the instance in which the outputs of all of comparators 58-64 are high, as this combination would indicate that control logic 20 is to cause the output voltage signal to approach the battery voltage, which may be undesirable. Nevertheless, in other embodiments such an output and associated additional mode can be provided.
Although not shown for purposes of clarity, mode selection logic 32 (
As illustrated in
Switch control logic 34 also includes decoder logic 92 coupled to the outputs of flip-flops 82-88. Decoder logic 92 decodes the latched MODE[2:0] word and “hold” signal into the individual switch control signals 38 (S1-S9) that control the above-described switches 40-56 of switch matrix 16. Note that while mode selection signals 36 indicate the “next” mode, the latched MODE[2:0] word and “hold” signal indicate the “current” mode. Decoder logic 92 produces switch control signals 38 (S1-S9) in response to the current mode and the clock signal.
The operation of decoder logic 92 is reflected in the circuit diagrams of
An example of the operation of voltage converter 10 in the exemplary embodiment is shown in
At timepoint 94, V_OUT reaches a level of ⅓ (V_BATT). In response, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V23) changes to correspond to the ½A mode, because V_OUT exceeds ⅓ (V_BATT) but is less than ½ (V_BATT). Note that the current mode or output of decoder logic 92 (
At timepoint 96 in this example, V_OUT reaches a level of ½ (V_BATT). In response, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V23) changes to correspond to the ⅔ mode, because V_OUT exceeds ½ (V_BATT) but is less than ⅔ (V_BATT). In the ⅔ mode, the operation of the capacitor circuit causes V_OUT to continue rising toward a level of ⅔ V_BATT. However, at timepoint 98 V_OUT reaches V_REF. In response, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V23) changes to correspond to the ½B mode. In the ½B mode, the operation of the capacitor circuit causes V_OUT to fall toward a level of ½ (V_BATT). However, at timepoint 100 V_OUT crosses V_REF again. In response, the combination of the states of comparison signals 30 (V_UD, V_13, V_12 and V23) changes to correspond to the ⅔ mode, and V_OUT again begins rising toward a level of ⅔ (V_BATT) at timepoint 103. Thus, once V_OUT reaches V_REF, V_OUT alternately crosses V_REF as it rises toward the ⅔ mode configuration and crosses V_REF as it falls toward the ½B mode configuration. Between timepoints 98 and 102, on average, V_OUT is maintained at a voltage approximately equal to V_REF. The variations or deviations in V_OUT from V_REF can be minimized by including filter circuitry at the output of voltage converter 10, such as capacitor 28 (
In the example shown in
As illustrated in
While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. Accordingly, the invention is not to be restricted except in light of the following claims.
Claims
1. A voltage converter, comprising:
- a switch matrix having a plurality of mode configurations, each mode configuration corresponding to one of a plurality of output signal voltages, the mode configuration being selectable in response to a mode control signal;
- comparator logic implemented to compare the output signal with a reference signal and produce a direction comparison signal; and
- control logic implemented to produce the mode control signal in response to the direction comparison signal.
2. The voltage converter of claim 1, wherein each mode configuration is defined by a capacitor circuit having a plurality of capacitors interconnected with each other between a voltage potential and an output node.
3. The voltage converter of claim 2, wherein each mode configuration has a first phase configuration in which the capacitor circuit is charged and a second phase configuration in which the capacitor circuit is discharged.
4. The voltage converter of claim 3, wherein the switch matrix switches between the first phase configuration and the second phase configuration of a selected mode configuration in response to a clock signal to produce an output signal at the output node having an output signal voltage corresponding to the selected mode configuration.
5. The voltage converter of claim 1, wherein the direction comparison signal indicates which of the output signal and the reference signal is greater.
6. The voltage converter of claim 5, wherein the control logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage greater than the reference signal in response to the direction comparison signal indicating that the reference signal is greater than the output signal, and the control logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage less than the reference signal in response to the direction comparison signal indicating that the output signal is greater than the reference signal.
7. The voltage converter of claim 1, wherein the switch matrix has three mode configurations.
8. The voltage converter of claim 7, wherein the three mode configurations include a first mode configuration corresponding to an output signal voltage of one-third of a base reference voltage, a second mode configuration corresponding to an output signal voltage of one-half of the base reference voltage, and a third mode configuration corresponding to an output signal voltage of two-thirds of the base reference voltage.
9. The voltage converter of claim 8, wherein the comparator logic includes a plurality of comparators and a voltage level generator circuit that generates a plurality of reference voltage levels and provides a selected reference voltage level to a first input of each comparator, each voltage level corresponding to one of the plurality of output signal voltages, the second input of each comparator coupled to the output signal, each comparator providing a corresponding comparison signal.
10. The voltage converter of claim 9, wherein the plurality of comparators comprises three comparators.
11. The voltage converter of claim 10, wherein a first comparator compares the output signal with a first reference voltage signal having a voltage of a first fraction of a base reference voltage and produces a first comparison signal.
12. The voltage converter of claim 11, wherein the first comparison signal indicates whether the output signal voltage exceeds the first fraction of the base reference voltage.
13. The voltage converter of claim 11, wherein a second comparator compares the output signal with a second reference voltage signal having a voltage of a second fraction of a base reference voltage greater than the first fraction of the base reference voltage and produces a second comparison signal.
14. The voltage converter of claim 13, wherein the second comparison signal indicates whether the output signal voltage exceeds the second fraction of the base reference voltage.
15. The voltage converter of claim 13, wherein a third comparator compares the output signal with a third reference voltage having a voltage of a third fraction of a base reference voltage greater than the second fraction of the base reference voltage signal and produces a third comparison signal.
16. The voltage converter of claim 15, wherein the third comparison signal indicates whether the output signal voltage exceeds the third fraction of the base reference voltage.
17. The voltage converter of claim 15, wherein the three mode configurations include a first mode configuration corresponding to an output signal voltage of the first fraction of the base reference voltage, a second mode configuration corresponding to an output signal voltage of the second fraction of the reference voltage, and a third mode configuration corresponding to an output signal voltage of the third fraction of the reference voltage.
18. The voltage converter of claim 17, wherein the first fraction is one-third, the second fraction is one-half and the third fraction is two-thirds.
19. The voltage converter of claim 17, wherein the control logic comprises combinational logic responsive to combinations of the first, second and third comparison signals.
20. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the first fraction of the base reference voltage if the first comparison signal indicates that the output signal voltage does not exceed the first fraction of the base reference voltage and the direction comparison signal indicates that the reference signal is greater than the output signal.
21. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the first fraction of the base reference voltage if the first comparison signal indicates that the output signal voltage exceeds the first fraction of the base reference voltage, the second comparison signal indicates that the output voltage does not exceed the second fraction of the base reference voltage, and the direction comparison signal indicates that the reference signal is less than the output signal.
22. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the second fraction of the base reference voltage if the first comparison signal indicates that the output signal voltage exceeds the first fraction of the base reference voltage, the second comparison signal indicates that the output voltage does not exceed the second fraction of the base reference voltage, and the direction comparison signal indicates that the reference signal is greater than the output signal.
23. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the second fraction of the base reference voltage if the second comparison signal indicates that the output voltage exceeds the second fraction of the base reference voltage, the third comparison signal indicates that the output voltage does not exceed the third fraction of the base reference voltage, and the direction comparison signal indicates that the reference signal is less than the output signal.
24. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the third fraction of the base reference voltage if the second comparison signal indicates that the output voltage exceeds the second fraction of the base reference voltage, the third comparison signal indicates that the output voltage does not exceed the third fraction of the base reference voltage, and the direction comparison signal indicates that the reference signal is greater than the output signal.
25. The voltage converter of claim 19, wherein the combinational logic produces the mode control signal to select a mode configuration corresponding to an output signal voltage of the third fraction of the base reference voltage if the third comparison signal indicates that the output voltage exceeds the third fraction of the base reference voltage and the direction comparison signal indicates that the reference signal is less than the output signal.
Type: Application
Filed: Nov 30, 2010
Publication Date: Jun 2, 2011
Applicant: SKYWORKS SOLUTIONS, INC. (Woburn, MA)
Inventors: David S. Ripley (Marion, IA), Hui Liu (Cedar Rapids, IA)
Application Number: 12/955,989
International Classification: H02M 3/07 (20060101);