Abstract: An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins of a first electronic device and pins of the electronic device by the electronic device, wherein the first electronic device comprises at least one data pin; and (b) applying the connections between the pins of the first electronic device and the pins of the electronic device as a device ID of the first electronic device by the electronic device.

Abstract: According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

Abstract: A hardware trojan security system may perform a computer implemented method to secure an electronic facility in relation to a hardware trojan, by performing a trojan vulnerability analysis, locating an instrument site location, identifying a selected instrument in relation to an effect of the trojan, marking instrument control-side markers and instrument operative-side markers, marking facility model control-side markers and facility model operative-side markers, marking access architecture control-side markers, and connecting the instrument with the facility model and access architecture by matching corresponding markers.

Abstract: In embodiments of statistics chart row mode drill down, a first interface is displayed in a table format that includes columns and rows, where each row is associated with an event and each column includes field for a respective event. The rows can further include one or more aggregated metrics representing a number of events associated with a respective row. A row can be emphasized in the first interface and, in response a menu can be displayed with selectable options to transition to a second interface, where the data displayed by the second interface is based on an option selected from the menu.

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for parameterization of physical dimensions of discrete circuit components for component definitions that define discrete circuit components. The component definitions may be selected for use in a device design. When a parametrization of a particular version of a discrete circuit component definition is changed, the version level of the device design is also changed and the circuit layout for the device design is physically verified for the new version level.

Abstract: A system and method for changing a circuit design are described. The method includes generating a propagation graph for the circuit design and estimating slack values for some of the paths in the propagation graph. The method also includes making a virtual change to the circuit design and determining whether to accept or reject the change based on how the change affects the estimated slack values.

Abstract: A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

Abstract: A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

Abstract: The present disclosure discloses an information security application-oriented reconfigurable system chip compiler and an automatic compilation method. The method includes the following steps: firstly, inputting a source program of a cryptographic algorithm; then, executing a software compilation function syntax check of the source program, and when the check result is passed, performing compilation mapping using a compiler; next, executing the cryptographic algorithm by simulation running using a simulator, and generating a configuration code by a simulator array; and finally, guiding a hardware behavior operation using a binary configuration code file generated by the simulator. The reconfigurable system chip compiler includes a source program input module, a software compilation function verification module, a compilation mapping module, a simulation execution module, a configuration code generation module, and a hardware debugging module.

Abstract: Embodiment herein provides a method for managing uniqueness constraints associated with entities in a graph database. The method includes receiving a constraint specification of an entity from a constraint management system and receiving a configure operation for maintaining uniqueness requirement in the constraint management system. The method also includes determining a constraint key based on inputs received for maintaining the uniqueness requirement in the constraint management system; and creating a composite unique constraint based on the constraint key. The composite unique constraint comprises properties of the constraint key and a constraint vertex indicating a class of constraints available in the inputs received for maintaining uniqueness requirement. The method also includes storing the composite unique constraint in the constraint specification received from the constraint management system to validate the uniqueness before performing an operation on the entity.

Abstract: A data transmission circuit may include a plurality of data transmission lines configured to transmit a victim data signal through a victim data transmission line, and transmit an adjacent data signal through an adjacent data transmission line disposed adjacent to the victim data transmission line; and a data input/output circuit configured to control a reference voltage level reflected into the victim data signal on the basis of data pattern information of the adjacent data signal, and compare the victim data signal to the reference voltage level and output the comparison result.

Abstract: A semiconductor device includes: an arithmetic circuit that repeats an operation related to a cryptographic processing for the predetermined number of rounds; a holding circuit that holds data related to the number of rounds of an operation of the arithmetic circuit; a judgement circuit that determines whether the number of rounds is the predetermined number of rounds; and an output buffer circuit that outputs the arithmetic result data of the arithmetic circuit when the judgement circuit determines that the number of rounds is the predetermined number. It is configured to duplicate the holding circuit, and not to output the arithmetic result data when two outputs of the duplicated holding circuit are not matched.

Abstract: Devices and circuitry for computing hash values.

Abstract: A method, computer program product, and computing system for defining a library of functional modules; enabling a user to select a plurality of functional modules from the library of functional modules; and enabling the user to visually arrange the plurality of functional modules to form a conversational application.

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: The timing margin of various signal paths in an integrated circuit is monitored by components on the integrated circuit itself. Path margin monitor (PMM) circuits on the integrated circuit receive (a) functional signals propagating along signal paths in the integrated circuit, and (b) corresponding clock signals that are used to clock the functional signals. The PMM circuits output signals (PMM signals) which are indicative of the actual timing margins for the signal paths. For convenience, these will be referred to as path margins. A controller is also integrated on the integrated circuit. The controller controls the PMM circuits. It also receives and analyzes the PMM signals to monitor the path margins across the integrated circuit. Automated software is used to automatically insert instances of the PMM circuits into the design of the integrated circuit. The controller may also be automatically configured and inserted into the design.

Abstract: Systems, methods, and computer-readable storage media are described for modeling the requirements of software to generate test requirements. In one exemplary embodiment, a computer-implemented method comprises generating a model of the requirements using a tree graph model, identifying primary paths of the tree graph model using an algorithm, and creating test cases based on the identified primary paths.

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: According to the present invention, an inter prediction method comprises the steps of: generating a merge candidate list for a block to be predicted, wherein the block is to correspond to a current prediction unit; deriving, on the basis of one of a plurality of merge candidates constituting the merge candidate list, motion information on the block to be predicted; and performing, on the basis of the derived motion information, a prediction on the block to be predicted so as to generate a prediction block corresponding to the current prediction unit.

Abstract: A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters.

Abstract: Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.

Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.

Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.

Abstract: An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the clock pin and the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins between the first electronic device and the second electronic device by the second electronic device; (b) applying the connections as a device ID of the first electronic device by the second electronic device; and (c) setting pins of the first electronic device such that the data pins of the second electronic device are coupled to the data pins of the first electronic device.

Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.

Abstract: Techniques are disclosed for performing time synchronization at a plurality of computing devices in a network. In one example, a method comprising obtaining timestamp data in accordance with a synchronization operation for a timing protocol; computing a skewness estimate and an offset estimate from the timestamp data by executing a regression analysis, wherein the regression analysis is configured to train a first model to predict the offset estimate and the skewness estimate, the offset estimate comprising a clock time difference between the first clock and the second clock; computing a corrected skewness estimate and a corrected offset estimate based on a second model having parameters based on the offset estimate and the skewness estimate; and modifying a current time value of at least one of the first clock or the second clock based on at least one of the corrected offset estimate or the corrected skewness estimate.

Abstract: A connection analysis method for a multi-port nested model and a medium. The method includes: acquiring instance information and nested relationships of a multi-port nested model, and building an instance relationship tree; reading port information and connection information of instances, and adding the port information and the connection information to the instance relationship tree; acquiring the port information and the connection information of the instances of each node layer by layer according to the instance relationship tree to build a connection dictionary; and acquiring port-to-port connection information of the instances by retrieving the connection dictionary to perform connection analysis on the multi-port nested model.

Abstract: Blind spots in a network system are identified and eliminated. Synthetic transactions are generated and transmitted across a network system, and at least a portion of the synthetic transactions is captured. Parts of the synthetic transactions that were not captured can be determined and employed to generate a logical security map of the network system based on the captured synthetic transactions. At least one blind spot can be identified from in the logical security map of the network system, and a solution determined to eliminate the at least one blind spot. Subsequently, the solution is implemented for the network system to eliminate the blind spot.

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

Abstract: A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Abstract: Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing paths, is modified from a first value to a second value, based on the path margin. A design metric relating to the IC design is updated based on the modified second slack. The IC design is configured to be used to fabricate an IC.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.

Abstract: A method, computer program product, and computing system for defining a library of functional modules; enabling a user to select a plurality of functional modules from the library of functional modules; and enabling the user to visually arrange the plurality of functional modules to form a conversational application.

Abstract: Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.