Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: A method is disclosed. The method includes computing a time delay for each path of a plurality of paths of a circuit design and determining a commonality score based on a number of segments that are common between the plurality of paths of the circuit design. The method further includes determining a criticality score based on the time delay for each path of the plurality of paths of the circuit design. The method further includes generating a graphical representation of the plurality of paths, wherein a first dimension of the graphical representation corresponds to the commonality score and wherein a second dimension of the graphical representation corresponds to the criticality score. The method further includes providing the graphical representation of the plurality of paths in a graphical user interface (GUI) to represent the plurality of paths in the circuit design.

Abstract: According to the present invention, an inter prediction method comprises the steps of: generating a merge candidate list for a block to be predicted, wherein the block is to correspond to a current prediction unit; deriving, on the basis of one of a plurality of merge candidates constituting the merge candidate list, motion information on the block to be predicted; and performing, on the basis of the derived motion information, a prediction on the block to be predicted so as to generate a prediction block corresponding to the current prediction unit.

Abstract: Methods and systems for circuit design are described. A tool may detect a timing violation on a signal path connected to a local clock buffer in a circuit model. The local clock buffer may be configured to generate a first clock signal having a first pulse width. The tool may determine a first metric associated with a first type of timing violation, and may determine a second metric associated with a second type of timing violation different from the first type of timing violation. The detected timing violation may be one of the first type and second type of timing violations. The tool may, based on the first metric and the second metric, determine whether to retain the generation of the first clock signal or to configure the local clock buffer to generate a second clock signal having a second pulse width different from the first pulse width.

Abstract: A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters.

Abstract: Various embodiments provide for multi-threaded network routing of a circuit design based on partitioning networks of the circuit design, which can enable partitioning routing tasks for the circuit design. More particularly, some embodiments iteratively partition networks of a circuit design into groups of networks, which enable various embodiments to schedule routing tasks for those groups of networks to available threads such that no two networks of the circuit design with overlapping routing regions are routed at the same time, and such that idle time of each thread (e.g., time where thread has no work or is waiting for another thread to finish) can be minimized.

Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.

Abstract: A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.

Abstract: An electronic device comprising: a clock pin; at least one data pin; a storage device, configured to store at least one program; a processing circuit, coupled to the clock pin and the data pin. A device ID setting method is performed when the processing circuit executes the program stored in the storage device. The device ID setting method comprises; (a) recording connections between pins between the first electronic device and the second electronic device by the second electronic device; (b) applying the connections as a device ID of the first electronic device by the second electronic device; and (c) setting pins of the first electronic device such that the data pins of the second electronic device are coupled to the data pins of the first electronic device.

Abstract: A method is provided for performing power validation on an integrated circuit (IC) design based on a power assertion specification. The method includes receiving the power assertion specification for the IC design, where the power assertion specification includes a predicted power consumption. Power consumption of the IC design is estimated according to power assertions specified in the power assertion specification. The estimated power consumption is compared against the predicted power consumption included in the power assertion specification. The IC design is determined to be associated with a power assertion failure based on results of the comparing. In response to determining that the IC design is associated with the power assertion failure, the IC design is refined to remedy the power assertion failure.

Abstract: A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.

Abstract: Techniques are disclosed for performing time synchronization at a plurality of computing devices in a network. In one example, a method comprising obtaining timestamp data in accordance with a synchronization operation for a timing protocol; computing a skewness estimate and an offset estimate from the timestamp data by executing a regression analysis, wherein the regression analysis is configured to train a first model to predict the offset estimate and the skewness estimate, the offset estimate comprising a clock time difference between the first clock and the second clock; computing a corrected skewness estimate and a corrected offset estimate based on a second model having parameters based on the offset estimate and the skewness estimate; and modifying a current time value of at least one of the first clock or the second clock based on at least one of the corrected offset estimate or the corrected skewness estimate.

Abstract: A connection analysis method for a multi-port nested model and a medium. The method includes: acquiring instance information and nested relationships of a multi-port nested model, and building an instance relationship tree; reading port information and connection information of instances, and adding the port information and the connection information to the instance relationship tree; acquiring the port information and the connection information of the instances of each node layer by layer according to the instance relationship tree to build a connection dictionary; and acquiring port-to-port connection information of the instances by retrieving the connection dictionary to perform connection analysis on the multi-port nested model.

Abstract: Blind spots in a network system are identified and eliminated. Synthetic transactions are generated and transmitted across a network system, and at least a portion of the synthetic transactions is captured. Parts of the synthetic transactions that were not captured can be determined and employed to generate a logical security map of the network system based on the captured synthetic transactions. At least one blind spot can be identified from in the logical security map of the network system, and a solution determined to eliminate the at least one blind spot. Subsequently, the solution is implemented for the network system to eliminate the blind spot.

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

Abstract: A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Abstract: A non-transitory computer-readable recording medium storing a timing library creation program of causing a computer to execute processing, the processing including: extracting, from a delay variation database that stores delay variation values of gates included in circuit design data, a delay variation value, out of the delay valuation values matching to characteristics which are characteristics of one of signal paths in the circuit design data and which include a threshold voltage, a drive force, and a number of gate stages of the signal path; calculating an extended delay variation coefficient based on the extracted delay variation value and the characteristics; and creating, based on a basic timing library in which the delay variation value is not reflected and the extended delay variation coefficient, an extended timing library in which the delay variation value is reflected.

Abstract: Techniques for integrated circuit (IC) design are disclosed. A path margin is determined for an endpoint of a plurality of timing paths for an IC design. This includes identifying a sub-critical path, among the plurality of timing paths, where the sub-critical path has more slack than a critical path relating to the endpoint. The path margin is generated based on a first slack associated with the sub-critical path. A second slack, relating to at least one of the plurality of timing paths, is modified from a first value to a second value, based on the path margin. A design metric relating to the IC design is updated based on the modified second slack. The IC design is configured to be used to fabricate an IC.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Abstract: A signal generating circuit includes the following: a clock circuit, configured to receive an external clock signal to generate an internal clock signal; a controlling circuit, configured to generate a control signal according to the frequency of the external clock signal; and a generating circuit, connected with the clock circuit and the controlling circuit respectively, and configured to receive the internal clock signal, the control signal and a flag signal to generate a target signal. When the flag signal changes from a first level to a second level, the target signal is changed from a third level to a fourth level, and after the target signal maintains the fourth level for a target time length, the target signal is changed from the fourth level to the third level. The generating circuit is further configured to determine the target time length according to the internal clock signal and the control signal.

Abstract: A method, computer program product, and computing system for defining a library of functional modules; enabling a user to select a plurality of functional modules from the library of functional modules; and enabling the user to visually arrange the plurality of functional modules to form a conversational application.

Abstract: Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: Embodiments herein include detecting a transformation in a circuit layout before clock tree synthesis is performed, and in response, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit. Moreover, the embodiments includes determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit and adjusting the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Abstract: An equivalent input characterization waveform (EICW) is determined for a channel-connected block (CCB) located on a boundary of a cell, for a specific waveform of interest. The EICW and the specific waveform of interest produce a same timing characteristic of the CCB, but the EICW belongs to a set of waveforms on which a behavioral timing model for the multi-stage cell is based whereas the specific waveform of interest is not so limited. A timing response of the multi-stage cell is then estimated based on applying the EICW.

Abstract: A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.

Abstract: Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: at least one programmable logic circuit to execute a function programmed with a bitstream; a self-test circuit to execute a self-test at a first voltage, the self-test and the first voltage programmed with first metadata associated with the bitstream, the self-test including at least one critical path length of the function; and a power controller to identify an operating voltage for the at least one programmable logic circuit based at least in part on the execution of the self-test at the first voltage.

Abstract: A method, computer program product, and computing system for defining a library of functional modules; enabling a user to select a plurality of functional modules from the library of functional modules; and enabling the user to visually arrange the plurality of functional modules to form a conversational application.

Abstract: A method for minimizing the skew (balancing) between all paths arriving at the inputs ports of each gate within a given combinatorial circuit.

Abstract: Simulator includes a first core unit corresponding to the first simulation model, a second core unit corresponding to the second simulation model, a slave block unit for communicating with one of the first core unit and the second core unit, the first core unit and the second core unit and a simulation control unit for causing either to execute instructions. The first core unit includes a high-speed mode instruction execution control unit that stops executing subsequent instructions in response to a request for switching from the first simulation model to the second simulation model, and a transaction monitor unit that monitors whether or not the transaction processing between the first core unit and the slave block unit has been completed. The simulation control unit causes the second core unit to execute instructions in response to a notification of completion of the transaction processing from the transaction monitor unit.

Abstract: A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.

Abstract: A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

Abstract: In an approach, a processor receives an input indicative of a set of registers, the set of registers being configured for obtaining output data from a design-under-test (DUT) in a field-programmable gate array (FPGA) module. A processor executes a set of instructions for monitoring the output data in the set of registers;. A processor generates data indicative of at least one portion of changes of the output data in the set of registers during the execution of the set of instructions. A processor causes a separate machine to analyze the data via utilizing an interface to send the data to the separate machine.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Abstract: Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.

Abstract: A method comprising categorizing nodes of a fabricated circuit as being priority nodes and nodes as being inferior nodes; evaluating a first priority node by automatically designating for verification the first priority node, and ascertaining whether a measured signal from the first priority node meets a pass-fail criterion for the first priority node; evaluating, when the measured signal from the first priority node meets the pass-fail criterion, a second priority node by automatically designating for verification the second priority node, and ascertaining whether a measured signal from the second priority node meets a pass-fail criterion for the second priority node; and evaluating, when the measured signal from the first priority node does not meet the pass-fail criterion, a first inferior node, by automatically designating for verification the first inferior node, and ascertaining whether a measured signal from the first inferior node meets a pass-fail criterion for the first inferior node.

Abstract: Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.

Abstract: The present disclosure is directed to a method and system for hierarchical multi-scale design with the aid of a digital computer. A hierarchical representation of a shape and material distribution is constructed which satisfies a top-level constraint at a top-level of representation. Properties for families of designs at each of the lower levels of representation that satisfy additional constraints link each of the lower levels of representation to at least a next higher level of the representation.

Abstract: A clock sweeping system includes multiple delay elements and a selection circuit. The delay elements are configured to generate multiple delayed clock signals. Each delay element is configured to receive an input signal and delay the input signal to generate a corresponding first delayed clock signal. The input signal is one of a first clock signal, a second clock signal, and a corresponding output signal generated by a previous delay element. The selection circuit is configured to select and output, based on a first select signal for a plurality of times, a corresponding second delayed clock signal as a first output clock signal. The selection circuit is further configured to select and output, based on a second select signal, one of the first and second clock signals as a second output clock signal. The first output clock signal is asynchronous with respect to the second output clock signal.

Abstract: A method includes performing, using a processor, a synthesis operation to generate a netlist from input data about an integrated circuit, placing and routing, using the one processor, standard cells defining the integrated circuit using the netlist, to generate layout data and wire data, extracting, using the processor, parasitic components from the layout data, and performing, using the processor, timing analysis of the integrated circuit according to timing constraints, based on the layout data and the wire data.

Abstract: A storage element that is operable based on a system clock signal, the storage element including a clock gating circuitry configured to generate a gated clock signal based on at least one Boolean signal and the system clock signal or a preprocessed system clock signal, wherein the clock gating circuitry comprises physical connections of small capacitance such that tapping of at least one of the physical connections results in a hold-time violation. Also, a hardware-based cryptography accelerator or a secured processing system including at least one such storage element, and a method for operating at least one storage element.