Combined With Field Effect Transistor Patents (Class 257/133)
  • Patent number: 10431598
    Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stuart B. Molin, Michael A. Stuber
  • Patent number: 10424642
    Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 24, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
  • Patent number: 10403727
    Abstract: To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 3, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tsutomu Ina, Yukihisa Ueno, Tohru Oka
  • Patent number: 10403748
    Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n? type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 3, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 10388656
    Abstract: A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 20, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10388773
    Abstract: A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 20, 2019
    Assignee: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Shigeki Takahashi
  • Patent number: 10373946
    Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu
  • Patent number: 10373919
    Abstract: A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuhiko Asai
  • Patent number: 10347754
    Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
  • Patent number: 10283475
    Abstract: A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current flowing in a first direction. A second substrate is operatively connected to the first substrate and includes a fourth layer, fifth layer and a sixth layer. A conductive joining layer connects the third layer of the first substrate and the fourth layer of the second substrate. The conductive joining layer may be a first sintered layer. The third layer of the first substrate, the first sintered layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction substantially opposite to the first direction. The net inductance is reduced by a cancellation effect of the switch current going in opposite directions.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 7, 2019
    Assignee: GM Global Technology Operations LLC
    Inventors: Terence G. Ward, Constantin C. Stancu, Marko Jaksic
  • Patent number: 10269652
    Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10262948
    Abstract: A semiconductor module manufacturing method, including preparing an external terminal that is of a pin shape and that has an outflow prevention portion formed on an outer surface portion thereof, attaching the external terminal to a substrate and electrically connecting the external terminal to the substrate, preparing a transfer molding die including a first mold portion and a second mold portion, which are combinable by attaching a parting surface of the first mold portion to a parting surface of the second mold portion, to thereby form a first cavity and a second cavity that are in communication with each other, combining the first and second mold portions to accommodate the substrate and the external terminal respectively in the first and second cavities, and to sandwich the outflow prevention portion between the first and second mold portions, and encapsulating the substrate by injecting resin into the first cavity.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomomi Nonaka
  • Patent number: 10243562
    Abstract: A voltage shifting circuit includes a first transistor in electrical parallel with a second transistor between an input node and an output node; a gate threshold capacitor disposed between the output node and a gate of the second transistor; and at least one of a) a downshift capacitor disposed between the input node and a drain/source of the first transistor, arranged to downshift a voltage from the input node and apply the downshifted voltage to the drain/source of the first transistor; and b) an upshift capacitor disposed between the input node and a drain/source of the second transistor, arranged to upshift a voltage from the input node and apply the upshifted voltage to the drain/source of the second transistor. This circuit is advantageously directly coupled to an input or output node of a non-complementary logic gate, of which multiple instances can be deployed in display circuitry or solar panels.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Patent number: 10170606
    Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 1, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Kohei Shinsho
  • Patent number: 10158013
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a silicon carbide drift layer, a buried silicon carbide layer and an oxide semiconductor layer; the buried silicon carbide layer is located within the silicon carbide drift layer and the buried silicon carbide layer is covered by the oxide semiconductor layer. Therefore, breakdown behavior and/or long-time reliability of the semiconductor device may be further improved.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hiroshi Shikauchi, Satoru Washiya, Youhei Ohno, Tomonori Hotate, Hiromichi Kumakura
  • Patent number: 10153324
    Abstract: A CCD with an internal heterostructure well to store the photogenerated carriers is realized by using barrier and absorber semiconductors with a type-II band alignment in nBn or pBp photodetectors to form a specific barrier configured to confine the depletion region and a well to trap and store the photogenerated minority carriers. Depending on the spectral regime, (InAs/InAsSb)/(InAs/AlGaSb) superlattices can be used in the infrared, Si/Ge or AlP/GaP in the visible portion of optical spectrum, and GaN/ZnO in the UV portion. The resulting device not only leverages the advantages of the conventional CCD (such as in-pixel signal integration to suppress the noise), but also boasts an advantageously low operational voltage, thereby ensuring the low power consumption and low band-to-band tunneling current/noise (in particular, for use as an infrared photodetector).
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 11, 2018
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Zhaoyu He, Yong-Hang Zhang
  • Patent number: 10134736
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 20, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10134888
    Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Nao Nagata
  • Patent number: 10121715
    Abstract: A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect the connection terminals, tips of the connection terminals protruding from the jig. The method further includes fitting a printed circuit board on the tips of the connection terminals protruding from the jig.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yo Sakamoto
  • Patent number: 10068972
    Abstract: A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first conductive type, wherein the drift region is in contact with the trench gate; a body region of a second conductive type, wherein the body region is disposed above the drift region and is in contact with the trench gate; a source region of the first conductive type, wherein the source region is disposed above the body region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate; and a front surface region of the second conductive type, wherein the front surface region is disposed above the source region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Sachiko Aoi, Shoji Mizuno, Shinichiro Miyahara
  • Patent number: 10063048
    Abstract: Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 28, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeremy C. Smith
  • Patent number: 10056499
    Abstract: An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 21, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman
  • Patent number: 10049750
    Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • Patent number: 10043894
    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 7, 2018
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Jan Willem Slotboom, Dirk Klaassen
  • Patent number: 10032903
    Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ethan Williford
  • Patent number: 10020308
    Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: July 10, 2018
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10008491
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Robert J. Gauthier, Jr., Souvick Mitra, Mickey Yu
  • Patent number: 10002953
    Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 19, 2018
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventor: Nao Nagata
  • Patent number: 9997602
    Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Matteo Dainese, Christian Jaeger
  • Patent number: 9905686
    Abstract: In a plane view of the front surface of the semiconductor substrate, the source region and the first contact region are arranged adjacent to each other in a direction along the gate trench in an area being in contact with a side surface of the gate trench, and the second contact region is arranged adjacent to the source region and the first contact region in an area apart from the gate trench. The impurity concentration of the first contact region is lower than the impurity concentration of the second contact region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: February 27, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masahiro Sugimoto, Yukihiko Watanabe, Shinichiro Miyahara
  • Patent number: 9899502
    Abstract: A bipolar junction transistor layout structure includes a first emitter including a pair of first sides and a pair of second sides, a pair of collectors disposed at the first sides of the first emitter, and a pair of bases disposed at the second sides of the first emitter. The first sides are perpendicular to the second sides. The first emitter is disposed in between the pair of collectors and in between the pair of bases.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yuan-Heng Tseng
  • Patent number: 9893211
    Abstract: Provided is a semiconductor device manufacturing method. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita
  • Patent number: 9859278
    Abstract: An apparatus including a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Robert S. Chau
  • Patent number: 9837531
    Abstract: A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 5, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 9793386
    Abstract: A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state. The device is configured such that the switching loss is different between at least two of the zones. Further, the device is configured such that zones having greater switching losses transition to the non-conducting state before zones having lesser switching losses.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: October 17, 2017
    Assignee: Ford Global Technologies, LLC
    Inventor: Ming Su
  • Patent number: 9786746
    Abstract: A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: October 10, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo
  • Patent number: 9780187
    Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 3, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Ikegami, Tsuyoshi Kachi
  • Patent number: 9773883
    Abstract: A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: September 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Akitaka Soeno, Yuichi Takeuchi, Narumasa Soejima
  • Patent number: 9773923
    Abstract: Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita
  • Patent number: 9761295
    Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 12, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Colin Stewart Bill, Harry Luan
  • Patent number: 9761700
    Abstract: Systems and methods are disclosed for processing radio frequency (RF) signals using one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: September 12, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Michael Joseph McPartlin
  • Patent number: 9748361
    Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 29, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
  • Patent number: 9735291
    Abstract: A semiconductor device includes a substrate; a well region of a first-conductivity-type, disposed in the substrate; a first impurity region of a first-conductivity-type disposed in the well region; a second impurity region of the second-conductivity-type disposed in the well region, the second-conductivity-type being opposite to the first-conductivity-type; a third impurity region disposed in the well region, a portion of the first impurity region overlapping a first portion of the third impurity region, a portion of the second impurity region overlapping a second portion of the third impurity region, and a third portion of the third impurity region being disposed between the first impurity region and the second impurity region; and a fourth impurity region and a barrier layer disposed in the substrate, the fourth impurity region and the barrier layer enclosing the well region from around and below, respectively.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 15, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Ming Chiou, Yu-Jui Chang, Cheng-Chi Lin
  • Patent number: 9686890
    Abstract: A structure for efficiently transferring heat generated from an electronic part or the like to a heat dissipation member is provided. A bus bar is used for a wiring pattern in an electronic device (60), such as a power line (2), a GND line (6) and the like. A heat transfer member (25) is held between a first bus bar that is a power line (2) connected to an electronic part and a second bus bar that is a GND line (6) connected to a heat dissipation member (7) to configure a heat dissipation structure in which heat generated from the electronic part is transferred through the power line (2), the heat transfer member (25) and the GND line (6) to the heat dissipation member (7).
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: June 20, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shingo Akamatsu, Mitsuo Sone
  • Patent number: 9685335
    Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: June 20, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Kyu-hyun Lee, Young-chul Kim, Kyeong-seok Park, Bong-yong Lee, Young-chul Choi
  • Patent number: 9685949
    Abstract: An ESD protection circuit is connected in parallel to a MIM capacitor between a first terminal and a second terminal. First Schottky diodes are connected in series to each other and have anodes connected on the first terminal side and cathodes connected on the second terminal side. Second Schottky diodes are connected in series to each other and connected in anti-parallel to the first Schottky diodes. When an RF signal is inputted to neither the first terminal nor the second terminal, the first terminal has a higher DC voltage than that of the second terminal. The number of the first Schottky diodes is greater than the number of the second Schottky diodes. The number of the second Schottky diodes is set such that an amplitude of the RF signal does not attenuate to predetermined amplitude of the RF signal when the RF signal passes through the MIM capacitor.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: June 20, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Miyo Miyashita, Suguru Maki
  • Patent number: 9666579
    Abstract: In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 30, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Akitaka Soeno, Yasuhiro Hirabayashi, Takashi Kuno, Yusuke Yamashita, Satoru Machida
  • Patent number: 9660044
    Abstract: A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor, a body drive stage to manufacture the body region of the power field effect transistor is shortened to obtain a relatively low on resistance for the power field effect transistor. Before the implanting stage of the dopants of the body region, a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer of the power field effect transistor are oxidized to obtain a power field effect transistor which has at the sidewalls an oxidized polysilicon layer that is thick enough to prevent a premature current injection from the gate to the source regions of the power field effect transistor.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 23, 2017
    Assignee: NXP USA, Inc.
    Inventors: Jean Michel Reynes, Graeme John Anderson, Pierre Jalbaud, Dale Neil Vaughan
  • Patent number: 9640610
    Abstract: An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 2, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Hamada, Naruhisa Miura
  • Patent number: RE47641
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa