Combined With Field Effect Transistor Patents (Class 257/133)
  • Patent number: 10892351
    Abstract: A semiconductor device includes a first semiconductor region of first conductivity type, a second semiconductor region of second conductivity type, a third semiconductor region of second conductivity type, a first electrode, a fourth semiconductor region of second conductivity type, a fifth semiconductor region of first conductivity type, a gate electrode, a sixth semiconductor region of second conductivity type, and second and third electrodes. The second and third semiconductor regions are formed below the first semiconductor region. A second conductivity type carrier concentration of the third semiconductor region is lower than that of the second semiconductor region. The gate electrode faces the fourth semiconductor region. The sixth semiconductor region is formed above the first semiconductor region and is located above the third semiconductor region.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 12, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tomohiro Tamaki
  • Patent number: 10848076
    Abstract: In a rectifying circuit including a HEMT and a diode connected antiparallel to the HEMT, a forward voltage drop when the diode starts to be conductive is made smaller than a voltage drop when the HEMT is reverse-conductive in an OFF state corresponding to an amount of rectified current when the HEMT is reverse-conductive in an ON state, inductance of a pathway extending through the diode is made larger than inductance of a pathway extending through the HEMT among the pathways connecting a source terminal and a drain terminal of the HEMT, and an amount of charge accumulated in a parasitic capacitance of the diode is made smaller than an amount of charge accumulated in an output capacitance of the HEMT. With this, there is provided a rectifying circuit in which switching loss due to the charge accumulated in the output capacitance of the HEMT is reduced.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Takeshi Shiomi
  • Patent number: 10833064
    Abstract: An ESD protection circuit and integrated circuit for a broadband circuit are disclosed. The ESD protection circuit includes a silicon-controlled rectifier, an inductor and a trigger unit. The silicon-controlled rectifier is formed by four semiconductor materials and includes a first end, a second end and a third end. The first end is coupled with a first P-type semiconductor material and a signal input end. The second end is coupled with a second N-type semiconductor material. The third end is coupled with a second P-type semiconductor material. One end of the inductor is coupled with the signal input end and the first end, and the other end thereof is coupled with a signal output end and a high-frequency circuit. One end of the trigger unit is coupled with the signal output end and the high-frequency circuit, and the other end thereof is coupled with the third end.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 10, 2020
    Assignee: National Taiwan Normal University
    Inventors: Chun-Yu Lin, Yu-Hsuan Lai
  • Patent number: 10811306
    Abstract: A preparation method of a multilayer monocrystalline silicon film sequentially includes: first, taking two monocrystalline silicon slices of which surfaces are clean, processing the surfaces of the silicon slices by a plasma activation technology, and then, performing pre-bonding; transferring the bonded silicon slices to an annealing furnace having a temperature of 200-300° C., and performing annealing for 6-10 hours to avoid generating a transition region and to completely bond the two silicon slices; thinning the annealed bonded slices to a desired target thickness; and taking the thinned SOI slice as Si-1, taking another monocrystalline silicon slice as Si-2, and performing the first three steps on Si-1 and Si-2 to obtain the multilayer monocrystalline silicon film. The silicon slices that are processed by the plasma activation technology have a large pre-bonding force during bonding. A favorable bonding effect is achieved after annealing.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Shenyang Silicon Technology Co., Ltd.
    Inventor: Qisen Dang
  • Patent number: 10707299
    Abstract: The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 7, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 10700053
    Abstract: An electrostatic protection element includes a substrate of a first conductivity type, an epitaxial layer formed on the substrate, the epitaxial layer being of a second conductivity type; a well formed on the epitaxial layer, the well being of the first conductivity type; a transistor formed inside of the well, the transistor including a drain region, a source region formed to face the drain region across a channel region, and a gate formed above the channel region so as to be insulated; and a well contact region of the first conductivity type disposed so as to form an opposing region where the drain region and the well contact region face each other while being separated by a prescribed distance in a direction parallel to at least an extension direction of the gate.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: June 30, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hisao Ohtake
  • Patent number: 10665690
    Abstract: A gate-controlled bipolar junction transistor includes a substrate, an emitter region, a base region disposed on one side of the emitter region, and a collector region disposed on one side of the base region and being opposite to the emitter region. The emitter region includes first fin structures, first metal gates extending across the first fin structures, and an emitter contact plug on the first fin structures. A gate contact region is disposed between the emitter region and the base region. Each of the first metal gates includes an extended contact end portion protruding toward the base region. The extended contact end portion is disposed within the gate contact region. A gate contact is disposed on the extended contact end portion.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Wei Pan, Sheng Cho
  • Patent number: 10658353
    Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak Ning
  • Patent number: 10658359
    Abstract: A semiconductor device, which is a diode, includes the following: an n cathode layer, which is an n-type region, disposed in a surface layer of a semiconductor substrate; a p cathode layer, which is a p-type region, disposed in the surface layer; and a cathode electrode, which is a metal electrode, in contact with both of the n cathode layer and the p cathode layer. The cathode electrode includes a first metal layer in contact with both of the n cathode layer and the p cathode layer, and a second metal layer disposed on the first metal layer. A contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than the oxygen concentration of a contact surface between the first metal layer, and the n cathode layer and the p cathode layer.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Tanaka, Fumihito Masuoka
  • Patent number: 10636473
    Abstract: Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 28, 2020
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10629732
    Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi
  • Patent number: 10593730
    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
  • Patent number: 10541241
    Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 21, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10516065
    Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 24, 2019
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Philipp Seng, Armin Willmeroth
  • Patent number: 10510904
    Abstract: A p type anode layer is formed on a front surface of an n type drift layer in an active region. An n type buffer layer is formed on a rear surface of the n? type drift layer. An n type cathode layer and a p type cathode layer are formed side by side on a rear surface of the n type buffer layer. An n type layer is formed on the rear surface of the n type buffer layer in a boundary region between the active region and the terminal region side by side with the n type cathode layer and the p type cathode layer. An extending distance of the n type layer to the active region side with an end portion of the active region as a starting point is represented by WGR1, and WGR1 satisfies 10 ?m?WGR1?500 ?m.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihito Masuoka, Hidenori Fujii
  • Patent number: 10510843
    Abstract: An insulated gate silicon carbide semiconductor device includes: a drift layer of a first conductivity type on a silicon carbide substrate of 4H type with a {0001} plane having an off-angle of more than 0° as a main surface; a first base region; a source region; a trench; a gate insulating film; a protective diffusion layer; and a second base region. The trench sidewall surface in contact with the second base region is a surface having a trench off-angle of more than 0° in a <0001> direction with respect to a plane parallel to the <0001> direction. The insulated gate silicon carbide semiconductor device can relieve an electric field of a gate insulating film and suppress an increase in on-resistance and provide a method for manufacturing the same.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 17, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuhiro Kagawa, Rina Tanaka, Yutaka Fukui, Naruhisa Miura, Yuji Abe, Masayuki Imaizumi
  • Patent number: 10504994
    Abstract: Provided is a power semiconductor device and a fabrication method thereof are provided. The power semiconductor device includes: a first epitaxial layer; a collector layer formed on one side of the first epitaxial layer; and a second epitaxial layer formed on another side of the first epitaxial layer, the first epitaxial layer having a higher doping concentration than the second epitaxial layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: December 10, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Ho Hyun Kim, Seung Bae Hur, Seung Wook Song, Jeong Hwan Park, Ha Yong Yang, In Su Kim
  • Patent number: 10483357
    Abstract: A semiconductor device including: a semiconductor substrate having a drift region of the first conductivity type; a cathode region formed on the lower surface of the semiconductor substrate; a diode portion having the cathode region formed on the lower surface of the semiconductor substrate; the first dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, including one part provided inside the diode portion and the other part provided outside the diode portion, and provided extending in series from inside the diode portion to outside the diode portion in a predetermined extending direction on the upper surface of the semiconductor substrate; and the first lead-out portion that is provided on the upper surface of the semiconductor substrate, and electrically connected to the first dummy trench portion outside the diode portion is provided.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mutsumi Kitamura, Tohru Shirakawa
  • Patent number: 10461181
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: October 29, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae Kim
  • Patent number: 10453538
    Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • Patent number: 10446673
    Abstract: A lateral insulated gate bipolar transistor (LIGBT) and method for eliminating the transistor tail current. The lateral insulated gate bipolar transistor comprises the silicon substrate, the buried oxide, and the drift region, the channel region, ohm-contact-high-doping region, the cathode, the gate dielectric, the anode contact, the gate, the cathode contact, the anode, which are placed above the silicon substrate, the electric field intensifier is placed at the upper surface of the drift region between the anode and the channel region to generate an electric field that starts from anode and points to the bottom surface of the electric field intensifier. The electric field intensifier is isolated from the drift region by the dielectric. The invention realizes performance improvements for both the conduction and the switching behaviors of the LIGBT device.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 15, 2019
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventor: Junhong Li
  • Patent number: 10431598
    Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Stuart B. Molin, Michael A. Stuber
  • Patent number: 10424642
    Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 24, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
  • Patent number: 10403748
    Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n? type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 3, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 10403727
    Abstract: To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 3, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tsutomu Ina, Yukihisa Ueno, Tohru Oka
  • Patent number: 10388773
    Abstract: A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 20, 2019
    Assignee: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Shigeki Takahashi
  • Patent number: 10388656
    Abstract: A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 20, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10373946
    Abstract: Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu
  • Patent number: 10373919
    Abstract: A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuhiko Asai
  • Patent number: 10347754
    Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Christian Jaeger, Johannes Georg Laven, Max Christian Seifert, Antonio Vellei
  • Patent number: 10283475
    Abstract: A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current flowing in a first direction. A second substrate is operatively connected to the first substrate and includes a fourth layer, fifth layer and a sixth layer. A conductive joining layer connects the third layer of the first substrate and the fourth layer of the second substrate. The conductive joining layer may be a first sintered layer. The third layer of the first substrate, the first sintered layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction substantially opposite to the first direction. The net inductance is reduced by a cancellation effect of the switch current going in opposite directions.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: May 7, 2019
    Assignee: GM Global Technology Operations LLC
    Inventors: Terence G. Ward, Constantin C. Stancu, Marko Jaksic
  • Patent number: 10269652
    Abstract: An nFET vertical transistor is provided in which a p-doped top source/drain structure is formed in contact with an n-doped semiconductor region that is present on a topmost surface of a vertical nFET channel. The p-doped top source/drain structure is formed utilizing a low temperature (550° C. or less) epitaxial growth process.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10262948
    Abstract: A semiconductor module manufacturing method, including preparing an external terminal that is of a pin shape and that has an outflow prevention portion formed on an outer surface portion thereof, attaching the external terminal to a substrate and electrically connecting the external terminal to the substrate, preparing a transfer molding die including a first mold portion and a second mold portion, which are combinable by attaching a parting surface of the first mold portion to a parting surface of the second mold portion, to thereby form a first cavity and a second cavity that are in communication with each other, combining the first and second mold portions to accommodate the substrate and the external terminal respectively in the first and second cavities, and to sandwich the outflow prevention portion between the first and second mold portions, and encapsulating the substrate by injecting resin into the first cavity.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomomi Nonaka
  • Patent number: 10243562
    Abstract: A voltage shifting circuit includes a first transistor in electrical parallel with a second transistor between an input node and an output node; a gate threshold capacitor disposed between the output node and a gate of the second transistor; and at least one of a) a downshift capacitor disposed between the input node and a drain/source of the first transistor, arranged to downshift a voltage from the input node and apply the downshifted voltage to the drain/source of the first transistor; and b) an upshift capacitor disposed between the input node and a drain/source of the second transistor, arranged to upshift a voltage from the input node and apply the upshifted voltage to the drain/source of the second transistor. This circuit is advantageously directly coupled to an input or output node of a non-complementary logic gate, of which multiple instances can be deployed in display circuitry or solar panels.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wilfried Ernst-August Haensch, Bahman Hekmatshoartabari
  • Patent number: 10170606
    Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 1, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Kohei Shinsho
  • Patent number: 10158013
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a silicon carbide drift layer, a buried silicon carbide layer and an oxide semiconductor layer; the buried silicon carbide layer is located within the silicon carbide drift layer and the buried silicon carbide layer is covered by the oxide semiconductor layer. Therefore, breakdown behavior and/or long-time reliability of the semiconductor device may be further improved.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Hiroshi Shikauchi, Satoru Washiya, Youhei Ohno, Tomonori Hotate, Hiromichi Kumakura
  • Patent number: 10153324
    Abstract: A CCD with an internal heterostructure well to store the photogenerated carriers is realized by using barrier and absorber semiconductors with a type-II band alignment in nBn or pBp photodetectors to form a specific barrier configured to confine the depletion region and a well to trap and store the photogenerated minority carriers. Depending on the spectral regime, (InAs/InAsSb)/(InAs/AlGaSb) superlattices can be used in the infrared, Si/Ge or AlP/GaP in the visible portion of optical spectrum, and GaN/ZnO in the UV portion. The resulting device not only leverages the advantages of the conventional CCD (such as in-pixel signal integration to suppress the noise), but also boasts an advantageously low operational voltage, thereby ensuring the low power consumption and low band-to-band tunneling current/noise (in particular, for use as an infrared photodetector).
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: December 11, 2018
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Zhaoyu He, Yong-Hang Zhang
  • Patent number: 10134888
    Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Nao Nagata
  • Patent number: 10134736
    Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 20, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Le-Tien Jung
  • Patent number: 10121715
    Abstract: A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect the connection terminals, tips of the connection terminals protruding from the jig. The method further includes fitting a printed circuit board on the tips of the connection terminals protruding from the jig.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: November 6, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yo Sakamoto
  • Patent number: 10068972
    Abstract: A semiconductor device is provided with a semiconductor substrate and a trench gate. The semiconductor substrate is provided with a drift region of a first conductive type, wherein the drift region is in contact with the trench gate; a body region of a second conductive type, wherein the body region is disposed above the drift region and is in contact with the trench gate; a source region of the first conductive type, wherein the source region is disposed above the body region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate; and a front surface region of the second conductive type, wherein the front surface region is disposed above the source region, exposed on the front surface of the semiconductor substrate and is in contact with the trench gate.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 4, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masahiro Sugimoto, Sachiko Aoi, Shoji Mizuno, Shinichiro Miyahara
  • Patent number: 10063048
    Abstract: Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 28, 2018
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeremy C. Smith
  • Patent number: 10056499
    Abstract: An electronic device comprising a bidirectional JFET can include a drain/source region; a lightly doped semiconductor layer overlying the drain/source region; a source/drain region overlying the lightly doped semiconductor layer; a trench extending through the source/drain region and into the lightly doped semiconductor layer; a gate electrode of the bidirectional JFET within the trench; and a field electrode within the trench. A process of forming an electronic device can include providing a workpiece including a first doped region and a lightly doped semiconductor layer overlying the first doped region; defining a trench extending into the lightly doped semiconductor layer; forming a gate electrode within the trench, wherein the gate electrode extends to a sidewall of the trench; and forming a field electrode within the trench, wherein a bidirectional JFET includes the first doped region, the lightly doped semiconductor layer, a second doped region, and the gate electrode.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 21, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman
  • Patent number: 10049750
    Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Mark Hawes, Toru Tanzawa, Jeremy Binfet
  • Patent number: 10043894
    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 7, 2018
    Assignee: NXP B.V.
    Inventors: Viet Thanh Dinh, Tony Vanhoucke, Evelyne Gridelet, Anco Heringa, Jan Willem Slotboom, Dirk Klaassen
  • Patent number: 10032903
    Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 24, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Ethan Williford
  • Patent number: 10020308
    Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: July 10, 2018
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Bruce L. Bateman, Valery Axelrad, Charlie Cheng
  • Patent number: 10008491
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance electrostatic discharge (ESD) devices and methods of manufacture. The structure includes: a first structure comprising a pattern of a first diffusion region, a second diffusion region and a third diffusion region partly extending over a first well; and a second structure comprising a fourth diffusion region in a second well electrically connecting to the first structure to form a silicon controlled rectifier (SCR) on a bulk region of a substrate.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: You Li, Robert J. Gauthier, Jr., Souvick Mitra, Mickey Yu
  • Patent number: 10002953
    Abstract: A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 19, 2018
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventor: Nao Nagata
  • Patent number: RE47641
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Yamaguchi, Wataru Saito, Ichiro Omura, Masaru Izumisawa