Method of Controlled Cell-Level Fusing Within a Battery Pack
A method is provided that achieves improved battery pack performance, system reliability and system safety while impacting only a small region of the battery pack/battery module, and thus having only a minor impact on battery pack cost, complexity, weight and size. The battery pack/battery module is designed such that the fusible interconnects associated with a single battery, or a specific fusible interconnect associated with a single battery, will be the last interconnect(s) to fuse during a short circuit event. The risk of sustained arcing for the predetermined interconnect(s) is minimized through the use of rapid clearing interconnects. As a result, the risk of damage and excessive heating is also minimized.
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This application is a continuation of U.S. patent application Ser. No. 12/850,282, filed Aug. 4, 2010, the disclosure of which is incorporated herein by reference for any and all purposes.
FIELD OF THE INVENTIONThe present invention relates generally to battery packs and, more particularly, to a battery pack that is designed to mitigate the effects of arcing during a short circuit.
BACKGROUND OF THE INVENTIONArcing is a well-known phenomena that results when the current in an electrical circuit is interrupted, wherein an arc is formed across the newly created gap in the circuit. If the arc is not quickly extinguished, for example by containment, cooling, insufficient voltage/current, etc., the intense heat generated by the arc may damage, if not combust, nearby materials and components. Accordingly, special precautions must be taken in the design of switches, relays, fuses and circuit breakers that are intended for use in high-power circuits. It is more difficult, however, to control unintended circuit interruptions that nevertheless may occur due to an inadvertent abusive situation (e.g., tool dropped on a battery pack; battery pack dropped; car crash which causes damage to the battery pack, etc.).
In a typical battery pack, fuses are used to mitigate the effects of an inadvertent short circuit. In some instances, the fuse is placed in series with one, or both, interconnects that couple the battery pack to the load (
Regardless of the approach used to provide circuit protection, it is desirable that the fusing element(s) of the circuit fuse quickly enough to avoid damage or excessive heating of adjacent cells/components. This is especially desirable in battery packs utilizing a large number of cells packed closely together as excessive heating may quickly initiate thermal runaway in one or more cells. During a thermal runaway event, a large amount of thermal energy is rapidly released, heating the entire cell up to a temperature of 900° C. or more. Due to the increased temperature of the cell undergoing thermal runaway, the temperature of adjacent cells within the battery pack will also increase, an effect that is exacerbated by the close packing of cells in a large battery pack. If the temperature of these adjacent cells is allowed to increase unimpeded, they may also enter into a state of thermal runaway, leading to a cascading effect that may propagate throughout the entire battery pack. As a result, not only is power from the battery pack interrupted, but the system employing the battery pack is more likely to incur extensive collateral damage due to the scale of thermal runaway and the associated release of thermal energy.
In a battery pack in which the cells are connected in parallel, as illustrated in
The present invention provides a battery pack, or battery pack module, that achieves improved battery pack performance, system reliability and system safety while impacting only a small region of the battery pack/battery module, and thus having only a minor impact on battery pack cost, complexity, weight and size. The battery pack/battery module is designed such that the fusible interconnects associated with a single battery, or a specific fusible interconnect associated with a single battery, will be the last interconnect(s) to fuse during a short circuit event. The risk of sustained arcing for the predetermined interconnect(s) is minimized through the use of rapid clearing interconnects. As a result, the risk of damage and excessive heating is also minimized.
In one aspect of the invention, a method of controlling arc formation within a battery pack is provided, where the battery pack includes a plurality of cells arranged in a parallel configuration, a first collector plate and a second collector plate. The method further includes the steps of (i) selecting a first impedance for a first plurality of fusible interconnects and electrically coupling a first terminal of each of the plurality of cells, except for a first cell, to the first collector plate, (ii) selecting a second impedance for a second plurality of fusible interconnects and electrically coupling a second terminal of each of the plurality of cells, except for the first cell, to the second collector plate, (iii) selecting a third impedance, lower than the first and second impedances, for a first fusible interconnect and electrically coupling a first terminal of the first cell to the first collector plate, wherein the first fusible interconnect is not one of the first and second pluralities of interconnects, (iv) selecting a fourth impedance, lower than the first and second impedances, for a second fusible interconnect and electrically coupling a second terminal of the first cell to the second collector plate, wherein the second fusible interconnect is not one of the first and second pluralities of interconnects, and (v) implementing an arc suppression system with the first cell. The arc suppression system may be applied to both the first and second fusible interconnects, or only the first fusible interconnect, depending at least in part on whether the first and second fusible interconnects have the same impedance or the first fusible interconnect has a lower impedance than the second fusible interconnect. The arc suppression system implementing step may include the steps of (i) positioning one or both fusible interconnects within an electrically non-conductive isolation structure; (ii) positioning both fusible interconnects as well as the first cell within an electrically non-conductive isolation structure; (iii) coating one or both fusible interconnects with an electrically non-conductive material; (iv) drawing current away from an arc formed when the fusible interconnect fuses during a short circuit event; (v) deflecting and extending the arc length of an arc formed when the fusible interconnect fuses during a short circuit event; and (vi) interposing a contact block(s) between the first cell and the collector plate(s), where the contact block(s) is connected to the collector plate(s) with a secondary fusible interconnect that has a lower impedance than the fusible interconnect. The method may further include the steps of configuring one or both collector plates with rapid ablation pathways. The impedance selecting steps of the method may further include the steps of (i) selecting particular interconnect lengths to achieve the desired impedances; (ii) selecting particular interconnect thicknesses to achieve the desired impedances; and/or (iii) varying the number of interconnects to achieve the desired impedances.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
In the following text, the terms “battery”, “cell”, and “battery cell” may be used interchangeably and may refer to any of a variety of different cell types, chemistries and configurations including, but not limited to, lithium ion (e.g., lithium iron phosphate, lithium cobalt oxide, other lithium metal oxides, etc.), lithium ion polymer, nickel metal hydride, nickel cadmium, nickel hydrogen, nickel zinc, silver zinc, or other battery type/configuration. The term “battery pack” as used herein refers to multiple individual batteries contained within a single piece or multi-piece housing, the individual batteries electrically interconnected to achieve the desired voltage and capacity for a particular application. The terms “electrical impedance” and “impedance” may be used interchangeably herein with both terms referring to the electrical impedance of the component in question. The term fusible interconnect as used herein refers to battery interconnect, typically a wire bond, that is designed to allow the expected current to pass without significant heating, but which will fuse in an overcurrent condition such as would be expected during a short circuit. Such a fusible interconnect is described in detail in co-assigned U.S. Pat. No. 7,671,565, the disclosure of which is incorporated herein for any and all purposes. It should be understood that identical element symbols used on multiple figures refer to the same component, or components of equal functionality. Additionally, the accompanying figures are only meant to illustrate, not limit, the scope of the invention and should not be considered to be to scale.
In accordance with the invention, a battery pack, or battery pack module, is designed so that a particular set of cell interconnects will fuse last during a short circuit event. The risk of sustained arcing for the predetermined interconnect(s) may then be minimized through the use of rapid clearing interconnects. As a result, the risk of damage, excessive heating, and the potential for thermal runaway, is also minimized. As described in detail below, there are many ways to predetermine which interconnect or set of interconnects will fuse last, and many ways to minimize the risk of sustained arcing in this predetermined interconnect(s).
The cells are connected to the collector plates using fusible interconnects, for example fusible wire bonds, that are designed to pass the expected current, but to fuse (i.e., break) during an overcurrent condition such as would be expected during a short circuit. In accordance with one embodiment of the invention, the interconnects (i.e., interconnects 309) used to connect all of the cells, but one, have substantially the same electrical and thermal characteristics. As a result, and similar to a conventional battery pack, the order in which interconnects 309 fuse during a short circuit event is unpredictable as the order will be determined by minor interconnect variations that arise during manufacturing, for example, minor variations in interconnect thickness, cross-section, etc. In this embodiment, one of the cells, e.g., cell 303z in
As previously noted, by designating a particular interconnect or pair of interconnects to be the last to fail during a short circuit event, the risk of sustained arcing may be minimized while requiring only minor changes to the overall design of the battery pack or battery module. In particular, only the designated interconnect(s) and potentially the region surrounding the designated interconnect(s) must be designed to minimize arcing. As a result, improved battery pack performance, system reliability and system safety may all be achieved while impacting only a small region of the battery pack/battery module, and thus having only a minor impact on battery pack cost, complexity, weight and size.
As the goal of the present invention is to minimize the risk of sustained arcing while minimizing the impact on battery pack design, it will be appreciated that limiting the arcing event to a single interconnect, rather than a pair of interconnects as shown in
It will be appreciated that there are numerous techniques that may be used to alter the impedance of a particular fusible interconnect, or a pair of interconnects, to insure that the selected interconnect(s) is the last to fuse among a group of interconnects corresponding to a group of parallel-arranged cells.
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In addition to varying the interconnect composition or dimensions as described above in order to control interconnect impedance, it should be understood that any of these techniques may also be used in combination with one another. For example, to achieve the desired impedance, both the thickness and length may be varied as illustrated in
As previously described, in addition to predetermining which cell interconnect(s) will fuse last during a short circuit event, the present invention utilizes a fusible interconnect and/or interconnect configuration that rapidly extinguishes any arcing that may occur when the last interconnect fuses. By reducing the risk of sustained arcing, the risk of collateral damage, excessive heating, and the potential for thermal runaway, is minimized. It will be appreciated that there are numerous applicable techniques that may be used to provide an interconnect that clears rapidly during fusing, therefore
One method of extinguishing the arc that may form when the last interconnect fuses is to design the collector plate and any surrounding conductive regions in such a way that the newly formed arc cannot be sustained, thus causing the arc to be extinguished before excessive damage may occur. For example, in the embodiment illustrated in
Another method of rapidly extinguishing the arc is to locate the interconnect in an isolated, non-conductive region that cannot support arc growth. In this approach, illustrated in
Another approach that may be used to extinguish the arc formed when the last interconnect fuses is illustrated in
In parallel with interconnect 1005 is a high voltage capacitor 1601 that is selected based on the expected operating voltage of the cells within this group of cells. As the interconnect fuses and the voltage begins to rise, and assuming the impedance of the capacitor is similar to or lower than the arc path, the capacitor will draw current away from the arc, thereby effectively extinguishing the arc. For example, assuming a 280 volt internal pack short with an arc that is sustained at 100 amps for 25 milliseconds, approximately 2.5 coulombs of charge pass through the arc. Therefore a 200 volt, 12.5 millifarad or less capacitor can be used in this example to mitigate the arc power so that the arc is not sustained.
As described above, one approach to extinguishing the arc formed when the interconnect fuses is to extend the arc length to a sufficient degree that it cannot be sustained. This approach is the basis for the embodiment illustrated in
In the embodiment illustrated in
In another embodiment illustrated in
Regardless of the technique used to extinguish the arc that is formed when the interconnect fuses, preferably one or more techniques are used to help mitigate the effects of arcing on the other cells within the battery pack/module. Techniques that may be used, either alone or in combination, include (i) providing additional space between the interconnect(s) that is preselected to fuse last along with the corresponding cell from the other cells in the group as illustrated in
As will be understood by those familiar with the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, while the invention has been described in terms of fusible interconnects and illustrated with cylindrical cells, the invention is not so limited. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.
Claims
1. A method of controlling arc formation within a battery pack, said battery pack comprised of a plurality of cells arranged in a parallel configuration, a first collector plate and a second collect plate, said method comprising the steps of:
- electrically coupling a first terminal of each of said plurality of cells, except for a first cell, to said first collector plate with a said first plurality of fusible interconnects;
- electrically coupling a second terminal of each of said plurality of cells, except for said first cell, to said second collector plate with a said second plurality of fusible interconnects;
- configuring a first fusible interconnect to fuse after said first plurality of fusible interconnects fuse and after said second plurality of fusible interconnects fuse, wherein said first fusible interconnect is not one of said first and second pluralities of interconnects;
- electrically coupling a first terminal of said first cell to said first collector plate with said first fusible interconnect;
- configuring a second fusible interconnect to fuse after said first plurality of fusible interconnects fuse and after said second plurality of fusible interconnects fuse, wherein said second fusible interconnect is not one of said first and second pluralities of interconnects;
- electrically coupling a second terminal of said first cell to said second collector plate with said second fusible interconnect; and
- implementing an arc suppression system with said first cell, wherein said arc suppression system is only implemented on said first cell of said plurality of cells.
2. The method of claim 1, wherein said step of implementing said arc suppression system further comprises the steps of positioning said first fusible interconnect within a first electrically non-conductive isolation structure and positioning said second fusible interconnect within a second electrically non-conductive isolation structure, wherein said first electrically non-conductive isolation structure separates said first fusible interconnect from said first plurality of fusible interconnects, and wherein said second electrically non-conductive isolation structure separates said second fusible interconnect from said second plurality of fusible interconnects.
3. The method of claim 2, wherein a single electrically non-conductive isolation structure is selected for said first and second electrically non-conductive isolation structure, wherein said method further comprises the step of positioning said first cell within said single electrically non-conductive isolation structure, and wherein said single electrically non-conductive isolation structure separates said first cell from said plurality of cells.
4. The method of claim 1, further comprising the step of configuring said first fusible interconnect to fuse after said second fusible interconnect, wherein said step of implementing said arc suppression system further comprises the step of positioning said first fusible interconnect within a first electrically non-conductive isolation structure, and wherein said first electrically non-conductive isolation structure separates said first fusible interconnect from said first plurality of fusible interconnects.
5. The method of claim 1, wherein said step of implementing said arc suppression system further comprises the step of coating said first and second fusible interconnects with an electrically non-conductive material.
6. The method of claim 1, further comprising the step of configuring said first fusible interconnect to fuse after said second fusible interconnect, and wherein said step of implementing said arc suppression system further comprises the steps of coating said first fusible interconnect with an electrically non-conductive material.
7. The method of claim 1, wherein during a short circuit event either said first fusible interconnect or said second fusible interconnect is last to fuse among said plurality of cells, and wherein said step of implementing said arc suppression system further comprises the step of drawing current away from an arc formed when said first or second fusible interconnect fuses, wherein said step of drawing current away extinguishes said arc.
8. The method of claim 1, further comprising the step of configuring said first fusible interconnect to fuse after said second fusible interconnect, wherein during a short circuit event said first fusible interconnect is last to fuse among said plurality of cells, and wherein said step of implementing said arc suppression system further comprises the step of drawing current away from an arc formed when said first fusible interconnect fuses, wherein said step of drawing current away extinguishes said arc.
9. The method of claim 1, wherein during a short circuit event either said first fusible interconnect or said second fusible interconnect is last to fuse among said plurality of cells, wherein an arc is formed when said first or second fusible interconnect fuses, and wherein said step of implementing said arc suppression system further comprises the step of deflecting and extending an arc length corresponding to said arc by exposing said arc to a magnetic field, wherein said step of deflecting and extending said arc length extinguishes said arc.
10. The method of claim 1, further comprising the step of configuring said first fusible interconnect to fuse after said second fusible interconnect, wherein during a short circuit event said first fusible interconnect is last to fuse among said plurality of cells, wherein an arc is formed when said first fusible interconnect fuses, and wherein said step of implementing said arc suppression system further comprises the step of deflecting and extending an arc length corresponding to said arc by exposing said arc to a magnetic field, wherein said step of deflecting and extending said arc length extinguishes said arc.
11. The method of claim 22, further comprising the steps of:
- interposing a first contact block between said first terminal of said first cell and said first collector plate, wherein said first fusible interconnect connects said first terminal of said first cell to said first contact block;
- selecting a fifth impedance for a first secondary fusible interconnect, wherein said fifth impedance is lower than said first, second, third and fourth impedances;
- electrically connecting said first contact block to said first collector plate with said first secondary fusible interconnect;
- interposing a second contact block between said second terminal of said first cell and said second collector plate, wherein said second fusible interconnect connects said first terminal of said first cell to said second contact block;
- selecting a sixth impedance for a second secondary fusible interconnect, wherein said sixth impedance is lower than said first, second, third and fourth impedances; and
- electrically connecting said second contact block to said second collector plate with said second secondary fusible interconnect.
12. The method of claim 22, wherein said step of selecting said third impedance for said first fusible interconnect further comprises the step of selecting said third impedance to be lower than said fourth impedance, and wherein said method further comprises the steps of:
- interposing a first contact block between said first terminal of said first cell and said first collector plate, wherein said first fusible interconnect connects said first terminal of said first cell to said first contact block;
- selecting a fifth impedance for a first secondary fusible interconnect, wherein said fifth impedance is lower than said first, second, third and fourth impedances; and
- electrically connecting said first contact block to said first collector plate with said first secondary fusible interconnect.
13. The method of claim 1, further comprising the steps of:
- configuring said first collector plate with a first rapid ablation pathway, wherein said first fusible interconnect is attached to said first rapid ablation pathway; and
- configuring said second collector plate with a second rapid ablation pathway, wherein said second fusible interconnect is attached to said second rapid ablation pathway.
14. The method of claim 1, further comprising the step of configuring said first fusible interconnect to fuse after said second fusible interconnect, and wherein said method further comprises the step of configuring said first collector plate with a rapid ablation pathway, wherein said first fusible interconnect is attached to said rapid ablation pathway.
15. The method of claim 1, wherein said step of configuring said first fusible interconnect further comprises the step of selecting an interconnect length corresponding to said first fusible interconnect which is shorter than an interconnect length selected for said first and second pluralities of fusible interconnects, and wherein said step of configuring said second fusible interconnect further comprises the step of selecting an interconnect length corresponding to said second fusible interconnect which is shorter than an interconnect length selected for said first and second pluralities of fusible interconnects.
16. The method of claim 1, wherein said step of configuring said second fusible interconnect further comprises the step of selecting an interconnect length corresponding to said second fusible interconnect which is shorter than an interconnect length selected for said first and second pluralities of fusible interconnects, and wherein said step of configuring said first fusible interconnect further comprises the step of selecting an interconnect length corresponding to said first fusible interconnect which is shorter than said interconnect length selected for said second fusible interconnect.
17. The method of claim 1, wherein said step of configuring said first fusible interconnect further comprises the step of selecting an interconnect thickness corresponding to said first fusible interconnect which is thicker than an interconnect thickness selected for said first and second pluralities of fusible interconnects, and wherein said step of configuring said second fusible interconnect further comprises the step of selecting an interconnect thickness corresponding to said second fusible interconnect which is thicker than an interconnect thickness selected for said first and second pluralities of fusible interconnects.
18. The method of claim 1, wherein said step of configuring said second fusible interconnect further comprises the step of selecting an interconnect thickness corresponding to said second fusible interconnect which is thicker than an interconnect thickness selected for said first and second pluralities of fusible interconnects, and wherein said step of configuring said first fusible interconnect further comprises the step of selecting an interconnect thickness corresponding to said first fusible interconnect which is thicker than said interconnect thickness selected for said second fusible interconnect.
19. The method of claim 1, wherein said step of electrically coupling said first terminal of each of said plurality of cells, except for said first cell, to said first collector plate further comprises the step of electrically coupling said first terminal of each of said plurality of cells, except for said first cell, to said first collector plate with a single interconnect of said first plurality of fusible interconnects, wherein said step of electrically coupling said second terminal of each of said plurality of cells, except for said first cell, to said second collector plate further comprises the step of electrically coupling said second terminal of each of said plurality of cells, except for said first cell, to said second collector plate with a single interconnect of said second plurality of fusible interconnects, wherein said step of electrically coupling said first terminal of said first cell to said first collector plate further comprises the step of electrically coupling said first terminal of said first cell to said first collector plate with a pair of said first fusible interconnects, and wherein said step of electrically coupling said second terminal of said first cell to said second collector plate further comprises the step of electrically coupling said second terminal of said first cell to said second collector plate with a pair of said second fusible interconnects.
20. The method of claim 1, wherein said step of electrically coupling said first terminal of each of said plurality of cells, except for said first cell, to said first collector plate further comprises the step of electrically coupling said first terminal of each of said plurality of cells, except for said first cell, to said first collector plate with a single interconnect of said first plurality of fusible interconnects, wherein said step of electrically coupling said second terminal of each of said plurality of cells, except for said first cell, to said second collector plate further comprises the step of electrically coupling said second terminal of each of said plurality of cells, except for said first cell, to said second collector plate with a single interconnect of said second plurality of fusible interconnects, wherein said step of electrically coupling said second terminal of said first cell to said second collector plate further comprises the step of electrically coupling said second terminal of said first cell to said second collector plate with a pair of said second fusible interconnects, and wherein said step of electrically coupling said first terminal of said first cell to said first collector plate further comprises the step of electrically coupling said first terminal of said first cell to said first collector plate with three of said first fusible interconnects.
21. The method of claim 22, further comprising the step of selecting said first and second impedances to be substantially the same.
22. The method of claim 1, further comprising the steps of:
- selecting a first impedance for said first plurality of fusible interconnects;
- selecting a second impedance for said second plurality of fusible interconnects;
- selecting a third impedance for said first fusible interconnect, wherein said third impedance is selected to be lower than said first impedance and said second impedance; and
- selecting a fourth impedance for said second fusible interconnect, wherein said fourth impedance is selected to be lower than said first impedance and said second impedance.
Type: Application
Filed: Aug 4, 2010
Publication Date: Feb 9, 2012
Patent Grant number: 8133287
Applicant: TESLA MOTORS, INC. (Palo Alto, CA)
Inventors: Weston Arthur Hermann (Palo Alto, CA), Scott Ira Kohn (Redwood City, CA), Paul Bryan Kreiner (Los Altos Hills, CA), Christopher David Gadda (Sunnyvale, CA)
Application Number: 12/850,520
International Classification: H01M 4/82 (20060101);