Abstract: A storage device includes: an embedding vector manager for determining an estimated access frequency of each of a plurality of embedding vectors, based on a learning data set, and dividing the plurality of embedding vectors into a plurality of embedding vector groups, based on an order of the estimated access frequencies; and a plurality of memory cell arrays for each storing embedding vectors included in any one embedding vector group among the plurality of embedding vector groups.

Abstract: Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Abstract: Provided is data receiving circuit, data receiving system and memory device. The data receiving circuit includes: first amplification circuit, configured to receive data signal, first reference signal and second reference signal, perform first comparison on the data signal and the first reference signal in response to sampling clock signal and output first signal pair, and perform second comparison on the data signal and the second reference signal and output second signal pair; second amplification circuit, configured to receive enable signal and feedback signal, selectively receive the first signal pair or the second signal pair as input signal pair based on the feedback signal during period in which the enable signal is at first level, receive the first signal pair during period in which the enable signal is at second level, amplify voltage difference of the first signal pair, and output first output signal and second output signal.

Abstract: A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Abstract: Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level.

Abstract: A level count disparity is determined based at least in part on: (1) an expected count of a plurality of cells in solid state storage and (2) an observed count of the plurality of cells in the solid state storage, where the observed count is associated with a number of cells in the solid state storage that are activated by performing a single read on the solid state storage using a previous read threshold. A next read threshold is determined, including by: determining a direction relative to the previous read threshold based at least in part on the level count disparity and independent of the second and earlier level count disparity; and determining a magnitude based at least in part on the level count disparity and the second and earlier level count disparity. Read data is obtained using the next read threshold and error correction decoding is performed.

Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

Abstract: A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, and output registered C/A signals and buffer control signals. The memory module further comprises a plurality of buffer circuits. In response to the buffer control signals, each buffer circuit is configured to communicate first data/strobe signals with at least one memory device and to communicate second data/strobe signals with the memory controller. The buffer circuit includes at least one delay circuit configured to delay at least one signal of the first data/strobe signals based on a first delay and a second delay.

Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.

Abstract: Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

Abstract: In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.

Abstract: A memory system includes a controller, a plurality of memory devices, and a signal wiring. The signal wiring is connected between the controller and the volatile memory devices and configuring a fly-by topology. At least one of the memory devices includes a memory cell array, a processing circuit configured to control the memory cell array, an input buffer through which a signal from the controller is transmitted to the processing circuit, and a resistor circuit connected between the input buffer and the signal wiring. The resistor circuit has a resistance value corresponding to a parasitic capacitance of the input buffer.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: A memory device includes at least one memory bank, a plurality of data pins coupled to a plurality of package pins, a data input/output (IO) circuit, at least one bank IO circuit and a plurality of switches. The package pins correspond to a first bit order, and the data pins correspond to a second bit order. The data IO circuit is configured to communicate a first data with the data pins, wherein the first data is arranged in the first bit order. The bank IO circuit is configured to communicate a second data with the memory bank, wherein the second data is arranged in the second bit order. The plurality of switches perform at least one swapping operation on the first data to generate the second data or to perform the at least one swapping operation on the second data to generate the first data.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks each including a plurality of cell units, each of the cell units including a plurality of memory cells; and a memory controller. The memory controller is configured to read second data from a second cell unit in a first block in response to first data being written in a first cell unit in the first block, and reserve refresh processing for the first block when the second data satisfies a condition.

Abstract: A semiconductor device includes a programming control signal generation circuit configured to generate a programming control signal and a programming termination signal based on programming data when a programming operation is performed, and a programming control circuit configured to program a command, an address, and an operation signal, based on the programming control signal to generate a programming command, a programming address, and a programming operation signal.

Abstract: A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

Abstract: A semiconductor device may include: a mode input control signal generation circuit configured to generate a control pulse when a mode control operation is performed, generate a mode input control signal by delaying the control pulse by a mode delay period, and control the mode delay period on the basis of a restart signal; a read strobe signal generation circuit configured to generate a read strobe signal on the basis of the control pulse; a read delay circuit configured to generate the read input control signal by delaying the read strobe signal by a read delay period; and a read pipe circuit configured to receive mode data on the basis of the mode input control signal, and receive cell data on the basis of the read input control signal.

Abstract: Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

Abstract: A memory controller comprising a DMA master device configured to provide a first data group to a non-volatile memory (NVM) device, a program buffer memory configured to temporarily store the first data group before the DMA master device provides the first data group to the NVM device, an exclusive OR computing circuit configured to perform an exclusive OR computation and an accumulation on a plurality of data included in the first data group provided from the program buffer memory to generate a first recovery data, after the DMA master device provides the first data group to the NVM device, and a buffer slave device including a first program recovery buffer memory configured to store the first recovery data and provide the first recovery data from the first program recovery buffer memory to the program buffer memory, in response to a program failure signal, may be provided.

Abstract: A storage device can control the input/output of data at a high frequency. The storage device includes a memory device and a memory controller for controlling the memory device, and providing the memory device with a command. The memory device includes a memory unit, and an interface chip for performing a training operation in response to the command. The interface chip generates a shift signal according to a first data strobe signal provided from the memory controller, and stores, based on the shift signal, training data provided from the memory controller.

Abstract: A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.

Abstract: A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers.

Abstract: There are provided a memory system and an operating method of the memory system. The memory system includes: a main controller for transmitting main data having N bits through a main channel, where N is a positive integer; memory devices for storing sub-data constituting the main data, and transmitting the sub-data through sub-channels; and a sub-controller for communicating with the main controller through the main channel, and communicating with the memory devices through the sub-channels. The sub-controller generates the sub-data each having n bits where n is a positive integer less than N, by dividing the main data, generates sub-data strobe clocks by decreasing a frequency of a main data strobe clock synchronized with the main data, and transmits/receives the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.

Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.

Abstract: A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.

Abstract: In a case where read information is a reading start location of second information, a controller causes a storage device to store location information regarding the read information as second location information, and in a case where the read information is not the reading start location of the second information, the controller causes a reading unit to read information based on location information different from the location information.

Abstract: A predefined data pattern is written using a plurality of values of a memory access parameter. A corresponding value of a data state metric associated with each value of a plurality of values of the memory access operation parameter is measured. An optimal value of the memory access operation parameter is selected from the plurality of values of the memory access operation parameter.

Abstract: A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.

Abstract: A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Abstract: A variety of applications can include devices or methods that provide read processing of data in memory cells of a memory device without predetermined read levels for the memory cells identified. A read process is provided to vary a selected access line gate voltage over time, creating a time-variate sequence where memory cell turn-on correlates with programmed threshold voltage. Total string current of data lines of a group of strings of memory cells of the memory device can be monitored during a read operation of selected memory cells of the strings to which a ramp voltage with positive slope is applied to an access line coupled to the selected memory cells. Selected values of the change of the total current with respect to time, from the monitoring of the total current, are determined. Read points to capture data are based on the determined selected values. Additional devices, systems, and methods are discussed.

Abstract: A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.

Abstract: Provided are a digital phase interpolator, a clock signal generator, and a volatile memory device including the clock signal generator. The clock signal generator includes an internal signal generator configured to generate a first internal signal and a second internal signal, which mutually have a phase difference, based on an external clock signal, a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal and generate a first interpolation signal, a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal and generate a second interpolation signal, and a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal and output the selected interpolation signal as an internal clock signal.

Abstract: An apparatus is provided for management of client devices for maintenance of a structural product. The apparatus is caused to receive device manifest reports that include information about the client devices and digital content hosted by respective library apps on the client devices. The apparatus is caused to generate a graphical user interface (GUI) to visually summarize the information, with the GUI embodied as a dashboard with a layout of software widgets. And the apparatus is caused to send the dashboard to an administrative device for display. This causes execution of the layout of software widgets on the dashboard at the administrative device to access the information from the content management platform, produce respective infographics to visually summarize the client devices and the digital content hosted by the respective library apps, based on the information, and display the respective infographics in the dashboard at the administrative device.

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

Abstract: An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.