Having Particular Data Buffer Or Latch Patents (Class 365/189.05)
  • Patent number: 10734978
    Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Soman Purushothaman, Sankar Prasad Debnath, Per Torstein Roine, Steven C. Bartling, Keshav Bhaktavatson Chintamani
  • Patent number: 10733089
    Abstract: Apparatuses and methods are provided for write address tracking. An example apparatus can include an array of memory cells and a cache coupled to the array. The example apparatus can include tracking circuitry coupled to the cache. The tracking circuitry can be configured to track write addresses of data written to the cache.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gary L. Howe, Timothy P. Finkbeiner
  • Patent number: 10734060
    Abstract: Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Akira Yamashita
  • Patent number: 10715359
    Abstract: The present invention provides a decision feedback equalizer including a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit generates a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and the first latch circuit generates a first digital signal according to the first set signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit generates the second set signal and the second reset signal according to the input signal, the first set signal and the first reset signal, and the second latch circuit generates a second digital signal according to the second set signal and the second reset signal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: July 14, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsi-En Liu, Shawn Min, Yi-Chun Hsieh
  • Patent number: 10699053
    Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: June 30, 2020
    Assignee: XILINX, INC.
    Inventors: Zhiyong Wang, Ruibing Lu, Lin Chai, Sabyasachi Das
  • Patent number: 10699774
    Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Scott E. Smith
  • Patent number: 10699755
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Adam S. El-Mansouri, John D. Porter
  • Patent number: 10693473
    Abstract: Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Armin Tajalli, Ali Hormati
  • Patent number: 10684979
    Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
  • Patent number: 10665271
    Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: May 26, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Takeda, Takashi Iwase
  • Patent number: 10664748
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10665277
    Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 26, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Shih-Wen Chou, Shih-Chang Hsu
  • Patent number: 10664395
    Abstract: A memory device includes a plurality of bit lines; a page buffer circuit including a plurality of page buffers which are electrically coupled to the plurality of bit lines; and a cache circuit including a plurality of caches which are electrically coupled to the plurality of page buffers, wherein a number of stages of the page buffer circuit is less than a number of stages of the cache circuit.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Soo-Nam Jung
  • Patent number: 10665275
    Abstract: A method for operating a memory device includes: receiving a write command; checking out whether a data strobe signal toggles or not after a given time passes from a moment when the write command is received; when the data strobe signal is checked out to be maintained at a uniform level, detecting voltage levels of a plurality of data pads; and performing an operation that is selected based on the voltage levels of the plurality of the data pads among a plurality of predetermined operations.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Sung-Eun Lee, Jung-Hyun Kwon
  • Patent number: 10658019
    Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 10658040
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Patent number: 10650899
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed. Calibration and testing sequences are also supported in which a non-destructive mode preserves data stored in a non-volatile memory array and status bits used to indicate open pages are cleared so later inadvertent delayed write-back operations as a result of the calibration or testing do not corrupt the non-volatile data.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: May 12, 2020
    Assignee: Everspin Technologies, Inc.
    Inventor: Syed M. Alam
  • Patent number: 10642537
    Abstract: A semiconductor memory includes a first plane that includes a first memory cell array, a second plane that includes a second memory cell array, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority. When a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 10636499
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 10629289
    Abstract: A solid state storage device is in communication with a host. The solid state storage device includes a control circuit and a non-volatile memory. The control circuit is in communication with the host. The control circuit includes an error correction circuit and a prediction model storage circuit. A prediction model is stored in the prediction model storage circuit. The non-volatile memory includes a memory cell array. The memory cell array includes plural blocks. Each of the blocks includes a corresponding state parameter. The control circuit determines a selected block from the memory cell array. The control circuit judges whether to perform a specified operation on the selected block according to the state parameter of the selected block and the prediction model.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Jia Zeng, Jen-Chien Fu, Tsu-Han Lu, Kuan-Chun Chen
  • Patent number: 10629255
    Abstract: A processing system and method for a data strobe signal (DQS). A counter circuit counts falling edges of the DQS within a valid region of the DQS and thereby generates a plurality of counting signals. An OR logic circuit receives the counting signals and a DQS window start signal and thereby generates a DQS window signal. A filter circuit is provided to gate the DQS according to the DQS window signal. The DQS window start signal is kept asserted until at least one of the counting signals changes due to the counting.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 21, 2020
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Chen Chen, Hui Wu, Fan Jiang, Qiang Si
  • Patent number: 10621122
    Abstract: Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Lior Moheban, Ronen Goldberg, Yakov Tokar, Gregory Kovishaner, Alex Pinskiy
  • Patent number: 10614871
    Abstract: A semiconductor device includes a delay circuit and a column signal generation circuit. The delay circuit delays a write signal by a sum of a write latency time and a burst operation time to generate a write pulse, delays a read signal to generate a read pulse, and generates a pre-charge signal which is enabled after a predetermined period elapses from a time when the write signal is generated. The column signal generation circuit generates a column signal from a chip selection signal and a command/address signal when the write pulse or the read pulse is inputted to the column signal generation circuit. The column signal is a signal for selecting at least one memory cell included in one of a plurality of banks.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Ho Kang, Jin Wook Kim, Yang Uk Son
  • Patent number: 10613607
    Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anurag Arora, Vikram Sharma, Sumantra Seth
  • Patent number: 10607680
    Abstract: In an embodiment a semiconductor device may include a weakness detector configured to manage error occurrence information by dividing the memory device into a plurality of areas, to control a first refresh period for a first refresh request at each of the plurality of areas based on the error occurrence information and to generate a second refresh request for a second refresh address included in each of the plurality of areas based on the error occurrence information, and a refresh controller configured to generate a first refresh command according to the first refresh period and output the first refresh command to the memory device and to output a second refresh command and the second refresh address to the memory device according to the second refresh request and the second refresh address.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Youngjae Jin, Joonwoo Kim, Youngook Song
  • Patent number: 10607667
    Abstract: A data output circuit includes: a voltage generation circuit configured to generate an operating voltage having a potential level higher than levels of a first power supply voltage and a second power supply voltage; a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to calibration code signals and the operating voltage; a data pre-driver circuit configured to generate and output internal data according to a data signal and the first power supply voltage; and a main driver circuit configured to generate output data according to the internal data and the second power supply voltage, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventors: Hee Jun Kim, Minsoon Hwang
  • Patent number: 10600702
    Abstract: A test element group includes a test element including a plurality of test transistors connected in series between a first node and a second node, the second node being connected to a ground node; a first transistor connected between the first node and a power supply node; and a second transistor configured to generate an output current, proportional to a voltage at the first node, and connected to the first node and the power supply node.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Zhan Zhan, Ju Hyun Kim, Sung Gun Kang, Hwa Sung Rhee
  • Patent number: 10599566
    Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ramasamy Adaikkalavan, Harish Shankar, Rajesh Kumar
  • Patent number: 10600470
    Abstract: A memory system includes a memory controller and a memory device. The memory controller determines and provides a hammer address. The hammer address is an address that has an activation number or frequency greater than a predetermined threshold. The memory device generates a hammer refresh signal representing a timing for a hammer refresh operation to refresh a first row of the memory device that is physically adjacent to a second row of the memory device corresponding to the hammer address. The memory device performs the hammer refresh operation using the hammer address provided from the memory controller and the hammer refresh signal generated by the memory device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jong-Min Bang
  • Patent number: 10593386
    Abstract: A semiconductor device includes a synthesis signal generation circuit, a column control circuit, and a control signal generation circuit. The synthesis signal generation circuit generates a register synthesis signal in response to first and second read pulses sequentially generated during a read operation. The column control circuit generates any one of a first bank selection signal and a second bank selection signal for respectively selecting a first bank group and a second bank group included in a core circuit in response to the first and second read pulses. The control signal generation circuit generates a control signal for controlling an output operation of a mode register in response to the register synthesis signal.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10585602
    Abstract: An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 10, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan
  • Patent number: 10580473
    Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 3, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ning Ge, John Paul Strachan, Jianhua Yang, Miao Hu
  • Patent number: 10574218
    Abstract: A digital glitch filter for filtering glitches in an input signal includes a first flip-flop for generating a filtered output signal, and a self-oscillating circuit for generating a self-oscillating clock signal. A first logic gate enables the self-oscillating circuit when the filtered output signal is not equal to the input signal. A ripple counter generates a divided clock signal by dividing the self-oscillating clock signal. A counter and comparator counts the divided clock signal to obtain a count number and compares the count number with a predetermined count target. A second flip-flop, which is connected to the counter and comparator, generates a valid signal, which is activate when the count number reaches the count target. The valid signal is input to the first flip-flop such that the filtered output signal toggles when the valid signal is active.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: February 25, 2020
    Assignee: NXP USA, Inc.
    Inventors: Zhixiong Lin, Mingqin Xie, Yong Zhu
  • Patent number: 10573396
    Abstract: A semiconductor device may include a mask control circuit suitable for generating a section-masking signal activated during a strobe section, based on at least one strobe signal; a strobe signal input circuit suitable for generating an input control signal toggled during the strobe section, based on the section-masking signal and the strobe signal; and a data signal input circuit suitable for receiving a data signal based on the input control signal.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Ki-Bong Koo
  • Patent number: 10566065
    Abstract: A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: February 18, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yi-Lin Hsieh, Jing-Long Xiao, Cheng-Yu Chen, Wang-Sheng Lin
  • Patent number: 10560093
    Abstract: A semiconductor device includes a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on a first selection termination control signal and a termination control signal and a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on a second selection termination control signal and the termination control signal.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 10559334
    Abstract: A memory device includes a memory cell array storing input data, a clock generator circuit generating first clocks and second clocks using a reference clock, a phase information generator circuit comparing a phase of the reference clock and a phase of at least one of the first clocks and the second clocks and generating phase information as a comparison result, an intermediate data generator circuit serializing a part of input data provided from the memory cell array based on the first clocks to generate first data, serializing a remaining part of the input data to generate second data, and selectively swapping the first data and the second data using the phase information to generate intermediate data, and an output data generator circuit serializing the intermediate data using the second clocks, to output output data through one output data line.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Park, Yongjun Kim, Chang-Yong Lee
  • Patent number: 10541030
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 10534573
    Abstract: Systems, methods and software for sample rate conversion with unknown input and output clocks are disclosed. In one embodiment, a method for an asynchronous transfer of audio data includes: receiving the audio data by an antenna of a receiver (RX); storing the audio data in an input buffer of the RX; and receiving data words from the input buffer by a sample rate converter (SRC). The consecutive data words are received from the input buffer at an adjustable period T. The method further includes tracking a filling level of the input buffer; and based on the filling level of the input buffer, adjusting the adjustable period T. When the filling level of the input buffer is below the target level of the input buffer, the adjustable period T is increased. When the filling level of the input buffer is above the target level of the input buffer, the adjustable period T is decreased.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: January 14, 2020
    Assignee: Sonova AG
    Inventors: Amre El-Hoiydi, Timothee Jost, Till Schmalmack, Jordi Hidalgo, Alessandro Gallo
  • Patent number: 10522215
    Abstract: A reading circuit is provided in the invention. The reading circuit includes a sensitive amplifier circuit and a latch circuit. A sensitive amplifier circuit is coupled to a first bit line and a second bit line to connect with a storage device, and includes a first inverter and a second inverter. The first bit line is coupled to a source of a first transistor of the first inverter and the second bit line is coupled to a source of a second transistor of the second inverter. The latch circuit is coupled to the sensitive amplifier circuit and outputs an output signal generated by the sensitive amplifier circuit.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 31, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Wenxiao Li, Jiesheng Chen
  • Patent number: 10509741
    Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Patent number: 10504582
    Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Noriaki Mochida
  • Patent number: 10497412
    Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: December 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Kyoo Lee, Jeong-Don Ihm, Byung-Hoon Jeong, Dae-Woon Kang
  • Patent number: 10496584
    Abstract: A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-young Lim, Hui-chong Shin, In-su Choi, Young-ho Lee
  • Patent number: 10497423
    Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. the computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: December 3, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Jen Chang, Wen-Ming Lee
  • Patent number: 10497413
    Abstract: System and method of read deskew training for ×4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each other, the read leveling settings can be common within the byte even the two DQS signals are transmitted to or received from two different memory storage devices.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 3, 2019
    Assignee: CAVIUM, LLC
    Inventor: David Da Wei Lin
  • Patent number: 10481799
    Abstract: A data storage device and a method of operating the same are provided. The data storage device includes a first non-volatile memory device, a second non-volatile memory device, and a management module. The management module receives, from a host, an external multi-access command including first and second physical addresses which are different from each other, generates and sends a first access command including the first physical address to the first non-volatile memory device, and generates and sends a second access command including the second physical address to the second non-volatile memory device. The data management module performs operations on the first and second non-volatile memory devices based on the first and second access commands and the first and second physical addresses, respectively. The data storage device may be a solid state drive (SSD) including NAND flash memory, and the multi-access command may be a multi-write, multi-read, or multi-erase command.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Jin Yun, Sil Wan Chang
  • Patent number: 10482930
    Abstract: In an embodiment a memory chip may be provided. The memory chip may include a chip select buffer configured to receive a chip select signal, a command buffer configured to receive a command signal, wherein the command signal is input after a time has elapsed since the chip select signal is activated and the command buffer is turned on when the command signal is input.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Young-Suk Moon
  • Patent number: 10474581
    Abstract: The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeremiah J. Willcock, Richard C. Murphy
  • Patent number: 10475492
    Abstract: A memory device comprises an array of memory cells, and a plurality of sense amplifiers coupled with the memory cells. A controller is configured to execute a read operation in response to a command and address, including a read cycle in which the memory cells at the address are electrically coupled to the sense amplifiers, and in which the memory cells at the address are electrically decoupled from the sense amplifiers in response to a timing signal.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 12, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shang-Chi Yang, Chun-Yu Liao, Yi-Wei Chang