Having Particular Data Buffer Or Latch Patents (Class 365/189.05)
  • Patent number: 11929140
    Abstract: A memory controller comprising a DMA master device configured to provide a first data group to a non-volatile memory (NVM) device, a program buffer memory configured to temporarily store the first data group before the DMA master device provides the first data group to the NVM device, an exclusive OR computing circuit configured to perform an exclusive OR computation and an accumulation on a plurality of data included in the first data group provided from the program buffer memory to generate a first recovery data, after the DMA master device provides the first data group to the NVM device, and a buffer slave device including a first program recovery buffer memory configured to store the first recovery data and provide the first recovery data from the first program recovery buffer memory to the program buffer memory, in response to a program failure signal, may be provided.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Min Lee, Hyung Jin Kim, Seong Wan Hong
  • Patent number: 11922064
    Abstract: A storage device can control the input/output of data at a high frequency. The storage device includes a memory device and a memory controller for controlling the memory device, and providing the memory device with a command. The memory device includes a memory unit, and an interface chip for performing a training operation in response to the command. The interface chip generates a shift signal according to a first data strobe signal provided from the memory controller, and stores, based on the shift signal, training data provided from the memory controller.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: March 5, 2024
    Assignee: SK hynix Inc.
    Inventors: Soo Jin Kim, Seung Jin Park
  • Patent number: 11915772
    Abstract: A data storage device has a controller that instructs a memory to read memory cells using a number of different read voltage levels and then selects the read voltage level that provides the best read. Instead of sending individual commands for each of the different read voltage levels, the controller sends a single command that specifies an initial read voltage level and a voltage shift, and the memory automatically increments the read voltage level by the voltage shift for each read.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vishal Sharma, Darshan Pagariya, Sourabh Sankule
  • Patent number: 11908541
    Abstract: A processing-in-memory (PIM) system includes a first and second PIM devices and a host. Each of the first and second PIM devices includes a plurality of multiplying-and-accumulating (MAC) operators and a plurality of memory banks supplying weight data to the plurality of MAC operators. The host controls the first and second PIM devices and includes a data buffer. The first and second PIM devices include a first global buffer and a second global buffer, which supply the vector data to the plurality of MAC operators, respectively. The host reads the vector data out of the first and second PIM devices to store the vector data into the data buffer and writes the vector data stored in the data buffer into the first and second global buffers.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11901027
    Abstract: There are provided a memory system and an operating method of the memory system. The memory system includes: a main controller for transmitting main data having N bits through a main channel, where N is a positive integer; memory devices for storing sub-data constituting the main data, and transmitting the sub-data through sub-channels; and a sub-controller for communicating with the main controller through the main channel, and communicating with the memory devices through the sub-channels. The sub-controller generates the sub-data each having n bits where n is a positive integer less than N, by dividing the main data, generates sub-data strobe clocks by decreasing a frequency of a main data strobe clock synchronized with the main data, and transmits/receives the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventor: Jong Joo Lee
  • Patent number: 11894075
    Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 6, 2024
    Assignee: Yangtze Memory Technologies Co. Ltd.
    Inventor: Jason Guo
  • Patent number: 11862228
    Abstract: A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES INC.
    Inventor: Rumin Ji
  • Patent number: 11836033
    Abstract: In a case where read information is a reading start location of second information, a controller causes a storage device to store location information regarding the read information as second location information, and in a case where the read information is not the reading start location of the second information, the controller causes a reading unit to read information based on location information different from the location information.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: December 5, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takahiro Yamashita
  • Patent number: 11837303
    Abstract: A predefined data pattern is written using a plurality of values of a memory access parameter. A corresponding value of a data state metric associated with each value of a plurality of values of the memory access operation parameter is measured. An optimal value of the memory access operation parameter is selected from the plurality of values of the memory access operation parameter.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seungjune Jeon, Tingjun Xie
  • Patent number: 11831471
    Abstract: A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: November 28, 2023
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, MIRISE Technologies Corporation
    Inventors: Shigeki Otsuka, Hyoungjun Na, Takasuke Ito, Yoshikazu Furuta, Tomohiro Nezuka
  • Patent number: 11822820
    Abstract: A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: November 21, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ran Zamir, Eran Sharon, Idan Alrod
  • Patent number: 11810638
    Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonkyoo Lee, Chiweon Yoon, Byunghoon Jeong, Youngmin Jo
  • Patent number: 11804280
    Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Kyoman Kang, Sangwan Nam
  • Patent number: 11799481
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Yo Han Jeong, Eun Ji Choi
  • Patent number: 11783871
    Abstract: A variety of applications can include devices or methods that provide read processing of data in memory cells of a memory device without predetermined read levels for the memory cells identified. A read process is provided to vary a selected access line gate voltage over time, creating a time-variate sequence where memory cell turn-on correlates with programmed threshold voltage. Total string current of data lines of a group of strings of memory cells of the memory device can be monitored during a read operation of selected memory cells of the strings to which a ramp voltage with positive slope is applied to an access line coupled to the selected memory cells. Selected values of the change of the total current with respect to time, from the monitoring of the total current, are determined. Read points to capture data are based on the determined selected values. Additional devices, systems, and methods are discussed.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Douglas Eugene Majerus
  • Patent number: 11763897
    Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Ezra E. Hartz, Vipul Patel
  • Patent number: 11763859
    Abstract: A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: September 19, 2023
    Assignee: SK hynix Inc.
    Inventor: In Sung Koh
  • Patent number: 11755508
    Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: September 12, 2023
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Craig E. Hampel, Scott C. Best, John Yan
  • Patent number: 11750181
    Abstract: Provided are a digital phase interpolator, a clock signal generator, and a volatile memory device including the clock signal generator. The clock signal generator includes an internal signal generator configured to generate a first internal signal and a second internal signal, which mutually have a phase difference, based on an external clock signal, a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal and generate a first interpolation signal, a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal and generate a second interpolation signal, and a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal and output the selected interpolation signal as an internal clock signal.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: September 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Junsub Yoon
  • Patent number: 11749360
    Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 11727078
    Abstract: An apparatus is provided for management of client devices for maintenance of a structural product. The apparatus is caused to receive device manifest reports that include information about the client devices and digital content hosted by respective library apps on the client devices. The apparatus is caused to generate a graphical user interface (GUI) to visually summarize the information, with the GUI embodied as a dashboard with a layout of software widgets. And the apparatus is caused to send the dashboard to an administrative device for display. This causes execution of the layout of software widgets on the dashboard at the administrative device to access the information from the content management platform, produce respective infographics to visually summarize the client devices and the digital content hosted by the respective library apps, based on the information, and display the respective infographics in the dashboard at the administrative device.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 15, 2023
    Assignee: THE BOEING COMPANY
    Inventors: Jared B. Kunz, Bradley D. Gorter, Rex Byron Douglas, Michael R. Munsey, Joshua J. Lavalleur, Michael E. Norman
  • Patent number: 11727967
    Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
  • Patent number: 11727991
    Abstract: An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youhwan Kim, Kyungduk Lee
  • Patent number: 11699469
    Abstract: Provided are an operating method of a host device, an operating method of a memory device, and a memory system. The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: July 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young San Kang, Jeong Hur, Walter Jun, Kwang Won Park, Kyoung Back Lee
  • Patent number: 11694752
    Abstract: In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 4, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Shu Xie
  • Patent number: 11670350
    Abstract: A data input buffer includes a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected with a first input terminal and a second input terminal thereof short-circuited, as write data, and wherein a buffer unit corresponding to a current value of the first impedance calibration code among the plurality of buffer units is configured to correct the offset according to the second impedance calibration code.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventors: Soon Sung An, Kwan Su Shon
  • Patent number: 11667453
    Abstract: A computer system generates information describing authenticity and a grade of a collectible scanned by a scanning device. A feature vector is extracted from the information. The feature vector includes a first set of features and a second set of features. The first set of features is matched to authenticity profiles of collectible items. Each authenticity profile characterizes at least one collectible item across multiple features. A confidence score is generated with respect to the authenticity of the collectible based on the authenticity profiles. The second set of features is matched to grade profiles of the collectible items. A grade score describing the grade of the collectible is generated based on the grade profiles. The grade of the collectible is determined based on the grade score. A graphical representation of the grade and the confidence score is transmitted to a display device.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: June 6, 2023
    Assignee: SGCC Inc.
    Inventor: John Hovig Dolmayan
  • Patent number: 11662799
    Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 30, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki-Seok Oh
  • Patent number: 11657860
    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joohwan Kim, Jindo Byun, Younghoon Son, Youngdon Choi, Junghwan Choi
  • Patent number: 11651817
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventor: Noboru Shibata
  • Patent number: 11625063
    Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Jin Cho, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
  • Patent number: 11626147
    Abstract: Embodiments relate to a transmission circuit, a transmission method, a storage apparatus, and a storage medium. The transmission circuit includes a comparison module and a data conversion module. The comparison module is configured to receive first data on a first data line and second data on a second data line, and compare the first data with the second data to output a comparison result indicating whether number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width. The data conversion module is electrically connected to the first data line, the comparison module and the second data line, and is configured to invert the first data and transmit the inverted first data to the second data line when the comparison result is indicative of exceeding the preset threshold.
    Type: Grant
    Filed: September 5, 2021
    Date of Patent: April 11, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Liang Zhang
  • Patent number: 11619963
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Amir Javidi, Daniel Cummings, Glenn Starnes
  • Patent number: 11616053
    Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: March 28, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. Devilliers, Kandabara Tapily
  • Patent number: 11600347
    Abstract: According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshiaki Dozaka
  • Patent number: 11600329
    Abstract: A system performs analog memory sanitization by forcing voltage levels in memory cells to substantially the same voltage level so that they are indistinguishable regardless of the data that has been previously stored in the cells. In some embodiments, a special programming operation for sanitizing a plurality of memory cells forces the charge in the cells to approximately the same voltage level by increasing the voltage level of all cells regardless of the data currently stored in the cells. As an example, each cell may be programmed to a logical high bit value (e.g., a “0”) by increasing the charge in each cell to a voltage level that is greater than the voltage level for writing the same logical bit value in a normal programming operation. Thus, after the programming operation is performed, the voltage levels of cells storing one logical bit value (e.g., a “0”) prior to the programming operation may be indistinguishable from voltage levels of cells storing a different logical bit value (e.g.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 7, 2023
    Assignee: Board of Trustees of the University of Alabama, for and on behalf of the University of Alabama in Huntsville
    Inventor: Biswajit Ray
  • Patent number: 11568229
    Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: January 31, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
  • Patent number: 11551731
    Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 10, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Vikas Rana, Arpit Vijayvergia
  • Patent number: 11537314
    Abstract: Systems and methods are provided for bringing a volume of a consistency group (CG) into an in-synchronization (InSync) state while other volumes of the CG remain in the InSync state. According to an example, in order to support recovery from disruptive events in a manner that ensures a zero recovery point objective (RPO) guarantee and insulates an application making use of the CG from adverse impacts, responsive to a triggering event, a Fast Resync process may first be attempted to promptly bring an affected volume back into an in-synchronization (InSync) state from an out of synchronization (OOS) state while allowing other members of the CG to remain in the InSync state. Should the Fast resync process be unsuccessful in bringing the volume back into the InSync state within a predetermined or configurable time threshold, then a second type of resynchronization process may be employed at the CG level.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 27, 2022
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Akhil Kaushik, Anoop Vijayan, Arun Kumar Selvam
  • Patent number: 11532376
    Abstract: A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Hosung Cho
  • Patent number: 11527271
    Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 13, 2022
    Assignee: IHP GMBH—Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
    Inventors: Oliver Schrape, Anselm Breitenreiter, Frank Vater, Milos Krstic
  • Patent number: 11513955
    Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 29, 2022
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 11508419
    Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong Sung Cho, Jeung Hwan Park, Jong Min Kim, Jung Kwan Kim
  • Patent number: 11510333
    Abstract: A module, comprising: a printed circuit board (PCB); a power and management connector disposed on the PCB to connect to a computing device via a first cable; a data connector disposed on the PCB to connect to the computing device via a second cable; and a memory slot, to accept a memory device, disposed on the PCB and connected to the power and management connector and the data connector.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: November 22, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Norton, Vincent Nguyen
  • Patent number: 11501815
    Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Tae H. Kim, Scott James Derner
  • Patent number: 11501848
    Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: November 15, 2022
    Assignee: Rambus Inc.
    Inventors: Adrian E. Ong, Fan Ho
  • Patent number: 11495588
    Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind Bhagavat, Rahul Agarwal
  • Patent number: 11494082
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yuko Noda
  • Patent number: 11495272
    Abstract: An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11489606
    Abstract: Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Anthony Louviere, John L. Melanson, Gabriel Vogel