Having Particular Data Buffer Or Latch Patents (Class 365/189.05)
  • Patent number: 11423992
    Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Jin Choi
  • Patent number: 11416250
    Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Elancheren Durai
  • Patent number: 11410736
    Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Sung Hyun Hwang
  • Patent number: 11404126
    Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 2, 2022
    Assignee: SK hynix Inc.
    Inventors: Kang Woo Park, Soo Yeol Chai
  • Patent number: 11403035
    Abstract: Apparatuses and methods related to a memory module controller are disclosed. An example apparatus, such as a dual in-line memory module (DIMM), includes a first interface coupled to a host, and a second interface coupled to another memory module. The memory module includes a controller configured to simultaneously communicate with the host via the first interface, which may be a non-volatile DIMM (NVDIMM) interface in one example, and communicate with the other memory module via the second interface. In some examples, the first and second interfaces are configured according to different standards or protocols. The controller controls access to memory on the memory module. The controller may be configured to receive commands from a direct memory access (DMA) module. In some examples, the other memory module connected via the second interface includes a local controller and memory of a different type.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Robert M. Walker
  • Patent number: 11393550
    Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, John Eric Linstadt
  • Patent number: 11393540
    Abstract: A control circuit on a control die compensates for interference caused by adjacent memory cells on target memory cells on a memory die. The compensation may be based on the data states of the adjacent memory cells. Data latches may be used to store data states of the memory cells. However, reading the target memory cells can over-write the data states of the adjacent memory cells in the data latches. The control die may store data state information for the adjacent memory cells prior to sensing the target memory cells (e.g., prior to a decoding error of a codeword in the target cells). Saving the data state information on the control die reduces storage requirements of the memory die and alleviates the need to sense the adjacent memory cells again if decoding the codeword in the target memory cells fails.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Eran Sharon, Idan Alrod
  • Patent number: 11380406
    Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: July 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yousuke Hagiwara, Kensuke Yamamoto, Takeshi Hioka, Satoshi Inoue
  • Patent number: 11380372
    Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy A. Manning, Troy D. Larsen, Glen E. Hush
  • Patent number: 11372784
    Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 28, 2022
    Assignee: Rambus Inc.
    Inventors: Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
  • Patent number: 11362043
    Abstract: A memory package includes a package substrate including power wiring and ground wiring. The memory package also includes a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring. The memory package further includes a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring. The memory package additionally includes a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Byung Jun Bang, Sun Kyu Kong
  • Patent number: 11355215
    Abstract: A data storage apparatus may include a data storage device including at least one data die to store first data, and at least one parity die to store second data, third data, and a chip-kill parity, where the at least one data die and the at least one parity die are connected to a channel, and controller in communication with the data storage device and configured to receive a write request for the first data and the second data from a host that is in communication with the data storage device through the channel to generate the chip-kill parity from the first data and the second data. The controller is further configured to read the third data from the parity die and provide the third data to the host upon receipt of a read request for the third data from the host while the chip-kill parity is being updated based on the first data.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: June 7, 2022
    Assignee: SK HYNIX INC.
    Inventor: Chung Un Na
  • Patent number: 11355181
    Abstract: A high bandwidth memory and a system having the same are disclosed. The high bandwidth memory includes a buffer die and a plurality of memory dies, each of which includes at least one first processing element bank group and at least one second processing element bank group. The at least one first processing element bank group includes one or more first banks connected to one or more first bank input/output line groups, and a first processing element controller connected to the one or more first bank input/output line groups and a first global input/output line group, and is configured to perform a first processing operation on first data output from one of the one or more first bank input/output line groups and second data transmitted through the first global input/output line group based on a first instruction that is generated based on a first processing command.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seongil O, Namsung Kim, Sukhan Lee
  • Patent number: 11355163
    Abstract: The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 7, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Wei Han, Shuangchen Li, Lide Duan, Hongzhong Zheng, Dimin Niu, Yuhao Wang, Xiaoxin Fan
  • Patent number: 11353987
    Abstract: A voltage compensation method includes: within a touch time period, multiplexing common electrode blocks as touch electrodes, and scanning the common electrode blocks in at least one column sequentially to detect a capacitance of each scanned common electrode block; within a time period between detecting the capacitance of each scanned common electrode block and starting an Nth display time period after the touch time period, calculating power consumption for each scanned common electrode block in accordance with the capacitance thereof, acquiring a corresponding common electrode voltage compensation value based on the power consumption, and adding the common electrode voltage compensation value to a reference common electrode voltage to acquire a compensated common electrode voltage applied to each scanned common electrode block; and within the Nth display time period, adjusting a common electrode voltage applied to each scanned common electrode block into the compensated common electrode voltage.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 7, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Rui Liu, Gaowei Chen, Junjie Xu, Yanming Wang, Jiaqiang Wang, Chao Yu, Dong Liu
  • Patent number: 11343190
    Abstract: In an example, a network switch is configured to operate natively as a load balancer. The switch receives incoming traffic on a first interface communicatively coupled to a first network, and assigns the traffic to one of a plurality of traffic buckets. This may include looking up a destination IP of an incoming packet in a fast memory such as a ternary content-addressable memory (TCAM) to determine whether the packet is directed to a virtual IP (VIP) address that is to be load balanced. If so, part of the source destination IP address may be used as a search tag in the TCAM to assign the incoming packet to a traffic bucket or IP address of a service node.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 24, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Samar Sharma, Mouli Vytla, Rajendra Kumar Thirumurthi
  • Patent number: 11335395
    Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale
  • Patent number: 11335387
    Abstract: An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 17, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weiwei Shan, Tao Wang
  • Patent number: 11335405
    Abstract: An operation method of a nonvolatile memory device includes receiving a first DQ signal representing a first data bit from an external device through a first DQ line and receiving a second DQ signal representing a second data bit from the external device through a second DQ line, and programming a first memory cell corresponding to the first DQ line and a second memory cell corresponding to the second DQ line such that the first memory cell has any one of an erase state and a first program state based on the first DQ signal and the second memory cell has any one of the erase state and a second program state based on the second DQ signal. A lower limit value of a threshold voltage distribution corresponding to the second program state is higher than a lower limit value of a threshold voltage distribution corresponding to the first program state.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 17, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Joonsoo Kwon
  • Patent number: 11315609
    Abstract: A read path for a memory is provided that includes an integrated sense mixing and redundancy shift stage coupled between a sense amplifier and a data latch. The data latch is integrated with a level shifter.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 26, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Patent number: 11315640
    Abstract: A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C0) of a latch (L1) of a page buffer/sensing circuit, data of the cache memory (C0) of a next page is read from a memory cell array, and the read data of the cache memory (C0) is held in the latch (L1). After outputting data held in the cache memory (C1) of the latch (L1), data of the same next page of the cache memory (C1) is read from the memory cell array, and the read data of the cache memory (C1) is held in the latch (L1).
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 26, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Makoto Senoo, Katsutoshi Suito, Tsutomu Taniguchi, Sho Okabe
  • Patent number: 11302386
    Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xinyu Wu, Dong Pan
  • Patent number: 11295823
    Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
  • Patent number: 11295817
    Abstract: Provided herein may be a page buffer and a semiconductor memory device having the same. The page buffer may include a sensing node, of which a potential is controlled based on an amount of current flowing through a bit line during a data sensing operation and based on a potential of a page buffer common node during a data transmission operation, and a main latch component configured to latch data based on the potential of the sensing node, wherein the main latch component latches the data depending on a first trip voltage and the potential of the sensing node during the data transmission operation, and latches the data depending on a second trip voltage and the potential of the sensing node during the data sensing operation, the first trip voltage and the second trip voltage being different.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Kang Woo Park
  • Patent number: 11289141
    Abstract: An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 29, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Kuan Cheng, Ching-Wei Wu
  • Patent number: 11276470
    Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Dheeraj Srinivasan, Andrea D'Alessandro
  • Patent number: 11276441
    Abstract: A memory device includes a data pad disposed in a first pad area and configured to receive data, a data strobe pad disposed in the first pad area and configured to receive a data strobe signal, a clock pad disposed in a second pad area adjacent to the first pad area and configured to receive a clock signal, a data conversion circuit disposed in the first pad area and configured to convert the data inputted through the data pad into parallel data based on the data strobe signal, and a data driving circuit disposed in the first pad area and configured to transmit the parallel data through a global input and output line based on the clock signal.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Seong Ju Lee, Ju Hyuck Kim
  • Patent number: 11270743
    Abstract: An electronic device includes a control signal generation circuit and a control circuit. The control signal generation circuit is configured to generate a command power control signal, a status power control signal, an address power control signal, and a pre-charge power control signal which are enabled to control a supply of power voltages during a write operation and an auto-pre-charge operation. The control circuit is configured to receive the power voltages to generate a write signal, a write pre-charge signal, a bank address signal, an internal address signal, and an auto-pre-charge address signal based on an internal chip selection signal and an internal command/address signal while the command power control signal, the status power control signal, the address power control signal, and the pre-charge power control signal are enabled.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 11269555
    Abstract: An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on the prediction.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: March 8, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Harihara Sravan, Nihal Singla, Chinh Vo
  • Patent number: 11270754
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Dean Gans
  • Patent number: 11263141
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 20, 2020
    Date of Patent: March 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, David Puffer, Prasoonkumar Surti, Lakshminarayanan Striramassarma, Vasanth Ranganathan, Kiran C. Veernapu, Balaji Vembu, Pattabhiraman K
  • Patent number: 11256613
    Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: February 22, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 11250894
    Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngcheon Kwon, Jemin Ryu, Jaeyoun Youn, Haesuk Lee, Jihyun Choi
  • Patent number: 11243898
    Abstract: A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 8, 2022
    Assignee: Arm Limited
    Inventors: Andreas Hansson, Aniruddha Nagendran Udipi, Neha Agarwal
  • Patent number: 11237916
    Abstract: A no-copy clone of a logical storage unit is created. A define process is initiated for defining a target logical storage unit as the clone before activation of the target logical storage unit. By initiating the define process before activating the logical storage unit, there is a greater likelihood that, when a write operation is received for a data portion on the source logical storage unit or target logical storage unit after activation of the target LSU, the data portion will already be defined and not need to be defined when performing the write operation. When a write operation is received at the source logical storage unit, if the target logical storage unit is not active yet, the data of the write operation may be written to an allocated physical location for the data portion shared between the source and target logical storage units without updating any clone metadata.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sandeep Chandrashekhara, Michael Ferrari, Jeffrey Wilson, Mark J. Halstead, Art Longden
  • Patent number: 11226767
    Abstract: Methods, apparatuses, and systems related to die-to-die communications are described. An apparatus may include a master die and a set of slave dies communicatively coupled to each other through an internal bus. The master die may be configured to provide a combined external interface for both the master die and the set of slave dies. For the die-to-die communications, a target die may coordinate transfer of communicated data to the internal interface according to a timing signal generated by a source external to the set of slave dies.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Bret Johnson
  • Patent number: 11222689
    Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Daniel B. Penney
  • Patent number: 11211102
    Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Sik Moon, Kyung-Soo Ha, Young-Soo Sohn, Ki-Seok Oh, Chang-Kyo Lee, Jin-Hoon Jang, Yeon-Kyu Choi, Seok-Hun Hyun
  • Patent number: 11205499
    Abstract: A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 21, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Shu-Liang Ning
  • Patent number: 11195674
    Abstract: A break-before-make (BB4M) circuit topology is disclosed for use with a multiplexer that eliminates shoot-through current between analog inputs and also between an analog input and analog output. The BB4M circuit generates a pulse that disables an existing selected channel before enabling a newly selected channel or gate driver, and is suitable for use in high-radiation or outer space operating environments.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: December 7, 2021
    Assignee: Cobham Colorado Springs Inc.
    Inventors: Younes J. Lotfi, Thomas R. Richardson, James E. Colley
  • Patent number: 11188260
    Abstract: A memory module includes a plurality of memory devices; a plurality of data buffers suitable for exchanging data with a memory controller; and a module controller suitable for transferring the data between the memory devices and the data buffers based on a command, an address and a clock provided from the memory controller, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Ho Jung
  • Patent number: 11164623
    Abstract: Apparatuses, systems, and methods for data strobe write timing. A memory device may receive a data strobe clock signal and serial write data during a write operation. A deserializer circuit of the memory may convert the serial write data into parallel write data using timing based on the data strobe clock signal. For example, one or more internal signals may be generated based on the data strobe clock signal and used to activate various operations of the deserializer circuit. The data strobe clock signal may also be used to activate bit lines of the memory device in order to write the parallel write data to memory cells along those activated bit lines. The memory may also receive a system clock, separate from the data strobe clock signal, which may be used for other operations of the memory. For example, in a read operation, the bit lines may be activated with timing based on the system clock.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kohei Nakamura, Minari Arai
  • Patent number: 11158382
    Abstract: A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 26, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Akihiro Imamoto, Akio Sugahara
  • Patent number: 11150686
    Abstract: Apparatus and methods of reducing dock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control circuit. The clock control circuit includes a command/address domain configured to selectively provide a command/address clock signal based, at least in part, on a chip select signal. The clock control circuit further includes a command domain circuit configured to selectively provide a command clock signal based, at least in part, on the chip select signal. The clock control circuit further includes a column latency domain circuit configured to selectively provide a column latency clock signal based, at least in part, on a memory command. The clock control circuit further includes a four phase domain circuit configured to selectively provide a four phase clock signal based, at least in part, on the memory command.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 11152054
    Abstract: Apparatuses and methods can be related to performing operations in memory. Operations can be performed in the background while the memory is performing different operations. For example, comparison operations can be performed by the memory device while the memory device is reading data. The results of the comparison operations can be stored in registers of the memory device. The registers can be made accessible externally to the memory device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
  • Patent number: 11151037
    Abstract: Provided are a computer program product, system, and method for using track locks and stride group locks to manage cache operations. A group of tracks from the storage devices are stored in a cache. Exclusive track locks for tracks in the group in the cache are granted for writes to the tracks in the group in the cache, wherein exclusive track locks can be simultaneously held for writes to different tracks in the cache. An exclusive group lock for the group of tracks in the cache is granted to destage the tracks in the group from the cache to the storage devices. The exclusive group lock is released in response to completing the destage of the tracks in the group in the cache to the storage devices.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11145343
    Abstract: A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 12, 2021
    Assignee: FARADAY TECHNOLOGY CORPORATION
    Inventors: Sivaramakrishnan Subramanian, Hong-Yi Wu, Sridhar Cheruku, Ko-Ching Chao
  • Patent number: 11144410
    Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Stuart Allen Berke, Vadhiraj Sankaranarayanan
  • Patent number: 11144483
    Abstract: Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Atsushi Shimizu
  • Patent number: 11138107
    Abstract: Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Alan J. Wilson