Abstract: A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.

Abstract: A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Abstract: A variety of applications can include devices or methods that provide read processing of data in memory cells of a memory device without predetermined read levels for the memory cells identified. A read process is provided to vary a selected access line gate voltage over time, creating a time-variate sequence where memory cell turn-on correlates with programmed threshold voltage. Total string current of data lines of a group of strings of memory cells of the memory device can be monitored during a read operation of selected memory cells of the strings to which a ramp voltage with positive slope is applied to an access line coupled to the selected memory cells. Selected values of the change of the total current with respect to time, from the monitoring of the total current, are determined. Read points to capture data are based on the determined selected values. Additional devices, systems, and methods are discussed.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: A data sorting control circuit includes a phase detector suitable for detecting a phase of each of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal in response to a read command, an order determiner suitable for determining a data order as a first order or a second order based on a seed address and the detected phase of each of the clock signals, and an sorting control signal generator suitable for shifting the read command based on the first clock signal to the fourth clock signal to generate a first sorting control signal, a second sorting control signal, a third sorting control signal, and a fourth sorting control signal, and outputting the first sorting control signal to the fourth sorting control signal according to the first order or the second order.

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.

Abstract: Provided are a digital phase interpolator, a clock signal generator, and a volatile memory device including the clock signal generator. The clock signal generator includes an internal signal generator configured to generate a first internal signal and a second internal signal, which mutually have a phase difference, based on an external clock signal, a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal and generate a first interpolation signal, a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal and generate a second interpolation signal, and a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal and output the selected interpolation signal as an internal clock signal.

Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

Abstract: An apparatus is provided for management of client devices for maintenance of a structural product. The apparatus is caused to receive device manifest reports that include information about the client devices and digital content hosted by respective library apps on the client devices. The apparatus is caused to generate a graphical user interface (GUI) to visually summarize the information, with the GUI embodied as a dashboard with a layout of software widgets. And the apparatus is caused to send the dashboard to an administrative device for display. This causes execution of the layout of software widgets on the dashboard at the administrative device to access the information from the content management platform, produce respective infographics to visually summarize the client devices and the digital content hosted by the respective library apps, based on the information, and display the respective infographics in the dashboard at the administrative device.

Abstract: An operating method of a storage device includes monitoring a temperature of a nonvolatile memory device including a plurality of memory blocks, receiving a first request from a host, in response to the first request, transmitting a first command to the nonvolatile memory device when a first memory block corresponding to the first request is exposed at a temperature of a threshold temperature or higher for a first time period that is equal to or greater than a threshold time period and a second command to the nonvolatile memory device when the first memory block is exposed at a temperature lower than the threshold temperature for the threshold time period, charging word lines of the first memory block with a driving voltage in response to the first command, and performing a first operation corresponding to the first request in response to the first command or the second command.

Abstract: Provided are an operating method of a host device, an operating method of a memory device, and a memory system. The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.

Abstract: In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.

Abstract: A computer system generates information describing authenticity and a grade of a collectible scanned by a scanning device. A feature vector is extracted from the information. The feature vector includes a first set of features and a second set of features. The first set of features is matched to authenticity profiles of collectible items. Each authenticity profile characterizes at least one collectible item across multiple features. A confidence score is generated with respect to the authenticity of the collectible based on the authenticity profiles. The second set of features is matched to grade profiles of the collectible items. A grade score describing the grade of the collectible is generated based on the grade profiles. The grade of the collectible is determined based on the grade score. A graphical representation of the grade and the confidence score is transmitted to a display device.

Abstract: A data input buffer includes a plurality of buffer units configured to receive a first impedance calibration code and a second impedance calibration code, wherein each of the plurality of buffer units outputs an offset detected with a first input terminal and a second input terminal thereof short-circuited, as write data, and wherein a buffer unit corresponding to a current value of the first impedance calibration code among the plurality of buffer units is configured to correct the offset according to the second impedance calibration code.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: Embodiments relate to a transmission circuit, a transmission method, a storage apparatus, and a storage medium. The transmission circuit includes a comparison module and a data conversion module. The comparison module is configured to receive first data on a first data line and second data on a second data line, and compare the first data with the second data to output a comparison result indicating whether number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width. The data conversion module is electrically connected to the first data line, the comparison module and the second data line, and is configured to invert the first data and transmit the inverted first data to the second data line when the comparison result is indicative of exceeding the preset threshold.

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

Abstract: A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.

Abstract: A system performs analog memory sanitization by forcing voltage levels in memory cells to substantially the same voltage level so that they are indistinguishable regardless of the data that has been previously stored in the cells. In some embodiments, a special programming operation for sanitizing a plurality of memory cells forces the charge in the cells to approximately the same voltage level by increasing the voltage level of all cells regardless of the data currently stored in the cells. As an example, each cell may be programmed to a logical high bit value (e.g., a “0”) by increasing the charge in each cell to a voltage level that is greater than the voltage level for writing the same logical bit value in a normal programming operation. Thus, after the programming operation is performed, the voltage levels of cells storing one logical bit value (e.g., a “0”) prior to the programming operation may be indistinguishable from voltage levels of cells storing a different logical bit value (e.g.

Abstract: According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.

Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

Abstract: Systems and methods are provided for bringing a volume of a consistency group (CG) into an in-synchronization (InSync) state while other volumes of the CG remain in the InSync state. According to an example, in order to support recovery from disruptive events in a manner that ensures a zero recovery point objective (RPO) guarantee and insulates an application making use of the CG from adverse impacts, responsive to a triggering event, a Fast Resync process may first be attempted to promptly bring an affected volume back into an in-synchronization (InSync) state from an out of synchronization (OOS) state while allowing other members of the CG to remain in the InSync state. Should the Fast resync process be unsuccessful in bringing the volume back into the InSync state within a predetermined or configurable time threshold, then a second type of resynchronization process may be employed at the CG level.

Abstract: A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.

Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

Abstract: A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.

Abstract: A module, comprising: a printed circuit board (PCB); a power and management connector disposed on the PCB to connect to a computing device via a first cable; a data connector disposed on the PCB to connect to the computing device via a second cable; and a memory slot, to accept a memory device, disposed on the PCB and connected to the power and management connector and the data connector.

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.

Abstract: An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

Abstract: Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.

Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a sensing node, a bit line controller connected between the sensing node and a bit line. The bit line controller is configured to first precharge and second precharge the sensing node.

Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, a control logic, and a voltage generator. The memory cell array includes memory cells. The page buffer is connected to the memory cells through a bit line and configure to read data of the memory cells. The control logic generates control signals for controlling the page buffer. The voltage generator generates activation voltages of the control signals. The page buffer includes a first transistor between the bit line and a first node, a second transistor between a power voltage and a second node, a third transistor between the first node and the second node, a fourth transistor between the second node and a third node, and a fifth transistor between the first node and the third node. The voltage generator controls a first control signal controlling the fifth transistor based on temperature of the semiconductor memory device.

Abstract: The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Abstract: Apparatuses and methods related to a memory module controller are disclosed. An example apparatus, such as a dual in-line memory module (DIMM), includes a first interface coupled to a host, and a second interface coupled to another memory module. The memory module includes a controller configured to simultaneously communicate with the host via the first interface, which may be a non-volatile DIMM (NVDIMM) interface in one example, and communicate with the other memory module via the second interface. In some examples, the first and second interfaces are configured according to different standards or protocols. The controller controls access to memory on the memory module. The controller may be configured to receive commands from a direct memory access (DMA) module. In some examples, the other memory module connected via the second interface includes a local controller and memory of a different type.

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.