Having Particular Data Buffer Or Latch Patents (Class 365/189.05)
  • Patent number: 11061852
    Abstract: A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: July 13, 2021
    Assignee: Arm Limited
    Inventors: Mbou Eyole, Emre Ozer, Xabier Iturbe, Shidhartha Das
  • Patent number: 11062754
    Abstract: Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 11062747
    Abstract: An example apparatus includes a first circuit configured to generate a first enable signal based on a first clock signal and a first command signal, a second circuit configured to generate a second enable signal based on the first clock signal and a second command signal, a third circuit configured to generate a second clock signal based on the first clock signal when the first enable signal is activated, a fourth circuit configured to generate a third clock signal based on the first clock signal when the second enable signal is activated, a first latch circuit configured to latch the second command signal in response to the second clock signal to generate a third command signal, and a second latch circuit configured to latch the third command signal in response to the third clock signal to generate a fourth command signal.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Atsuko Momma
  • Patent number: 11056162
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Sun Yoon, Dong Hyuk Chae
  • Patent number: 11057672
    Abstract: A node (200) of a communication network determines a precision to be applied for reporting of consumption of streamed content. The node (200) sends configuration information (304) indicating the precision towards a plurality of client devices (10). After receiving reports of consumption (308) of the streamed content from at least some of the client devices (10), the node (200) adapts the precision to be applied for said reporting of consumption of the streamed content and sends further configuration information indicating the adapted precision towards the client devices (10).
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: July 6, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Victoria Matute Arribas, Thorsten Lohmar, Lukas Ruge
  • Patent number: 11048645
    Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 29, 2021
    Inventors: Sun-Young Lim, Dimin Niu, Jae-Gon Lee
  • Patent number: 11048439
    Abstract: A memory device is provided. The device comprises a substrate, a controller, at least a tap, a plurality of memory modules, and at least two resistors. The controller connects to the substrate. The tap, the memory modules, and the resistors are set on the substrate. The tap comprises an input terminal connecting to the controller; a first output terminal; and a second output terminal. After connecting to each other in series, the memory modules connect to the first output terminal and the second output terminal. Each of the resistors connects to one of the memory modules which connect to the first output terminal and the second output terminal. Thus, command signals, address signals, and timing signals are separately sent to the memory modules through the first output terminal and the second output terminal of the tap simultaneously to process instruction or read information by the controller.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: June 29, 2021
    Assignee: EOREX CORPORATION
    Inventors: Cheng-Lung Lin, Wan-Tung Liang
  • Patent number: 11049534
    Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyung Ho Chu, Soo Bin Lim, Yong Suk Joo
  • Patent number: 11036630
    Abstract: A memory system includes: a memory device; and a controller suitable for performing: a free block management operation of detecting victim blocks onto which a garbage collection operation is to be performed to generate required free blocks; a garbage collection operation time management operation of calculating an estimated garbage collection operation time for the detected victim blocks; and a garbage collection operation period management operation of dynamically changing a garbage collection operation period based on the estimated garbage collection operation time and periodically performing a garbage collection operation based on the garbage collection operation period during a specific time, wherein the controller repeatedly performs, whenever an update period arrives, the free block management operation, the garbage collection operation time management operation, and the garbage collection operation period management operation.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11037626
    Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 15, 2021
    Inventors: Hyun-Jin Kim, Chung-Ho Yu, Yong-Kyu Lee, Jae-Yong Jeong
  • Patent number: 11024362
    Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 1, 2021
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Suresh Rajan, Scott C. Best
  • Patent number: 11024367
    Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dale H. Hiscock, Debra M. Bell, Michael Kaminski, Joshua E. Alzheimer, Anthony D. Veches, James S. Rehmeyer
  • Patent number: 11010056
    Abstract: A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 18, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Fei Xia, Mingyu Chen, Dejun Jiang, Jin Xiong
  • Patent number: 11011212
    Abstract: Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuration that includes a pulse generator. The pulse generator may be configured to output a pulse signal responsive to a transition of an input signal. By generating a pulse signal in a feedback loop of a ring oscillator, the ring oscillator may support a cycle that does not rely on both a first transition propagation pass (e.g., a rising edge propagation) and a responsive, opposite transition propagation pass (e.g., a falling edge propagation) through the delay chain, which may support a ring oscillator cycle time (e.g., period) that more closely represents aspects of the delay chain that are meant to be calibrated.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Hiroshi Akamatsu
  • Patent number: 11011220
    Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 11010336
    Abstract: A system and method include receiving, by a database engine of a database system associated with a virtual computing system, a user request via a dashboard for provisioning a source database with the database system, receiving, by the database engine via the dashboard, selection of a database engine type, and receiving, by the database engine via the dashboard, selection of a Service Level Agreement (“SLA”) and a protection schedule. The system and method also include provisioning, by the database engine, the source database based upon the database engine type, creating, by the database engine, an instance of a database protection system based upon the SLA and the protection schedule, including associating the instance of the database protection system with the source database, and displaying, by the database engine, the source database within the dashboard.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 18, 2021
    Assignee: Nutanix, Inc.
    Inventors: Balasubrahmanyam Kuchibhotla, Kamaldeep Khanuja, Jeremy Launier, Sujit Menon, Maneesh Rawat
  • Patent number: 11011221
    Abstract: Apparatuses and methods for signal line buffer timing control are disclosed. An example apparatus includes a plurality of signal lines including first and second control lines and further including data lines, and further includes first and second signal line buffers. The first signal line buffer includes first driver circuits configured to drive respective data signals on the data lines and to drive first and second control signals on the first and second control lines, respectively. The second signal line buffer includes second driver circuits configured to be activated to receive the data signals. The first and second control signals arrive at the second signal line buffer at different times. The second driver circuits are activated responsive a later one of active first and second control signals and are deactivated responsive to an earlier one of inactive first and second control signals.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Keisuke Fujishiro, Yoshifumi Mochida
  • Patent number: 11005475
    Abstract: An emission driver includes a latch circuit and a buffer circuit. The latch circuit receives a first signal, a second signal, and a first clock signal. The latch circuit includes a first output terminal and a second output terminal. The first output terminal of the latch circuit outputs a third signal according to the first clock signal. The second output terminal of the latch circuit outputs a fourth signal in reverse to the third signal according to the first clock signal. The buffer circuit includes a first input terminal, a second input terminal and a third output terminal. The first input terminal of the buffer circuit receives the third signal. The second input terminal of the buffer circuit receives the fourth signal. The third output terminal of the buffer circuit outputs an emission signal according to the third signal and the fourth signal.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 11, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Kazuyuki Hashimoto, Hirofumi Watsuda, Hidetoshi Watanabe
  • Patent number: 11003986
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10998047
    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 4, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Can Li, Catherine Graves, John Paul Strachan
  • Patent number: 10990160
    Abstract: A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 27, 2021
    Assignee: GOWIN Semiconductor Corporation
    Inventor: Jinghui Zhu
  • Patent number: 10983936
    Abstract: A programmable arbitrary sequence direct memory access (DMA) controller accesses sequentially addressed memory locations (source or destination) using address pointer registers. Each sequentially addressed memory location containing an indirect memory address is stored in an address latch and used to access the actual non-sequential memory location to be accessed by the DMA transfer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 20, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Keith Edwin Curtis
  • Patent number: 10977118
    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng, Hyun-Joong Kim, Won-hyung Song, Jangseok Choi
  • Patent number: 10971200
    Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD?.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 6, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hsuan Lin, Chao-Hung Wang
  • Patent number: 10964702
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Patent number: 10964361
    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 30, 2021
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, Ely K. Tsern
  • Patent number: 10956268
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Bryan K. Casper, Stephen R. Mooney, David Dunning, Mozhgan Mansuri, James E. Jaussi
  • Patent number: 10956090
    Abstract: Life of a non-volatile memory is extended without increasing processing time due to turning power ON/OFF. An EEPROM stores counter information and setting information, a first RAM and a second RAM store counter information and setting information, a memory management unit manages a storage area in the first RAM for the counter information and setting information so as to be updatable and manages a storage area in the second RAM for the counter information and setting information so as not to be updatable, and a system control unit, when a change in contents of the counter information and the setting information occurs, rewrites the counter information and the setting information in the first RAM in accordance to the changed contents, and when the power is turned OFF, reads and compares the counter information and the setting information in the first RAM with the counter information and the setting information in the second RAM, and writes only different data to the EEPROM.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 23, 2021
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Yukio Iwasaki
  • Patent number: 10957391
    Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, Jr., Dean L. Lewis
  • Patent number: 10950314
    Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
  • Patent number: 10950280
    Abstract: A semiconductor device includes an information signal generation circuit configured to store the register information depending on an input control signal generated based on the mode register read command, and output the stored register information depending on an output control signal generated based on the mode register read command.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10943629
    Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Hyeong Soo Jeong
  • Patent number: 10937466
    Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-hwan Jeon
  • Patent number: 10917093
    Abstract: A memory system includes a memory device with a termination circuit providing a termination impedance for a data signal in the memory device. The device also includes a calibration circuit configured to set the termination impedance to a predetermined value. The device further includes an impedance adjustment circuit configured to adjust the termination impedance based on a feedback signal indicating a change in the termination impedance due to at least one of a change in a temperature of the memory device or a change in voltage of a voltage bus in the memory device.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 10916291
    Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 9, 2021
    Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG LEE UNIVERSITY
    Inventors: Hyuk Jae Lee, Hyun Kim, Duy Thanh Nguyen, Bo Yeal Kim, Ik Joon Chang
  • Patent number: 10916327
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for fuse latch and match circuits. A memory may include a number of fuse registers, each of which is associated with a line of redundant memory cells. An address may be stored in fuse latches of the fuse register. A dynamic logic circuit may activate one of the fuse registers and a match logic circuit may compare the address stored in the activated fuse register to an address received as part of an access operation to determine if the redundant memory cells should be accessed. The fuse latches may be floated during a power up operation. The dynamic logic circuit may control a timing of the activation and comparison operation.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 10914769
    Abstract: According to an aspect of a present invention, there is provided a semiconductor device including a first power monitoring device and a second power monitoring device. The first power monitoring device outputs first operating power that is to be supplied to a second control section. The second power monitoring device outputs second operating power that is to be supplied to a first control section. Based on a first setting given from the first control section, a first power monitoring circuit autonomously verifies whether the second operating power is normal, and periodically transmits the result of verification to the second control section as first error information. Based on a second setting given from the second control section, a second power monitoring circuit autonomously verifies whether the first operating power is normal, and periodically transmits the result of verification to the first control section as second error information.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 9, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiki Yamahira, Masahiro Sakai
  • Patent number: 10901454
    Abstract: A memory is provided with a logic gate that processes a first version and a second version of a memory clock signal to assert a clock signal for the clocking of latches in a second array of columns for the memory. The first version clocks the latches in a first array of columns for the memory. But the second version does not clock any latches in the first array of columns.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 26, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Shiba Narayan Mohanty, Rakesh Kumar Sinha
  • Patent number: 10892002
    Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kazutaka Miyano
  • Patent number: 10891993
    Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam, Qiang Tang, Eric N. Lee
  • Patent number: 10892031
    Abstract: Storage capacity optimization of non-volatile memory is shown. Through a controller, communication between a host and a non-volatile memory is in units of a first data length. The controller manages a bad column table for the non-volatile memory in units of a second data length. The second data length is shorter than the first data length. Taking byte communication as an example, one nibble of storage units is marked as bad when it has any damaged storage units.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: January 12, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Yi-Hung Yuan
  • Patent number: 10892005
    Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Xinyu Wu, Dong Pan
  • Patent number: 10872644
    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 22, 2020
    Inventors: Hidehiro Fujiwara, Yen-Huei Chen
  • Patent number: 10867240
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10854271
    Abstract: Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers a arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toshiaki Tsukihashi
  • Patent number: 10846229
    Abstract: A memory device controls a page buffer to ensure the reliability of data. The memory device includes: a memory cell array including a plurality of memory cells configured for storing data; first and second page buffers respectively including main latches and cache latches, which are coupled to a bus, the first and second page buffers being connected to the memory cell array respectively through bit lines coupled to the main latches; and control logic including a bus precharge controller for differently setting a voltage level of the bus, based on a distance between a reference position and the first page buffer and a distance between the reference position and the second page buffer, for precharging of the bus for transmitting data of a cache latch included in each of the first and second page buffers to a corresponding main latch.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Won Jae Choi, Tae Heui Kwon
  • Patent number: 10847194
    Abstract: An input/output circuit includes a data buffer group configured to buffer data received through data lines, a data strobe buffer configured to buffer a data strobe signal to output a buffered data strobe clock, a digitally controlled delay line configured to output delay data by controlling skew of the buffered data according to a delay code, a data strobe clock output circuit configured to generate a delay data strobe clock in response to the buffered data strobe clock, a sampler configured to sample the delay data according to the delay data strobe clock to output sampled data, and a de-skew circuit configured to update the delay code according to the sampled data.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong Hyun Kim, Dae Han Kwon, Kwan Su Shon, Soon Ku Kang, Jung Hyun Shin, Doo Bock Lee, Yo Han Jeong, Eun Ji Choi, Tae Jin Hwang
  • Patent number: 10846190
    Abstract: One embodiment provides a method, including: identifying, using a processor, a connection of a device to an information handling device; receiving, at the information handling device, an indication of a user selection action on the device; and performing, responsive to receiving the indication, an action on the information handling device. Other aspects are described and claimed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventor: Jonathan Randall Hinkle
  • Patent number: 10834444
    Abstract: Convenience in a decoding process on a receiver side for when a predetermined number of high-quality-format image data is transmitted together with basic-format image data is achieved. A base stream including, as an access unit, encoded image data for each picture of basic-format image data, and a predetermined number of enhanced streams, each including, as an access unit, encoded image data for each picture of high-quality-format image data are generated. Here, a predictive coding process is performed on image data in high-quality format by referring to the image data in basic format or image data in another high-quality format, by which an enhanced stream is generated. Then, information indicating decoding order is added to each access unit of the enhanced streams. A container in a predetermined format that includes the base stream and the predetermined number of enhanced streams is transmitted.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: November 10, 2020
    Assignee: SONY CORPORATION
    Inventor: Ikuo Tsukagoshi
  • Patent number: 10831979
    Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy