Particular Decoder Or Driver Circuit Patents (Class 365/230.06)
  • Patent number: 11562778
    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 24, 2023
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Frederick A. Ware, William N. Ng
  • Patent number: 11538540
    Abstract: The present disclosure provides an information tamper-resistant system and method. The system includes: a storage module; a writing module connected with the storage module through a first OTP switch, to write source information to the storage module; a first reading module connected with the storage module through a second OTP switch, to read out written information in the storage module and disconnect the first OTP switch and the second OTP switch after confirming that the written information is accurate; and a second reading module connected with the storage module through a third OTP switch, to read out information stored in the storage module after the third OTP switch is switched on; the first OTP switch, the second OTP switch, and the third OTP switch can only perform one switch-on operation or one switch-off operation. The system and method effectively avoid theft and tampering of information.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: December 27, 2022
    Assignee: Montage Technology (Kunshan) Co., Ltd.
    Inventors: Xiong Zhang, Gang Shi
  • Patent number: 11522014
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 11514979
    Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 29, 2022
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, Jr.
  • Patent number: 11500791
    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chulbum Kim, Mark A. Helm, Yoav Weinberg
  • Patent number: 11501822
    Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 15, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jianquan Jia, Ying Cui, Kaikai You
  • Patent number: 11495499
    Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 8, 2022
    Assignee: Arm Limited
    Inventors: Amit Chhabra, David Victor Pietromonaco
  • Patent number: 11482270
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 25, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11474739
    Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N?2)th batch of program data, N being an integer equal to or greater than 2, program an (N?1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 18, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Chun Yuan Hou
  • Patent number: 11466685
    Abstract: Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Mieko Kojima
  • Patent number: 11462259
    Abstract: Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 11456042
    Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: September 27, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Jiahui Yuan, Abhijith Prakash
  • Patent number: 11443175
    Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: September 13, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do
  • Patent number: 11435940
    Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: September 6, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Mohamed Azimane
  • Patent number: 11430709
    Abstract: A semiconductor device is provided, including multiple memory chips and a temperature detection module. The temperature detection circuit includes: multiple temperature sensitive units, arranged on the memory chips to detect temperatures of the memory chips; and a processing unit. The multiple temperature sensitive units share the processing unit with each other. The processing unit is configured to process a signal of at least one of the temperature sensitive units. The processing unit includes a calibration value memory cell and a calibration unit. The calibration value memory cell is configured to store a calibration value corresponding to the temperature sensitive unit. The calibration unit is configured to calibrate the temperature sensitive unit according to the calibration value.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: August 30, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shuliang Ning
  • Patent number: 11417372
    Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
  • Patent number: 11417388
    Abstract: Semiconductor devices that include circuitry to mitigate unstable or metastable states in logic circuits in response to receipt of an unassigned row address. The semiconductor device may include one or more logic circuits that are configured to adjust particular address-based control signals to mitigate processing based on the unassigned row address. For example, the one or more logic circuits may override processing of the unassigned row address to provide control signals that correspond to an assigned row address, which may allow the semiconductor device to operate in a known state, rather than performing operations based on an unassigned row address.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takayuki Miyamoto, Satoshi Yamanaka
  • Patent number: 11417368
    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tomoko Ogura Iwasaki, Foroozan Koushan, Jayasree Nayar, Ji-Hye Gale Shin
  • Patent number: 11410738
    Abstract: A word line decoding circuit and memory comprises a first address decoding module to obtain word line logic signals; a word line pre-coding module to obtain word line pre-coding signals and first switch signals; a second address decoding module to obtain first and second selection signals; a third address decoding module to obtain third selection signals; a first level conversion module which performs level conversion on the first selection signals to obtain first and second control signals; a second level conversion module which performs level conversion on the second selection signals to get third and fourth control signals; a third level conversion module which performs level conversion on the third selection signals to obtain fifth control signals; a word line toggle switch signal generation module which generates second switch signals based on each control signal; and a word line toggle module to generate word line signals.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 9, 2022
    Assignee: CHINA FLASH CO., LTD.
    Inventors: Hong Nie, Zeyu Zhu, Yue Zhao, Ying Sun
  • Patent number: 11403173
    Abstract: A memory device includes content banks configured to store content data and parity banks configured to store parity data for reconstructing the content data. In response to receiving, in a first clock cycle, a first request requesting a first operation to be performed in a first content bank and a second request requesting to write new content data to the first content bank, the memory device performs the first operation in the first content bank, and writes the new content data to a second content bank. The second content bank is selected from a subset of content banks defined by content banks that correspond with parity banks different from parity banks that correspond with the first content bank. The memory device updates, based on the new content data written to the second content bank, parity data in the parity banks that correspond with the second content bank.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 2, 2022
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Roi Sherman, Dror Bromberg
  • Patent number: 11398269
    Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: July 26, 2022
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Chikara Kondo
  • Patent number: 11386935
    Abstract: A charge pump circuit includes a first transistor having a drain connected to an input node, and a source connected to a first node; a second transistor having a drain connected to the first node, and a source connected to an output node; a first capacitor between the first and second nodes; a first inverter including an input node to which a clock signal is supplied and an output node connected to the second node via a first line; a first voltage detection circuit which includes an input node connected to the first line; a third transistor having a source connected to a third node, and a drain connected to the second node; a second inverter including an input node connected to the first voltage detection circuit and an output node connected to a fourth node via a second line; and a second capacitor between the third and fourth nodes.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Takumi Fujimoto
  • Patent number: 11380401
    Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 11373701
    Abstract: A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Sung, Sung Lae Oh, Je Hyun Choi
  • Patent number: 11366487
    Abstract: A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: June 21, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Koji Ito
  • Patent number: 11367507
    Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hua-Tai Shieh
  • Patent number: 11355206
    Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 11342019
    Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Pao, Shih-Hao Lin, Kian-Long Lim
  • Patent number: 11328642
    Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: May 10, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangliang Shang, Lijun Yuan, Haoliang Zheng, Libin Liu, Xing Yao, Seungwoo Han
  • Patent number: 11328763
    Abstract: A semiconductor memory device includes a common driver suitable for generating a preliminary driving signal according to a voltage at a first node; and a plurality of individual drivers suitable for providing a core voltage to a sense amplifying circuit of a corresponding one of a plurality of cell mats, according to the preliminary driving signal, wherein each of the individual drivers includes: a level shifting circuit suitable for outputting a main driving signal by shifting a level of the preliminary driving signal when a corresponding mat select signal and a pull-up driving signal are activated; a pull-up driver suitable for driving a pull-up power line with the core voltage according to the main driving signal; and a switch suitable for coupling the first node to the pull-up power line when the corresponding mat select signal and the pull-up driving signal are activated.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Man Im
  • Patent number: 11322197
    Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
  • Patent number: 11315625
    Abstract: The invention relates to a data edge jumping method, applied to a memory system, wherein the memory system comprises a processor and a memory driven by the processor, and a plurality of groups of data lines are connected between the processor and the memory. The data edge jumping method comprising: coding data output by the processor to enable total current produced by data transmission through each of the plurality of groups of data lines at the same time to be zero; transmitting the coded data through the plurality of groups of data cables, and decoding the data before reaching the memory; and inputting the decoded data into the memory, and enabling the total current produced in the data lines to be close to 0 A, so that electromagnetic interference is hardly produced by signals transmitted through the data lines, and allowance of signal radiation is large enough.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 26, 2022
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventors: Chuanting Xu, Kun Zhang
  • Patent number: 11314462
    Abstract: An interface circuit includes; a transmitter interface circuit including an output pad and configured to receive a first input data signal and generate a second input data signal from the first input data signal, and a receiver interface circuit including an input pad and configured to receive the second input data signal via the output pad and an internal channel The transmitter interface circuit also includes an equalization signal generation circuit configured to receive the first input data signal, generate a pulse signal by delaying the first input data signal by applying a target delay time or a target width adjustment to the first input data signal, generate an equalization signal based on the pulse signal, and provide the equalization signal to the output pad to suppress a reflected wave on the internal channel.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 26, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kihwan Seong, Donguk Park
  • Patent number: 11309512
    Abstract: An organic EL display device includes a reflective electrode and a transparent electrode disposed facing each other with an organic EL layer interposed therebetween. The reflective electrode includes a reflective film and a protection film formed on the reflective film, and the protection film includes a frame-shaped portion surrounding the periphery of the organic EL layer and an opening surrounded by the frame-shaped portion. This improves the reflectivity of the reflective electrode while protecting the reflective electrode.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 19, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tetsunori Tanaka
  • Patent number: 11308887
    Abstract: A display panel and a display device are disclosed, the display panel includes a plurality of display regions, a peripheral region surrounding the plurality of display regions, a plurality of light-emission control scan driving circuits provided in the peripheral region, a first start signal line, and a second start signal line. The first start signal line is different from the second start signal line, the plurality of display regions include a first display region and a second display region, the plurality of light-emission control scan driving circuits include a first light-emission control scan driving circuit and a second light-emission control scan driving circuit, the first start signal line is configured to provide a first start signal to the first light-emission control scan driving circuit, and the second start signal line is configured to provide a second start signal to the second light-emission control scan driving circuit.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 19, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yue Long, Chao Zeng, Yao Huang, Meng Li, Weiyun Huang, Libin Liu
  • Patent number: 11302388
    Abstract: A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: April 12, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Arun Babu Pallerla, Changho Jung
  • Patent number: 11302397
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 11302378
    Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Christoph Raisch
  • Patent number: 11302396
    Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: April 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
  • Patent number: 11302381
    Abstract: Methods, systems, and devices for driving word lines using sub word line drivers are described. A memory array may include a plurality of sub-arrays arranged with gaps in between. Word lines may be arranged across multiple sub-arrays and drive access transistors that are used to selectively access rows (e.g., rows of memory cells) within the sub-arrays. In some examples, signals applied to selection devices driving the word lines may be over-driven for a duration at or near the desired transitions of the word line, and some signals may be driven to a relatively high level for a duration around the high and low transitions of a global row line. Whether a signal is over driven or driven to a relatively high level may depend on the type or types of transistors used in each word line driver.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Brenton P. Van Leeuwen
  • Patent number: 11270746
    Abstract: A word line driver circuit is disclosed. A word line driver circuit may include a circuit configured to generate a clamped voltage based on a first fixed supply voltage and in response to receipt of a first control signal triggering an active mode. The circuitry may further be configured to generate an internal global word line voltage based on the clamped voltage during the active mode. Further, the word line driver circuit may include at least one main word line driver configured to receive the internal global word line voltage and generate a global word line voltage. Additionally, the word line driver circuit may include at least one sub word line driver configured to receive the global word line voltage and generate a word line voltage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Tae H. Kim
  • Patent number: 11257532
    Abstract: Apparatuses and methods for driving word driver lines in a gradual manner are disclosed herein. Word driver lines may be driven to intermediate potentials between high and low potentials. In some examples, the word driver lines may be driven in a step-wise manner. In some examples, the intermediate potential may be a bias voltage. The bias voltage may be provided by a bias voltage generator. One or more enable signals may be used to control the driving of the word driver line. In some examples, an address signal may be used to control the driving of the word driver line. Driving the word driver line in a gradual manner may cause a word line to discharge in a gradual manner in some examples.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Takamasa Suzuki
  • Patent number: 11257553
    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: February 22, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu
  • Patent number: 11226907
    Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11211113
    Abstract: Some embodiments include an integrated assembly having first and second wordlines coupled with DRIVER circuitry. The first wordline has a first end distal from the DRIVER circuitry, and the second wordline has a second end distal from the DRIVER circuitry. A switch is adjacent to the first end and is configured to couple said first end to one or both of the second end and a LOW-VOLTAGE-REFERENCE-SOURCE (e.g., a VNWL supply) during a transition of the first wordline from an “ON” state to an “OFF” state.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 11210983
    Abstract: The present disclosure relates to a display, and more particularly, to a display including a multiplexer capable of implementing a high-voltage driving, a low-consumption power driving, and a high-speed switching. A display including a multiplexer according to the present disclosure includes a data driver for outputting image data; a multiplexer connected with the data driver through a driving line; a display panel connected with the multiplexer through a data line; and a gate driver connected with the display panel through a gate line, and the multiplexer includes a first TFT controlled by the charging and the discharging of a first mux line; and a second TFT controlled by the charging and the discharging of a second mux line.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 28, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: YongHo Jang, TaeWoong Moon, Uyhyun Choi
  • Patent number: 11188456
    Abstract: A storage system and method for predictive block allocation for efficient garbage collection are provided. One method involves determining whether a memory in a storage system is being used in a first usage scenario or a second usage scenario; in response to determining that the memory is being used in the first usage scenario, using a first block allocation method; and in response to determining that the memory is being used in the second usage scenario, using a second block allocation method, wherein the first block allocation method allocates blocks that are closer to needing garbage collection than the second block allocation method.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 30, 2021
    Inventors: Ariel Navon, Micha Yonin, Alexander Bazarsky, Judah Gamliel Hahn, David Gur, Omer Fainzilber
  • Patent number: 11189336
    Abstract: A word line driving device of a memory device is provided. The word line driving device of the memory device includes a word line, a word line driver, and a conducting line. The word line is disposed on a first metal layer. The word line is connected to a plurality of memory cells in a memory array. The word line driver is coupled to a first node of the word line. The conducting line is disposed on a second metal layer. The first node of the word line is coupled to a first node of the conducting line and a second node of the word line is coupled to a second node of the conducting line. The distance of the second metal layer with respect to a plurality of transistors in the memory device is greater than a distance of the first metal layer with respect to the plurality of transistors in the memory device.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ku-Feng Lin
  • Patent number: 11164621
    Abstract: A sense amplifier and a semiconductor device which are less likely to be influenced by a variation in transistor characteristics and their operation methods are provided. An amplifier circuit in a sense amplifier includes a first circuit and a second circuit, each including an inverter, a first transistor, a second transistor, and a capacitor. A first terminal and a second terminal of the capacitor are electrically connected to a first bit line and an input terminal of the inverter, respectively. The first transistor and the second transistor function as a switch that switches conduction and non-conduction between the input terminal and an output terminal of the inverter, and a switch that switches conduction and non-conduction between the output terminal of the inverter and the second bit line, respectively. The first circuit and the second circuit are initialized by a potential obtained when conduction is established between the input terminal and the output terminal of the inverter.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: November 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura
  • Patent number: 11164614
    Abstract: Systems and method are provided for a memory circuit. A predecoder circuit is configured to receive a first address signal, a first clock signal, and a second clock signal. The predecoder circuit is configured to generate a selection signal based on the first clock signal and the first address signal. And the predecoder circuit is further configured to maintain the selection signal based on the second clock signal and the first address signal.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Sanjeev Kumar Jain