Particular Decoder Or Driver Circuit Patents (Class 365/230.06)
  • Patent number: 11948657
    Abstract: Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Eric J. Schultz
  • Patent number: 11901009
    Abstract: An address decoding circuit includes a decoding unit corresponding to a bank group and including first NAND gates, an address selection signal outputted by each first NAND gate controls a corresponding bank in the bank group corresponding to the decoding unit. The first NAND gate includes a first input end connected to an address signal of a bank corresponding to the first NAND gate and a second input end connected to an output end of a second NAND gate or a third NAND gate, the second NAND gate includes a first input end connected to an enable signal and a second input end connected to a control signal, and the third NAND gate includes a first input end connected to the enable signal and a second input end connected to an inverted signal of the control signal.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 13, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan Gu
  • Patent number: 11887649
    Abstract: Methods of operating a number of memory devices are disclosed. A method may include receiving, at each of a number of memory devices, a refresh command. The method may also include refreshing, at each of the number of memory devices and in response to the refresh command, a number of memory cells based on a count of an associated refresh address counter, wherein a count of a refresh address counter of at least one memory device of the number of memory devices is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. Related systems and memory modules are also described.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 30, 2024
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
  • Patent number: 11869592
    Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 9, 2024
    Inventors: Gary L. Howe, Scott E. Smith
  • Patent number: 11862231
    Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: January 2, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
  • Patent number: 11862230
    Abstract: A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: January 2, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jianquan Jia, Ying Cui, Kaikai You
  • Patent number: 11854608
    Abstract: The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: December 26, 2023
    Inventors: Babak Mohammadi, Joachim Neves Rodrigues
  • Patent number: 11837286
    Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventor: John Christopher Sancon
  • Patent number: 11830539
    Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.
    Type: Grant
    Filed: September 25, 2022
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junsoo Kim, Minwoo Kwon
  • Patent number: 11830553
    Abstract: The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Cheng-Jer Yang
  • Patent number: 11823734
    Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 21, 2023
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 11817151
    Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including maintaining a counter to track a number of memory access operations performed on a range of consecutive wordlines in a block of the memory device. The operations further include determining that the number of memory access operations performed on the range of consecutive wordlines satisfies a threshold criterion. The operations further include, responsive to the number of memory access operations performed on the range of consecutive wordlines satisfying the threshold criterion, causing a memory management operation to be performed at each wordline of the range of consecutive wordlines in the block of the memory device.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Laura Varisco, Swetha Bongu, Kirthi Ravindra Kulkarni, Soujanya Venigalla
  • Patent number: 11815995
    Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: November 14, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Che-Wei Liang, Shuo-Nan Hung, Hung-Wei Lu, Ming-Cheng Tu
  • Patent number: 11810643
    Abstract: A word line driving circuit includes a first circuit and a second circuit. The first circuit is configured to provide a first word line driving voltage and a second word line driving voltage based on a first control signal, a second control signal, a first bias voltage, a second bias voltage and a base voltage. The second circuit is configured to provide the first control signal and the second control signal based on a third control signal, a fourth control signal, a word line control signal, a reverse word line control signal, the first bias voltage, the second bias voltage and the base voltage. The first bias voltage and the second bias voltage have different levels during the read mode and the program mode for adaptively adjusting the read voltage and the program voltage, thereby improving the data access time.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Ho, Min-Chia Wang, Hsiu-Ming Yeh, Chung-Ming Lin
  • Patent number: 11810641
    Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christian N. Mohr, Jennifer E. Taylor, Vijayakrishna J. Vankayala
  • Patent number: 11800825
    Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: October 24, 2023
    Assignee: Kioxia Corporation
    Inventor: Kenichi Murooka
  • Patent number: 11790980
    Abstract: Methods, systems, and devices for driver sharing between banks or portions of banks of memory devices are described. An apparatus may include a first bank and a second bank of memory cells and a word line driver configured to activate word lines. The word line driver may include a master word line driver and an address driver. In some examples, the master word line driver may be configured to generate a first signal to a first portion of the first bank or a second portion of the first bank as part of performing an access operation. In some examples, the master word line driver may be configured to generate a first signal for the first bank or the second bank as part of performing an access operation. The address driver configured to generate a second signal to a portion of the first bank or the second bank.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, George B. Raad
  • Patent number: 11790972
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 17, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11769543
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: September 26, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11763868
    Abstract: A sub-wordline driver for a semiconductor memory device includes a plurality of first active regions spaced apart from each other by a predetermined distance in each of a first direction and a second direction within a first region and a main wordline formed to traverse the plurality of first active regions by extending in the first direction. The main wordline includes a first line formed to extend in the first direction, a second line formed to extend in the first direction, and configured to be spaced apart from the first line by a predetermined distance in the second direction, and a connection line configured to interconnect the first line and the second line in the second direction at an end portion of the first region.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: September 19, 2023
    Assignee: SK HYNIX INC.
    Inventor: Jae Hong Jeong
  • Patent number: 11749318
    Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
  • Patent number: 11742024
    Abstract: A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Cheng-Hsiung Kuo, Chung-Chieh Chen
  • Patent number: 11741389
    Abstract: The method for obfuscating hardware partially imitates the neural network perceptron, obfuscating the hardware design. This method obfuscates the design functionality and immunes integrated circuits against Trojan insertion. This method can also be used to check for the existence of faults inside chips. This method resolves the concern related to security and reliability when outsourcing the manufacture of integrated circuits.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: August 29, 2023
    Assignee: University of Louisiana at Lafayette
    Inventors: Siroos Madani, Mohammad R. Madani, Magdy Bayoumi
  • Patent number: 11720286
    Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: August 8, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Patent number: 11721380
    Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ali Taghvaei, Atul Katoch
  • Patent number: 11690221
    Abstract: A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 27, 2023
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Chiang Ong, Tsung-Ta Hsieh, Chih-Yang Huang
  • Patent number: 11676669
    Abstract: An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a first circuit to generate a temperature-dependent voltage (TDV) that is dependent on an operating temperature of the integrated circuit, and a second circuit to generate a plurality of temperature reference voltages, based on or more codes. One or more comparator circuits compare individual ones of the plurality of reference voltages with the TDV, to generate one or more comparison signals that are indicative of the operating temperature of the integrated circuit.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 13, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Yih-Shan Yang
  • Patent number: 11676663
    Abstract: A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: June 13, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Zhi Chao Du, Yu Wang, Haibo Li, Ke Jiang, Ye Tian
  • Patent number: 11670377
    Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Won Yun, Kyung Min Kang, Dong Ku Kang
  • Patent number: 11670375
    Abstract: A memory device provides a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hua Tan, Jingxun Eric Wu, Yingying Zhu, Hui Yang, Bo Zhou
  • Patent number: 11663137
    Abstract: An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Perry V. Lea
  • Patent number: 11621035
    Abstract: Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 4, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vivek Raj, Vinayak Rajendra Ganji, Shivraj Gurpadappa Dharne
  • Patent number: 11621030
    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: April 4, 2023
    Assignee: Rambus Inc.
    Inventors: Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
  • Patent number: 11620358
    Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Chetan Chauhan, Rajesh Sundaram, Richard Coulson, Bruce Querbach, Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan
  • Patent number: 11615849
    Abstract: A method for programming a memory device including a first plane and a second plane is provided. The method includes simultaneously initiating programming of the first plane and the second plane, and in response to the first plane being successfully programmed and the second plane not being successfully programmed, suspending the programming of the first plane, and keeping the programming of the second plane.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 28, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Haibo Li, Chao Zhang
  • Patent number: 11610626
    Abstract: An arithmetic device includes a first memory cell, a first bit line, a first transistor, a second memory cell, a second bit line, a second transistor, a third bit line, a first switching circuit, a second switching circuit and a controller. The controller sets a conduction state between the first memory cell and the first bit line by the first transistor, and sets a conduction state between the second memory cell and the second bit line by the second transistor. The controller sets the first switching circuit and the second switching circuit in a coupled state and sets the conduction state between the first bit line and the third bit line and between the second bit line and the third bit line to transition voltages of the first, second and third bit lines to a first voltage.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Fumihiko Tachibana
  • Patent number: 11593201
    Abstract: Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seth Eichmeyer, James Rehmeyer, Benjamin Johnson, Jason Johnson
  • Patent number: 11595044
    Abstract: An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 28, 2023
    Assignee: SOCIONEXT INC.
    Inventor: Osamu Uno
  • Patent number: 11587632
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of fuse elements, a reference resistor unit, a first conductive terminal, a first switching circuit, and a second switching circuit. Each of the plurality of fuse elements has a first terminal and a second terminal. The reference resistor unit is configured to receive a first power signal and electrically couple with the first terminal of each of the plurality of fuse elements. The first conductive terminal is configured to receive a second power signal and is electrically connected to the second terminal of each of the plurality of fuse elements.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11574663
    Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: February 7, 2023
    Assignee: Kioxia Corporation
    Inventors: Keisuke Nakatsuka, Tomoya Sanuki, Takashi Maeda, Go Shikata, Hideaki Aochi
  • Patent number: 11562778
    Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 24, 2023
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Frederick A. Ware, William N. Ng
  • Patent number: 11538540
    Abstract: The present disclosure provides an information tamper-resistant system and method. The system includes: a storage module; a writing module connected with the storage module through a first OTP switch, to write source information to the storage module; a first reading module connected with the storage module through a second OTP switch, to read out written information in the storage module and disconnect the first OTP switch and the second OTP switch after confirming that the written information is accurate; and a second reading module connected with the storage module through a third OTP switch, to read out information stored in the storage module after the third OTP switch is switched on; the first OTP switch, the second OTP switch, and the third OTP switch can only perform one switch-on operation or one switch-off operation. The system and method effectively avoid theft and tampering of information.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: December 27, 2022
    Assignee: Montage Technology (Kunshan) Co., Ltd.
    Inventors: Xiong Zhang, Gang Shi
  • Patent number: 11522014
    Abstract: Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a first vertical level to interconnect structures formed at a second vertical level different from the first vertical level. The conductive lines include a plurality of contacted lines that are vertically connected to the interconnect structures at the socket interconnect region, a plurality of terminating lines terminating at the socket interconnect region, and a plurality of pass-through lines that pass through the socket interconnect region without being vertically connected and without being terminated at the socket interconnect region.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hernan A. Castro
  • Patent number: 11514979
    Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 29, 2022
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, Jr.
  • Patent number: 11500791
    Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chulbum Kim, Mark A. Helm, Yoav Weinberg
  • Patent number: 11501822
    Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: November 15, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jianquan Jia, Ying Cui, Kaikai You
  • Patent number: 11495499
    Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 8, 2022
    Assignee: Arm Limited
    Inventors: Amit Chhabra, David Victor Pietromonaco
  • Patent number: 11482270
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 25, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11474739
    Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N?2)th batch of program data, N being an integer equal to or greater than 2, program an (N?1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 18, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Chun Yuan Hou
  • Patent number: 11466685
    Abstract: Disclosed herein is an apparatus that includes a first buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Mieko Kojima