Chip Capacitor Precursors
A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.
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This application is a Divisional of and claims priority to U.S. patent application Ser. No. 12/132,316 filed on Jun. 3, 2008. Said application incorporated herein by reference for all purposes.
FIELDEmbodiments of the invention are related to integrated circuits (ICs), and particularly to chip capacitors and packaged semiconductors having one or more chip capacitors therein.
BACKGROUNDPackaged semiconductors can be embodied as single die packages or multi-chip packages. On example of single chip packages is a chip scale package (CSP).
Multichip packages include multichip modules (MCM) and System-in-a-Package or System in Package (SIP). As commonly used and defined herein, a plurality of die mounted on the same plane (e.g. the cavity substrate) is referred to as a MCM, whereas vertically stacked die stacking is referred to as a SIP.
The MCM or SIP performs all or most of the functions of an electronic system, such as the functions required by a cellular phone or music player. An exemplary SIP generally comprises several chips, such as a specialized processor, dynamic random access memory (DRAM), flash memory, and passive components, such as resistors, capacitors and in some case inductors, all mounted on the same substrate (e.g. a multi-layer printed circuit board (PCB)). This means that a complete functional unit can be built in a single multi-chip package, so that few external components are needed for system operation.
In certain applications, packaged semiconductors need high value capacitors, such as for power supply decoupling to minimize switching noise in certain electronic systems. To realize such high value capacitors, conventionally, an embedded capacitor is used. Conventional embedded capacitors are realized using a stack up structure comprising a plurality of stacked metal layers having dielectric layers therebetween and via connections between the metal layers formed on a conventional multi-layer PCB substrate, such as FR4 or BT.
SUMMARYThis Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Conventional embedded stack up structure capacitors require an interconnect be formed between the metal stack up layers for each capacitor plate, and thus require a plurality of interconnect steps. In addition, a step is needed to electrically connect the stack up capacitor(s) to an electrically conducting (e.g. copper) layer on the PCB substrate (e.g. FR4). Therefore, the process to form conventional stack up structure capacitors involves a large number of processing steps. Moreover, the dielectric between the metal layers is generally the dielectric substrate material (e.g. FR4) which is known to have a relatively low dielectric constant, thus requiring a wide metal area to achieve reasonable capacitance values.
Embodiments of the present invention substantially solve the problems of incorporating discrete capacitors in the packaged semiconductor device by dropping a pre-formed capacitor precursor, which as defined herein is a multilevel metal structure having dielectric between the respective electrically conductive (e.g. metal) layers, but lacks electrical connection between the electrically conductive layers, onto a PCB substrate surface during assembly. The substrate surface can be a top or bottom surface of a multi-layer PCB, or embedded within one of the layers the multi-layer PCB.
The dielectric layers can be high k dielectric layers which helps limit the necessary area to realize a desired capacitance value. Alternatively, the dielectric layers can have a relatively low k value, but can provide high dielectric strength. After dropping one or more pre-formed capacitor precursors according to embodiments of the invention onto or into the substrate, the metal layers of respective plates of the pre-formed capacitor precursor are electrically connected by standard printed circuit board manufacturing comprising forming vias (e.g. by drilling holes) and filing the vias with an electrically conductive material (e.g. copper). The filled vias also serve the purpose of electrically connecting the capacitor plates to electrically conductive contact regions on the substrate material, and can be drilled and filled along with other vias on the PCB.
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the instant invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One having ordinary skill in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
As defined herein, a chip capacitor is a multilayer monolithic capacitor constructed in chip form, with metallized terminations for each plate of the capacitor to facilitate direct bonding on hybrid integrated circuits, such as those built on PCB substrates. As described above, one or more preformed chip capacitor precursors are first fabricated. Precursors become completed capacitors during assembly by placing/dropping the capacitive precursor on a PCB substrate surface or on a internal layer of a multi-layer PCB laminate substrate using conventional assembly processing including drilling vias and filling the vias with an electrically conductive material (e.g. copper). To avoid confusion, as used herein, the process to form the capacitive precursor is referred to as fabrication, while the processing to convert the capacitor precursor to the chip capacitor after dropping onto the board substrate is referred to herein as part of assembly processing.
In one embodiment of the invention, the substrate for the precursor capacitor can be a PCB substrate, such as FR4 or BT, or a ceramic substrate, wherein one or more preformed chip capacitor precursors are generally preformed using a fabrication process comprising conventional PCB manufacturing techniques. The capacitor precursor fabricated becomes a chip capacitor during assembly by dropping the precursor into or onto a board and electrically connecting the electrically conducting (e.g. metal) layers together associated with each of the respective capacitor plates. In one embodiment, the capacitor precursor becomes a chip capacitor in the assembly process using standard PCB manufacturing comprising forming vias (e.g. by drilling holes in the capacitor precursor) and filing the vias with an electrically conductive material (e.g. copper). The filled vias can also serve the purpose of electrically connecting the capacitor plates to electrically conductive contact regions on the board substrate, and in one embodiment are be drilled and filled along with other vias on the substrate.
In another embodiment of the invention, the substrate for the capacitive precursor to be fabricated can be an integrated circuit substrate (e.g. silicon wafer). In this embodiment, a plurality of chip capacitor precursors are generally simultaneously fabricated using conventional integrated circuit fabrication techniques (e.g. metal and dielectric deposition, and etching). The chip precursor fabrication process can optionally include the formation of through substrate vias (TSVs). As with the PCB substrate fabrication embodiment for the chip capacitor precursor, the fabricated integrated circuit substrate-based capacitor precursor is dropped into (in the case of embedded) or onto a board substrate surface and has its metal layers associated with respective plates of the capacitor electrically coupled by filing the vias with an electrically conductive material (e.g. copper). The filled vias can also serve the purpose of electrically connecting the capacitor plates to electrically conductive contact regions on the board substrate, and can be filled along with other vias on the board substrate.
As described below, during assembly, further processing is performed on capacitive precursor 100, including at least via filling. After dropping the capacitive precursor 100 on a surface of or to be embedded within a layer of a multilayer PCB (e.g. FR4), a first via is formed in area 119 and a second via is formed in area 120, wherein the vias are generally filled in assembly with a metal comprising material (e.g. plated with copper) to complete the chip capacitor. In the completed chip capacitor, filled vias formed in areas 119 and 120 are used to electrically connect together layers 112, 114, 116, and 118 and 111, 113, 115 and 117, which serves as a first capacitor plate and a second capacitor plate, respectively.
As noted above, in one embodiment, substrate 105 can be a multi-layer PCB substrate, such as polymer-based FR4 or BT, or a ceramic-based substrate. In this embodiment, the chip capacitor precursor 100 is generally fabricated using a stack up structure having a dielectric adhesive material placed between the respective PCB layers, using conventional PCB manufacturing techniques (e.g. drilling, filling). In another embodiment, substrate 105 is a conventional integrated circuit substrate (e.g. silicon wafer), wherein the chip capacitor or chip capacitors is/are generally fabricated using conventional integrated circuit fabrication techniques (e.g. deposition of dielectric and metal and etching (e.g. plasma etching or RIE).
The dielectric layers 101-107 can comprise a variety of dielectric materials. In certain embodiments, such as for certain embodiments of the laminate embodiment for the capacitive precursor, the dielectric material is that of the PCB board, such as FR4 or BT (k of about 4.2 to 4.8). In another embodiment, the dielectric layer comprises a material having a k≧50, such as BNZ (Bi—Nb—Zn) which provides a k value of about 170-220. In yet another embodiment, the dielectric material is a high dielectric strength material, particularly for high voltage applications.
In one embodiment, the electrically conductive material (e.g. metal) patterns, and the locations of electrically conductive material free areas 119 and 120 and optionally electrically conductive material free area 123 can be designed to match an intended metal interconnect pattern on the board substrate the capacitive precursor will be dropped onto. As described below relative to
The fabricated capacitive precursor can be diced into structures comprising single capacitor precursors, diced into structures comprising a plurality of capacitive precursors, or a combination of single capacitor precursors and a plurality of capacitive precursors.
An exemplary method of assembling a packaged semiconductor according to an embodiment of the invention having one or more chip capacitors in a top or bottom surface of a PCB substrate is now described. The packaged semiconductor comprises a PCB substrate, at least one integrated circuit on the PCB substrate, and at least one chip capacitor die having first and second capacitor plates coupled to the integrated circuit on the PCB substrate. The first substrate can be multi-layer PCB and have electrically conductive contact regions thereon, generally on its top and bottom surface. The method comprises dropping at least one pre-formed capacitor precursor die according to an embodiment of the invention and the integrated circuit die on the same or opposite sides of the PCB substrate. If the pre-formed capacitor precursor die lacks at least a first pair of vias for providing an electrical contact between capacitor plates of the chip capacitor, following dropping, at least a first pair of vias are formed in the pre-formed capacitor precursor die. The first pair of vias are then filled with an electrically conductive material (e.g. plated with copper) to form the chip capacitor, wherein the filling of the vias provides both an electrical contact between the capacitor plates of the chip capacitor and the electrically conductive contact regions on the top and generally also the bottom surface of the PCB substrate.
In one embodiment, alignment for the drill process to form the vias can be an automated “blind” process. The blind alignment process is generally needed in the case of embedded capacitors according to embodiments of the invention. Positioning data for the particular packaged semiconductor device including lateral and optionally vertical coordinates relative to some reference on the PCB (a particular corner of the board or a bushing in the board) for mechanical alignment to the via landing locations for the respective capacitive precursors is stored. Drilling can proceed to drill the via landing locations based on the stored positioning data. Drilling can be guided to the proper depth based on vertical position coordinates.
In another embodiment of the invention, the drill process to form the vias can be a “sighted” process based at least in part on observable surface features. The sighted process is generally possible when chip capacitor precursors according to embodiments of the invention are dropped on the top or bottom of the board. As with the blind process described above, drilling can be guided to the proper depth based on stored vertical position coordinates.
Depending on application, capacitive precursors according to embodiments of the invention can be standardized designs or custom designed. In the case of custom designs, given a desired capacitance value, area available, and placement on or embedded in a board, custom capacitor precursors can be designed to provide the desired capacitance value.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
The Abstract of the Disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the following claims.
Claims
1. A capacitive precursor, comprising: a plurality of dielectric layers including respective ones of said plurality of dielectric layers between neighboring ones of said plurality of electrically conductive material layers,
- a substrate;
- a plurality of electrically conductive material layers stacked on said substrate, said plurality of electrically conductive material layers comprising first and second patterns, wherein said first patterns each comprise at least a first pair of overlaying areas free of said electrically conductive material, and said second patterns each comprise at least a second pair of overlaying areas free of said electrically conductive material, wherein said first pair of areas overlay areas of said second pattern having said electrically conductive material and said second pair of areas overlay areas of said first pattern having said electrically conductive material, and
- wherein said plurality of electrically conductive material layers are electrically isolated from one another by said dielectric layers.
2. The capacitive precursor of claim 1, wherein said substrate comprises a polymer or a ceramic printed circuit board (PCB).
3. The capacitive precursor of claim 1, wherein said substrate comprises silicon.
4. The capacitive precursor of claim 1, wherein said electrically conductive material comprises at least one metal.
5. The capacitive precursor of claim 1, wherein at least one of said plurality of dielectric layers comprise a material having a k≧50.
6. The capacitive precursor of claim 1, wherein said first pair of areas and second pair of areas are between 0.05 mm to 0.5 mm.
7. The capacitive precursor of claim 1, wherein said first and second patterns both further comprise at least one common overlaying area that is free of said electrically conductive material.
8. The capacitive precursor of claim 1, comprising a plurality of said capacitive precursors on said substrate.
9. The capacitive precursor of claim 8, wherein said first and second patterns both further comprise at least one common overlaying area that is free of said electrically conductive.
10.-31. (canceled)
Type: Application
Filed: Nov 28, 2011
Publication Date: Apr 5, 2012
Applicant: TEXAS INSTRUMENTS INCORPORATED (Dallas, TX)
Inventor: Azuma Chikara (Ibaraki)
Application Number: 13/305,181