AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE
A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.
This application hereby claims priority to and incorporates by reference U.S. Provisional Application No. 61/438,861, filed Feb. 2, 2011 and entitled “AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE.”
TECHNICAL FIELDThe present invention relates generally to the field of electronic communications and more particularly to signaling between integrated circuit devices.
BACKGROUNDIn an integrated circuit (IC) device having an adjustable-width signaling interface, a selectable number of input/output (I/O) pins may be used to convey information-bearing signals, thus enabling an IC to be configured according to system requirements. In the context of a memory system, for example, a single memory IC having an adjustable width data interface that ranges from N I/O pins to N/M (N divided by M) I/O pins can be used to support the various pin widths demanded by different industry sectors, and can also be used to support capacity expansion techniques in which the number of signaling links allocated to a given memory IC is diluted (or reduced) as the memory IC population is increased.
Unfortunately, width adjustability has been limited to relatively low max/min width ratios (i.e., ratio of N to N/M, and thus low values of M) due to practical constraints involved with laterally transferring the data along the interface between internal registers and the I/O pins. More specifically, each halving of the interface width typically requires a lateral transfer bandwidth equal to the link bandwidth itself—a transfer bandwidth that begins to consume an impractically large volume of interconnect resources as the max/min width ratio grows larger than two. Moreover, signal propagation delay associated with the transfer tends to increase with the square of the physical transfer distance which itself is typically proportional to the max/min width ratio.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Integrated circuit devices having area-efficient, width-adjustable signaling interfaces formed by segmented lateral transfer paths are disclosed in various embodiments. In one embodiment, for example, a lateral-transfer path is formed by daisy-chained segments that include logic to select an input signal from either a downstream path segment or a local I/O node and transfer the selected input signal to both an upstream path segment and to a local destination register. By this arrangement, different subsets of the daisy-chained segments may be applied to effect lateral data transfer in different width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure. In other embodiments, I/O nodes physically centered between data destinations (and sources) are selected to be the active I/O nodes in below-maximum width configurations thus halving (approximately) the lateral transfer distance and propagation time from I/O node to data destination. In yet other embodiments, the data incoming/outgoing via a given I/O node is split into upper and lower portions, with the upper data portion being laterally transferred to/from logic-side data registers above the I/O node and the lower data portion being laterally transferred to/from logic-side data registers below the I/O node. Because only half the total incoming data volume is laterally transferred in either direction, the net lateral transfer bandwidth (and thus the number of interconnects and area consumed thereby) is halved relative to the transfer bandwidth otherwise required. These and other embodiments are disclosed in further detail below.
In the continuous-path approach, shown at 101, the implementation area required by the conductors of the lateral-transfer structure (shaded) is dependent on the range of I/O widths supported by the signaling interface, Nmax to Nmin. That is, each halving of the interface width (i.e., from Nmax to Nmax/2, from Nmax/2 to Nmax/4, etc.) necessitates an additional lateral transfer path having bandwidth BWLink (i.e., as shown by paths marked “x4”, “x2” and “x1”), and thus an additional number ‘n’ of lateral-transfer conductors corresponding to the serialization/deserialization ratio within the link transceivers (DQ) of the physical signaling interface (PHY). Assuming a serialization/deserialization ratio of 16, for example, the physical width of lateral transfer structure 101 grows by 16 conductors for each halving of the logical interface width (i.e., physical width of the lateral transfer structure is proportional to Log2(Nmax/Nmin)*BWLink) a growth that rapidly exceeds the available implementation area and thus constrains the supportable logical interface widths to a relatively small range.
By contrast, the implementation area required by segmented lateral transfer structure 111 is independent of the range of supported interface widths and instead defined by the conductor count needed to support the bandwidth of a single link. In effect, by decomposing the lateral transfer structure into daisy-chained segments that can be switchably coupled to one another to form composite transfer paths of different lengths, and by limiting the PHY-side connection to a given composite transfer path to a solitary I/O node (i.e., the active I/O node used to source data to the core-side registers coupled to the composite transfer path), the full range of logical interface width selections, from the native or maximum width of the interface, Nmax, to a single I/O node (Nmin=1) may be achieved. Moreover, as discussed in further detail below, the individual segments may include buffer amplifiers that limit the tRC delay of laterally transferred signals, thus avoiding RC-dependent flight time delays that plague conventional implementations.
Still referring to
Each lateral transfer segment 121 (e.g., 121a, 121b, 121c) within segmented lateral transfer structure 111 is referred to herein as a “transfer cell” and is coupled to a local I/O node within PHY 110 (e.g., a pin or other link-interconnect 117 and data transceiver 119), and to a local core register 120, as well as to sets of one or more conductors 126u, 126d that form respective segments of a segmented lateral transfer path. Referring specifically to transfer cell 121b, a pair of switching elements 123, 124 are provided to switchably couple either the local I/O node or input transfer path segment 126d to output transfer path segment 126u and to local core register 120 (collectively, the “cell output”), thus enabling either the local I/O node or the downstream transfer cell to source data to the cell output. Moreover, input transfer path segment 126d constitutes the output transfer path segment of downstream transfer cell 121a, and output transfer path segment 126u constitutes the input transfer path segment to upstream cell 121c, thus establishing a daisy-chain (input-to-output-to-input-to-output, . . . ) of transfer path segments that can be driven by any of the data I/O nodes within the interface. More specifically, the “I/O” switching elements 123 within the chain of transfer cells may be configured to establish a single I/O node source (the active I/O node) within a cluster of I/O nodes, and the “transfer” switching elements 125 may be configured to establish one or more composite transfer paths, each switchably isolated (i.e., decoupled) from one another to conduct input data from the active I/O node to the subset of the core registers corresponding to the I/O node cluster.
Comparing the different interface-width configurations shown in
Returning to
Different embodiments of two-state transfer cells that may be used to implement transfer cells 121 are shown at 130 and 140. In transfer cell 130, pass gates 133 and 135 (i.e., parallel N-type and P-type transistor elements coupled in parallel) are used to implement I/O and transfer switching elements 123 and 125, respectively. Complementary instances of select signal, ‘S,’ (generated in part by inverter 137) are supplied to control (gate) terminals of pass gates 133, 135 such that one of the pass gates is closed when the other is open and vice-versa, thus establishing a two-input multiplexer 131. In alternative embodiments, the I/O and transfer switching elements 123, 125 may be implemented by various circuit elements other than the pass-gates shown, including Boolean logic implementations in which the multiplexer select signal, S, I/O data input (WI) and transfer data input (YI) are logically multiplexed to yield output signal YO/WO.
While transfer cell 130 may suffice for relatively small interface widths, signal attenuation and tRC delay tend to increase rapidly as the cell count grows. To overcome these difficulties, transfer cell 140 includes, in addition to elements 133, 135, 137, a transfer buffer 145 (e.g., implemented by back-to-back inverter stages and optionally forming part of multiplexer 141) to drive the transfer output, YO, and an isolation buffer 147 to isolate the transfer output from the local output, WO (i.e., output coupled to the local core register), thereby providing a signal repeater at each transfer stage that may substantially lower the overall propagation time of a laterally transferred signal from the source I/O node to the most remote destination register. That is, in contrast to a continuous path approach in which the propagation delay grows in proportion to the square of the transfer path length (i.e., due to linearly increasing resistance and linearly increasing capacitance, and thus quadratically increasing tRC), cell-by-cell buffering of transfer path segments limits the tRC delay along any given transfer path segment to yield a potentially lower net propagation delay along the segmented lateral transfer path than may be achieved using a continuous path approach.
Still referring to
Focusing on the write data path, the sixteen write data values, Wdata[i][15:0] (where ranges from 15 to 0 in the example shown), are delivered to respective write-data transfer blocks, “W16,” that, together with counterpart read-data transfer blocks, “R16,” constitute the lateral transfer circuitry within the signaling interface. In one embodiment, shown in detail view 177, each W16 block may be viewed as an array of interconnect cells, that include bit-transfer cells, W1 (179), and bit-routing cells, W0 (181). In the particular example shown, transfer cells 179 are disposed in a diagonal within the interconnect cell array (i.e., at array positions [i, i], where T ranges from 0 to 15, and where array position [0,0] is situated at the bottom left corner of the array) so that the input and output signals for each transfer cell 179 may be conveyed exclusively through routing cells 181 as they extend to/from edges of the W16 block. As shown, each W1 cell includes a multiplexer 185 (which may internally include a buffer amplifier as shown at 141 in
In the x8 interface (
In the x4 interface of
Reflecting on the different interface configurations shown in
While the propagation time reduction is most notable in the narrowest width configuration (i.e., where the lateral transfer path or paths are longest), the transfer propagation time is also reduced in other logical width configurations. For example, in the x2 width configuration, I/O nodes [2] and [6] are selected as the centered I/O's within respective single-source clusters of four I/O nodes, thus reducing the lateral transfer distance relative to the unidirectional lateral transfer arrangement. In the x4 example, in which the single-source I/O cluster size is two, the lateral transfer distance is unidirectional regardless of the I/O node selected (i.e., there is only one lateral transfer destination) and in the native width, there is no lateral transfer at all.
The embodiment at 317 may be employed in applications where buffer amplifiers or other generally unidirectional circuit elements are desirable. As shown, the lateral transfer path is split into isolated upper and lower segments, Yu and Yd, each of which is either (i) undriven, (ii) driven according to the state of local input (WI), or (iii) driven according to the state of a signal present on alternate transfer path segment (i.e., Yu driving Yd or vice-versa). More specifically, upper- and lower-segment drivers 320, 322 may be selectively enabled by enable signals Eu and Ed, respectively, to drive or refrain from driving a signal onto the upper and lower path segments, and upper- and lower-segment multiplexers 319 and 321 are controlled by respective select signals Su and Sd, to select either the local input, WI, or the alternate transfer path segment as the signal source for an enabled segment driver (note that select signals Su and Sd will not necessarily have the same logic values within cell 317 as within cell 307 for a given width configuration). By this arrangement, bidirectional transfer cell 317 can be put into at least the following states, each of which is employed in one or more of the interface configurations shown in
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- Direct Output (Eu=1, Su=1, Ed=0, Sd=x, where ‘x’ indicates “don't care”): local input selected by upper segment multiplexer and driven onto upper path segment, while lower path segment is undriven;
- Bidirectional Output (Eu=1, Su=1, Ed=1, Sd=1): local input selected by upper- and lower-segment multiplexers and driven onto both the upper and lower path segments;
- Transfer-Up (Eu=1, Su=0, Ed=0, Sd=x, where ‘x’ indicates don't care): signal present on lower path segment driven onto upper path segment, thus effecting an upward lateral transfer;
- Transfer-Down (Ed=1, Sd=0, Eu=0, Su=x): signal present on upper path segment driven onto lower path segment, thus effecting a downward lateral transfer; and
- Isolation: upper and lower transfer path segments undriven (Eu=0, Ed=0, Su=x, Sd=x).
Referring to the bilateral-transfer interface configurations shown in
In the x4 configuration, each of the bidirectional transfer cells corresponding to an active I/O node is set to the bilateral output state to drive both upper and lower transfer path segments according to the state of the local input, thus delivering the input data to the local output (WO) and to the local output of the immediately downstream transfer cell. By contrast, each of the bidirectional transfer cells corresponding to inactive I/O nodes (i.e., the cells immediately downstream from respective “active-node transfer cells”) are set to the isolation state, thus avoiding contention with adjacent cells or, viewed, alternatively, isolating each dual-I/O cluster (i.e., single-source I/O cluster having one active I/O node and one inactive I/O node) from the others.
In the x2 interface configuration, each of the bidirectional transfer cells corresponding to an active I/O node is again placed in a bidirectional output state, while, while the transfer cells immediately above and below a given bidirectional-output transfer cell are set to transfer-up and transfer-down states, respectively, and the bottom transfer cell in each quad-I/O cluster (i.e., cluster formed by I/O nodes 0-3 or cluster formed by I/O nodes 4-7) is set to an isolation state.
Similarly, in the x1 interface configuration, the bidirectional transfer cell corresponding to the sole active I/O node (i.e., central I/O node 4 in this example, although node 3 may alternatively be used) is set to the bilateral output state, while all transfer cells above are set to the transfer-up state and all transfer cells below are set to the transfer-down state (except optionally the transfer cell corresponding to the bottom-edge I/O node, which may be set to the isolation state), thereby enabling data to be conveyed between the I/O node centered within the interface and the core registers above and below.
Still referring to
Transfer cell 375 enables the same functional path connections as transfer cell 365, but includes buffer amplifiers 382, 385 and other generally unidirectional circuit elements to mitigate, for example, transfer-distance-dependent tRC. For example, upper and lower segment multiplexers 377, 379 and upper and lower segment drivers 378 and 380 (e.g., tri-state drivers) enable the data-source select operations and switched through-connection provided by switching elements 367, 369 and 371 within transfer cell 365, and output multiplexer 381 corresponds to switching elements 372 and 373. Further, the segment multiplexers 377, 379 and segment drivers 378, 380 correspond to the segment multiplexers 319, 321 and segment drivers 320, 322 shown in transfer cell 317 of
Each of the transfer cell embodiments 365, 375 shown in
-
- Direct Output (Eu=1, Su=1, Ed=0, Sd=x, Sc=0): upper portion of local input selected by upper segment multiplexer and driven onto upper transfer path segment (and thus to upper local core register), lower portion of local input forwarded to lower core register via output multiplexer, and lower transfer path segment undriven;
- Bidirectional Output (Eu=1, Su=1, Ed=1, Sd=1, Sc=1): upper and lower portions of local input selected by upper- and lower-segment multiplexers and driven onto both the upper and lower path segments, respectively;
- Transfer-Up (Eu=1, Su=0, Ed=0, Sd=x, Sc=1): signal present on lower path segment driven onto upper path segment, thus effecting an upward lateral transfer;
- Transfer-Down (Ed=1, Sd=0, Eu=0, Su=x, Sc=1): signal present on upper path segment driven onto lower path segment, thus effecting a downward lateral transfer; and
- Isolation: upper and lower transfer path segments undriven, and upper path segment coupled in common to upper and lower data outputs (Eu=0, Ed=0, Su=x, Sd=x, Sc=1).
In the x8 configuration, each W8 transfer block corresponding to an active I/O node is set to the bilateral output state to drive both upper and lower transfer path segments according to the state of the local input, thus delivering the upper portion of the local input data in common to the upper and lower local core registers, and laterally transferring the lower portion of the local input data to the downstream (i.e., lower and adjacent) W8 block for delivery to the upper and lower core registers for that transfer block. By contrast, each of the W8 transfer blocks corresponding to inactive I/O nodes (i.e., the W8 blocks immediately downstream from respective “active-node transfer blocks”) are set to the isolation state, thus avoiding contention with adjacent W8 blocks or, viewed, alternatively, isolating each of eight dual-I/O clusters (i.e., single-source I/O cluster having one active I/O node and one inactive I/O node) from the others.
In the x4 interface configuration, each of the W8 transfer blocks corresponding to an active I/O node is again placed in a bidirectional output state, while the W8 transfer blocks immediately above and below are set to transfer-up and transfer-down states, respectively, and the bottom W8 transfer block in each quad-I/O cluster (i.e., cluster formed by I/O nodes 0-3, 4-7, 8-11, or 12-15) is set to an isolation state.
Similarly, in the x2 interface configuration, each of the W8 transfer blocks corresponding to an active I/O node is placed in a bidirectional output state, while the three W8 transfer blocks immediately above and below are set to transfer-up and transfer-down states, respectively, and the bottom W8 transfer block in each eight-I/O cluster (i.e., cluster formed by I/O nodes 0-7 or 8-15) is set to an isolation state.
Lastly, in the x1 interface configuration, the W8 transfer block corresponding to the sole active I/O node (i.e., central I/O node 8 in this example, although node 7 may alternatively be used) is set to the bilateral output state, while all transfer cells above are set to the transfer-up state and all transfer cells below are set to the transfer-down state (except optionally the transfer cell corresponding to the bottom-edge I/O node, which may be set to an isolation state), thereby enabling respective upper and lower portions of the input data to be conveyed between the I/O node centered within the interface and the core registers above and below.
In contrast to the write-data transfer cells (e.g., described in reference to
-
- Direct Output (Eu=1, Su=1, Ed=0, Sd=x, Sc=0): upper data from local core register delivered to upper data output (Rou) via output multiplexer (471), multiplexed data input (Riud) from local core register (i.e., signal output via core-register multiplexer 479) selected by lower segment multiplexer and driven onto lower transfer path segment for delivery to lower data output (Rod), and upper transfer path segment undriven;
- Semi-Drive (Upper): (Eu=1, Su=1, Ed=0, Sd=x, Sc=1): multiplexed data input (Riud) driven onto upper transfer path segment for delivery to either local upper output (via output multiplexer) or lower output of upstream transfer cell, while lower transfer path segment undriven;
- Semi-Drive (Lower): (Eu=0, Su=0, Ed=1, Sd=1, Sc=1): multiplexed data input (Riud) driven onto lower transfer path segment for delivery to upper output of downstream cell (i.e., via output multiplexer within that cell) while upper transfer path segment is undriven;
- Transfer-Up (Eu=1, Su=0, Ed=0, Sd=x, Sc=x): signal present on lower path segment driven onto upper path segment, thus effecting an upward lateral transfer;
- Transfer-Down (Ed=1, Sd=0, Eu=0, Su=x, Sc=x): signal present on upper path segment driven onto lower path segment, thus effecting a downward lateral transfer; and
- Isolation: upper and lower transfer path segments undriven, and upper path segment coupled in common to upper and lower data outputs (Eu=0, Ed=0, Su=x, Sd=x, Sc=1).
In the x8 configuration depicted in
In the x4 configuration (
In the x2 configuration (
In the x1 configuration (
In one embodiment, the command/address logic 513 within memory component 501 includes a programmable mode register 525 having an interface width field 527. The memory controller programs the mode register, for example, by issuing a register-write command and corresponding register value via the command/address path (although the register value may alternatively be issued via one or more data links). Memory component 501 responds to the register-write command by loading the register value into the mode register (which may include multiple registers), including loading an interface width setting into interface width field 527. The interface width setting is supplied to interface control circuitry within command/address logic 513 which responsively outputs static and/or dynamic transfer-state control signals 516 corresponding to the specified interface width (e.g., as described in reference to
In the embodiment shown, the interface width setting is a three-bit code having one of five values to establish the different logical widths shown (i.e., x16, x8, x4, x2, x1, though more or fewer width configurations may apply in alternative embodiments). In the memory component shown, the lateral transfer structure 511 implements a split-route, bilateral transfer operation and thus effects a centered I/O arrangement as discussed above. That is, as shown in the table at 528, the active I/O pins (or other interconnects) for each logical width narrower than the native width of the memory component (i.e., x8 and below in the example shown) are mutually exclusive. For example, none of the active I/O pins in any logical width configuration of x8 or narrower is used in any other logical width configuration of x8 or narrower. Thus, each register programming operation that sets a logical width narrower than the native width of the memory device enables data transfer via an exclusive subset of the I/O pins of memory component 501 (i.e., pins that are unused in any other logical width narrower than the native width of the memory device).
In the embodiment of
It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and VHDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, computer storage media in various forms (e.g., optical, magnetic or semiconductor storage media, whether independently distributed in that manner, or stored “in situ” in an operating system).
When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Additionally, links or other interconnection between integrated circuit devices or internal circuit elements or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses. Signals and signaling links, however shown or described, may be single-ended or differential. A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction (and thus controlling an operational aspect of the device and/or establishing a device configuration) or through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The terms “exemplary” and “embodiment” are used to express an example, not a preference or requirement.
While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims
1. A method of operation within a memory component, the method comprising:
- receiving write data exclusively via a first set of signaling-link receivers if a signaling interface of the memory component is set to a first logical width; and
- receiving write data exclusively via a second set of signaling-link receivers if the signaling interface of the memory component is set to a second logical width, wherein the second logical width exceeds the first logical width and the first set of signaling-link receivers includes at least one signaling-link receiver not included in the second set of signaling-link receivers.
2. The method of claim 1 wherein the second logical width is twice the first logical width and the second set of signaling-link receivers comprises twice as many signaling-link receivers as the first set of signaling-link receivers.
3. The method of claim 1 wherein the memory component comprises a first number of signaling-link receivers that includes the first and second sets of signaling-link receivers and that defines a maximum width of the signaling interface.
4. The method of claim 3 wherein the first number of signaling-link receivers comprises twice as many signaling-link receivers as the second set of signaling-link receivers.
5. The method of claim 1 further comprising receiving write data exclusively via a third set of signaling-link receivers if the signaling interface of the memory component is set to a third logical width, wherein the third logical width exceeds the second logical width, the second set of signaling-link receivers includes at least one signaling-link receiver not included in the third set of signaling-link receivers, and the first set of signaling-link receivers includes at least one signaling-link receiver not included in the third set of signaling-link receivers.
6. The method of claim 1 further comprising setting the signaling interface to one of a plurality of logical widths, including the first logical width and the second logical width, in response to a width configuration value received from a source external to the memory component.
7. The method of claim 6 wherein setting the signaling interface to one of a plurality of logical widths comprises switchably coupling a plurality of path segments in one of a plurality of possible configurations.
8. The method of claim 7 wherein, in a first configuration of the plurality of path segments, the plurality of path segments are switchably coupled between a first signaling-link receiver and a first plurality of data registers, and in a second configuration of the plurality of path segments, at least a portion of the plurality of path segments are switchably coupled between a second signaling-link receiver and the first plurality of data registers, the first signaling-link receiver being included within the first set of signaling-link receivers but not the second set of signaling-link receivers, and the second signaling-link receiver being included in the second set of signaling-link receivers but not the first set of signaling-link receivers.
9. The method of claim 8 wherein the at least a portion of the plurality of path segments includes a first path segment to convey a write data bit in a first direction when the plurality of path segments are in the second configuration and to convey a write data bit in a second direction, opposite the first direction, when the plurality of path segments are in the first configuration.
10. The method of claim 9 wherein the memory component comprises an integrated circuit die and wherein the plurality of signaling-link receivers are disposed adjacent an edge of the integrated circuit die, and wherein the first direction is parallel to the edge of the integrated circuit die.
11. The method of claim 1 further comprising:
- outputting read data exclusively via a first set of signaling-link output drivers if the signaling interface of the memory component is set to the first logical width; and
- outputting read data exclusively via a second set of signaling-link output drivers if the signaling interface of the memory component is set to the second logical width, wherein the first set of signaling-link output drivers includes at least one signaling-link output driver that is not included within the second set of signaling-link output drivers.
12. A memory component comprising:
- a first set of signaling-link receivers to receive write data if the memory component is set to a first logical width; and
- a second set of signaling-link receivers to receive write data if the memory component is set to a second logical width, wherein the second logical width exceeds the first logical width and at least one of the signaling-link receivers within the first set is not used to receive write data if the memory component is set to the second logical width.
13. The memory component of claim 12 wherein the second logical width is twice the first logical width and the second set of signaling-link receivers comprises twice as many signaling-link receivers as the first set of signaling-link receivers.
14. The memory component of claim 12 wherein the first set of signaling-link receivers and the second-set of signaling-link receivers constitute respective subsets of signaling-link receivers within a first number of signaling-link receivers that defines a maximum logical width setting of the memory component.
15. The memory component of claim 14 wherein the first number of signaling-link receivers comprises twice as many signaling-link receivers as the second set of signaling-link receivers.
16. The memory component of claim 12 further comprising a third set of signaling-link receivers to receive write data if the memory component is set to a third logical width, wherein the third logical width exceeds the second logical width, at least one signaling-link receiver within the first set of signaling-link receivers is not used to receive write data if the memory component is set to the third logical width, and at least one signaling-link receiver within the second set of signaling-link receivers is not used to receive write data if the memory component is set to the third logical width.
17. The memory component of claim 12 further comprising a programmable register to store a width value that sets the logical width of the memory component, and control circuitry to load the width value into the programmable register in response to a command from a source external to the memory component.
18. The memory component of claim 12 further comprising a plurality of path segments switchably coupled in a first configuration between the first set of signaling-link receivers and a plurality of data registers when the memory component is set to the first logical width.
19. The memory component of claim 18 wherein the plurality of path segments is switchably coupled in a second configuration between the second set of signaling-link receivers and the plurality of data registers if the memory component is set to the second logical width.
20. The memory component of claim 19 wherein the plurality of path segments is decoupled from at least one signaling-link receiver of the first set of signaling-link receivers if coupled in the second configuration and decoupled from at least one signaling-link receiver of the second set of signaling-link receivers if coupled in the first configuration.
21. The memory component of claim 19 wherein the plurality of path segments includes a first path segment to convey a write data bit in a first direction if the plurality of path segments are coupled in the second configuration and to convey a write data bit in a second direction, opposite the first direction, if the plurality of path segments are coupled in the first configuration.
22. The memory component of claim 21 wherein the plurality of path segments, the plurality of data registers and the first and second sets of signaling-link receivers are implemented in an integrated circuit die, the first and second sets of signaling-link receivers being disposed adjacent an edge of the integrated circuit die, and wherein the first direction is parallel to the edge of the integrated circuit die.
23. The memory component of claim 12 further comprising:
- a first set of signaling-link output drivers to output read data if the memory component is set to the first logical width; and
- a second set of signaling-link output drivers to output read data if the memory component is set to a second logical width, wherein at least one signaling-link output driver within the first set of signaling link output drivers is not used to output read data if the memory component is set to the second logical width.
24. An integrated circuit device comprising:
- a data interface to output write data to a memory component; and
- a command interface to output a logical width value to the memory component that establishes one of a plurality of logical widths within the memory component; and
- a data interface to output write data that is to be received via a first set of signal receivers within the memory component if the logical width value specifies a first logical width, and to output write data that is to be received via a second set of signal receivers within the memory component if the logical width value specifies a second logical width, wherein the second logical width exceeds the first logical width and at least one signal receiver within the first set of signal receivers is not used to receive write data if the logical width value specifies the second logical width.
25. The integrated circuit component of claim 24 wherein the second logical width is twice the first logical width.
26. The integrated circuit component of claim 25 wherein the second logical width is half a maximum logical width of the memory component.
27. A memory component comprising:
- means for receiving write data exclusively via a first set of signaling-link receivers if a signaling interface of the memory component is set to a first logical width; and
- means for receiving write data exclusively via a second set of signaling-link receivers if the signaling interface of the memory component is set to a second logical width, wherein the second logical width exceeds the first logical width and the first set includes at least one signaling-link receiver that is not included within the second set.
Type: Application
Filed: Dec 8, 2011
Publication Date: Aug 2, 2012
Inventor: Frederick A. Ware (Los Altos Hills, CA)
Application Number: 13/315,149