Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

Abstract: A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality. The method further includes comparing the uncorrected data with the data and metadata from the other storage devices, speculatively modifying the uncorrected data based, at least in part, on the other data to create a set of reconstructed first data codewords, and, in response to a determination that one of the reconstructed first data codewords has recovered the first data, issuing a write_raw command to rewrite the modified data and associated metadata to the first storage device.

Abstract: A data transferring apparatus and a method for transferring data with overlap are provided. The data transferring apparatus includes a command splitter circuit and a plurality of tile processing circuits. The command splitter circuit splits a block level transfer command into a plurality of tile transfer tasks. The command splitter circuit may issue the tile transfer tasks to the tile processing circuits in a plurality of batches. The tile processing circuits may execute the tile transfer tasks in a current batch, so as to read data of a plurality of corresponding tiles among a plurality of source tiles of a source block to the tile processing circuits. After all the tile transfer tasks in the current batch have been executed by the tile processing circuits, the command splitter circuit issues the tile transfer tasks in a next batch of the batches to the tile processing circuits.

Abstract: A display device capable of improving image quality is provided. A display device includes a plurality of pixel blocks in a display region. The pixel blocks each include a first circuit and a plurality of second circuits. The first circuit has a function of adding a plurality of pieces of data supplied from a source driver. The second circuit includes a display element and has a function of performing display in accordance with the added data. One pixel has a configuration including one second circuit and an component of the first circuit that is shared. When the first circuit is shared by a plurality of pixels, the aperture ratio can be increased.

Abstract: A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity and data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

Abstract: Providing concurrent access to a tape volume of a tape emulation unit includes a first process generating a first attachment request to attach to the tape emulation unit, generating a first unique id corresponding to the first attachment request, a second process generating a second attachment request, different from the first attachment request, to attach to the tape emulation unit, generating a second unique id corresponding to the second attachment request, and allowing the first process to access a tape volume on the tape emulation unit using the first unique id while the second process concurrently accesses the tape volume on the tape emulation unit using the second unique id. The first process may access the tape volume for writing data to the tape volume. Only one of the processes may access the tape volume for writing data to the tape volume.

Abstract: A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.

Abstract: A method of executing an early-Z draw call in a graphics processing pipeline may include detecting a late-Z draw call in the pipeline, determining a compatibility of a depth comparison function of the early-Z draw call with a depth comparison function of the late-Z draw call, and speculatively executing a fragment of the early-Z draw call with a shader. The method may further include determining that the fragment of the early-Z draw call passes the depth comparison function of the early-Z draw call, and updating a depth buffer with a depth value for the fragment of the early-Z draw call. The method may further include determining that the fragment of the early-Z draw call provides a correct result, and forwarding the speculative shader result for the fragment to a next stage of the pipeline.

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: A method and device for out-of-order cryptographic processing to eliminate or ameliorate data dependency stalls, in the cryptographic pipeline of a data storage device, resulting from the application of cipher text stealing. A cryptographic processing pipeline performs the steps of: a) cryptographically process a penultimate data block, to produce a penultimate processed data block, and store a portion of the penultimate processed data block in the memory store; b) cryptographically process at least one leading data block, to produce at least one processed leading data block; and c) cryptographically process a concatenation of a last data block and the portion of the penultimate processed data block, to produce a last processed data block, wherein the cryptographic processing pipeline starts to perform step b) before completing step a).

Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

Abstract: A method for streaming sensor data from a set of radio-frequency identification (RFID) tags includes determining an initial communication approach to be performed with respect to each RFID tag. The method also includes managing access to the RFID tag by refining the initial communication approach based on records of successes and failures of the initial communication approach. A radio-frequency identification (RFID) system is also disclosed, the system comprising one or more processors and a memory system comprising one or more non-transitory computer-readable media storing instructions that, when executed by at least one of the one or more processors, causes the system to perform operations for streaming sensor data from one or more RFID tags to one or more RFID readers.

Abstract: Disclosed herein are system, method, and computer program product embodiments for efficiently maintaining a distributed processing of data between a source and sink. An embodiment operates by maintaining a scheduler in communication with the source and the sink, wherein the source and the sink communicate over a network. The scheduler identifies an utilization of a resource unit of the source, the sink and/or the network meeting or exceeding a predetermined threshold. After identifying that the utilization of the resource unit of the source, the sink and/or the network meets or exceeds a predetermined threshold, the scheduler triggers an operator of the source and/or the sink. The operator modifies a processing of data by the at least one of the source and the sink.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

Abstract: A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of ALUs in a data path is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first selecting a first available instruction node from the dependency graph; first assigning the selected first available instruction node to the instruction word; second selecting any available dependent instruction nodes that are dependent upon a result of the selected first available instruction node and do not violate any predetermined rule; second assigning to the instruction word the selected any available dependent instruction nodes; and updating the dependency graph to remove any instruction nodes assigned during the first and second assigning from further consideration for assignment.

Abstract: An information processing apparatus connected to a device to which an IP address is not set is provided. The apparatus acquires device information that includes unique information of the device, decides a free port number and decide an address, which includes the decided port number, as an access destination for acquiring data from the device, shares the address with an access source, and notifies the unique information and the port number, wherein, when the access source accesses the shared address, the access is detected based on the port number and data is requested from the device corresponding to the unique information, and when the data is received from the device, the data is transmitted to the access source.

Abstract: Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates a command reference clock signal. Each of the access signal transmission circuits adjusts a phase and a duty cycle of one of access signals from a memory access controller according to the command reference clock signal to generate one of output access signal including an output external read enable signal to activate a memory device and an output internal read enable signal. The data reading circuit samples a data signal from the activated memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller. The multiplexer generates the sampling signal according to the output internal read enable signal under a SDR mode and generates the sampling signal according to a data strobe signal from the activated memory device under a DDR mode.

Abstract: The present disclosure provides a processor, a display driving circuit, and an electronic device. The processor includes: a memory being divided into a first part that stores correction data for correcting an image signal, a second part that stores data of an image signal to be displayed, and a third part that stores data of an application to be executed; and an output port configured to transmit the data of the image signal and the correction data stored in the memory to an external display driving circuit, separately.

Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

Abstract: A computer system comprises memory to store computer-executable instructions. The computer system may, as a result of execution of the instructions by one or more processors, cause the system to load a first subset of a set of data elements into a first cache, load a second subset of the set of data elements into a second cache, and as a result of elements of the first subset being processed, issue commands to place elements of the second subset into the first cache to enable processing the second subset to be processed from the first cache.

Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.

Abstract: A system including one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the one or more computers to implement a memory and memory-based neural network is described. The memory is configured to store a respective memory vector at each of a plurality of memory locations in the memory. The memory-based neural network is configured to: at each of a plurality of time steps: receive an input; determine an update to the memory, wherein determining the update comprising applying an attention mechanism over the memory vectors in the memory and the received input; update the memory using the determined update to the memory; and generate an output for the current time step using the updated memory.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

Abstract: Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

Abstract: Provided are techniques for synchronously performing commit records operations. A local copy of a commit records message is built for a Non-Volatile Storage (NVS) track, with a valid indicator set to indicate that this commit records message is valid and has not been processed yet. A Direct Memory Access (DMA) chain is executed to transfer customer data from a host to real segments and alternate segments of a track buffer and to transfer the local copy of the commit records message to a mail message structure of a mail message array. At DMA completion, an NVS manager is synchronously called to perform a commit records operation with the commit records message in the mail message structure. In response to the commit records operation completing, there is an indication that a new write DMA is allowed to proceed for the NVS track.

Abstract: Embodiments are generally directed to register bank conflict reduction for multi-threaded processor execution units. An embodiment of an apparatus includes a processor including one or more execution units (EUs), at least a first execution unit (EU) to process a plurality of threads, the first EU including a register file including multiple register banks with each register bank including multiple registers, and one or more read multiplexers to read registers from the register file, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict. Registers for each thread for the first EU are distributed across the registers banks within the register file such that a first register for a first thread of the plurality of threads and a following second register for the first thread are located in different register banks within the register file.

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract: A GPU comprises: a GPR comprising registers; an L1 cache coupled to the GPR and configured to implement a pixel mapping by: segregating pixels of an image into regions, the regions comprise a first region and a second region, the first region comprises first pixels, and the second region comprises second pixels, loading the first pixels into the GPR in a horizontal manner, and loading the second pixels into the GPR in a vertical manner; and an ALU configured to read the first pixels and the second pixels independently of a shared memory.

Abstract: An example method is provided to maintain state information of a virtual machine in a virtualized computing environment through a self-triggered approach. The method may comprise detecting, by a first host from a cluster in the virtualized computing environment, that the first host is disconnected from a network connecting the first host to a distributed storage system accessible by the cluster. The method may also comprise suspending, by the first host, a virtual machine supported by the first host and storing state information associated with the virtual machine. The method may further comprise selecting a second host from the cluster and migrating the suspended virtual machine to the second host such that the suspended virtual machine is able to resume from suspension on the second host based on the stored state information.

Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.

Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

Abstract: This application provides a drive circuit of a display device and a driving method for the display device. The display device includes a driver module and a display panel. The drive circuit includes: N single-ended to differential modules, connected to N signal output lines of the driver module and 2N scanning lines of the display panel and connected to a clock signal. Each single-ended to differential module is correspondingly connected to one signal output line and two scanning lines. The N single-ended to differential modules are configured to: output, to the 2N scanning lines according to the clock signal, scanning signals output by the N signal output lines, and charge the 2N scanning lines by using the N signal output lines, where N?1, and N is a positive integer.

Abstract: An example of a system includes a plurality of non-volatile memory dies, a memory bus coupled to the plurality of non-volatile memory dies, and one or more control circuits coupled to the plurality of non-volatile memory dies through the memory bus. The one or more control circuits include a plurality of die-specific request queues configured in a one-to-one correspondence with the plurality of non-volatile memory dies. The one or more control circuits are configured to add die-specific atomic requests to individual die-specific request queues of the plurality of die-specific request queues independently of each other in response to die-specific triggering events.

Abstract: Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.

Abstract: Embodiments are described for dynamically spawning and/or decommissioning backup proxy nodes in a virtual infrastructure. A backup server can include a polling agent that polls the virtual infrastructure to determine a list of virtual machines whose data is to be backed up, and a list if virtual proxy nodes that facilitate backups of virtual machine data. A proxy map can be generated that describes the mapping of virtual machines to backup proxy nodes in the virtual infrastructure. Rules can be applied to the proxy map to determine whether a new proxy node should be spawned or an existing proxy node should be decommissioned. A new virtual proxy can be generated by accessing a database of preconfigured template virtual proxies to quickly generate the new virtual proxy. One or more virtual machines can be remapped to the newly created virtual proxy to ensure optimal throughput of backup data.

Abstract: A method for executing a computer program, the method implemented by a processor comprising a plural number of computing units and an interconnect connected to the computing units, wherein each computing unit comprises a processing unit and a memory having at least two memory ports, each port assignable to one or more respective regions of the memory, wherein the method comprises at each computing unit: performing an initial step of the program to write: an initial output value to an output region of the memory, and an initial input value to an input region of the memory; and performing a subsequent step of the program by: in a compute phase: assigning one of the two ports to both the input region and the output region; executing code sequences on the processing unit to compute an output set of one or more new output values, and writing the output set to the output region, the output set computed from the initial output and initial input values, each of which is retrieved via said one port in the compute phas

Abstract: A processing apparatus is described. The apparatus includes a plurality of execution threads having a first thread space configuration including a first plurality of rows of execution threads to process data in parallel, wherein each thread in a row is dependent on a top neighbor thread in a preceding row, partition logic to partition the plurality of execution threads into a plurality of banks, wherein each bank includes one or more of the first plurality of rows of execution threads and transform logic to transform the first thread space configuration to a second thread space configuration including a second plurality of rows of execution threads to enable the plurality of execution threads in each of the plurality of banks to operate in parallel.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.

Abstract: A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.

Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

Abstract: A computing system is configured to maintain equivalency of independent queues located in different coupling facilities. The computer system includes a first coupling facility and a second coupling facility. The first coupling facility receives a plurality of different commands instructing the first coupling facility to load data into a first structure. The first coupling facility generates a first command data block including first data corresponding to a received first command and a first sequence value indicating a sequence at which the first data was loaded into the first structure with respect to remaining data corresponding to the plurality of commands. A second coupling facility includes a second structure and a second queue. The second coupling facility receives the first command data block from a first queue of the first coupling facility and loads the first data from the second queue into the second structure based on the first sequence value.

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Abstract: A system includes a cut-through bridge including a plurality of stages within a controller for communication packet transmission to transfer data and one or more control signals successively between the stages. The system also includes a control signal interceptor within the controller operable to intercept control signals between a first stage and a second stage of the cut-through bridge. The control signal interceptor is further operable to generate a forced valid control signal for each of the control signals regardless of an error condition of the control signals. The control signal interceptor outputs the forced valid control signal for each of the control signals to the second stage of the cut-through bridge. The forced valid control signal for each of the control signals is propagated through one or more successive stages of the cut-through bridge to an end stage to prevent an invalid state at the end stage.

Abstract: Systems, methods, and instrumentalities are disclosed for escape color coding for palette coding mode. A video bitstream may be received. The video bitstream may comprise a quantization parameter (QP) and/or a quantized escape color value that corresponds to an escape color pixel. A scaled escape color value may be generated by scaling the quantized escape color value by a scaling factor. A left-shift parameter may be determined based on the QP. A left-shifted escape color value may be generated by left-shifting the scaled escape color value based on the left-shift parameter. A right-shifted escape color value may be generated by right-shifting the left-shifted escape color value based on a constant parameter. A reconstructed escape color value may be determined based on the right-shifted escape color value. The device may decode the video bitstream based on the reconstructed escape color value.

Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.