METHOD OF MANUFACTURING SEMICONDUCTOR CHIP STACK
A method of manufacturing a semiconductor chip stack includes providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region; forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.
This application is a division of U.S. application Ser. No. 12/641,333 filed on Dec. 18, 2009, and incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a semiconductor chip stack and manufacturing method thereof, and more particularly, to a semiconductor chip stack having through-silicon via (TSV) and manufacturing method thereof.
2. Description of the Prior Art
Integrated circuit (IC) products are constructed by chips that are fabricated by conventional semiconductor manufacturing processes. The processes to fabricate a chip start with a wafer: a plurality of regions is defined on a wafer. Then, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are performed to form the desired circuit trace(s) and followed by separating each region to form a plurality of chips. Chips are packaged to form a chip package; and the chip package is attached on a board such as a printed circuit board (PCB). It is also well-known that the chip is electrically connected to pins on the PCB and thus each of the programs on the chip can be performed.
Pursuing thinner and lighter IC products, the semiconductor industries always tries to reach the limits to the process miniaturization, and to develop different package technologies. For example, flip-chip (FC) technology, multi-chip package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology are developed to stack the chips or packages in three dimensions, therefore density of the semiconductor devices per unit volume is increased. In recent years, a “through-silicon via (TSV)” technique is further developed to improve interconnections between chips in the package so as to increase the package efficiency.
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After separating the regions 102 to obtain the chips, the prior art is to stack and package the chips with different specific function, thus a semiconductor chip package 110 is obtained. As shown in
As mentioned above, the conventional chips respectively possess one specific function, and each chip comprises kinds of semiconductor devices in the sub-regions with different integration densities. However, the devices are formed by the same processes. For example, to comply with the process requirement for fabricating the devices with high integration density, high-grade semiconductor processes are performed to the wafer even though the devices with low integration density need no such high-grade semiconductor processes. In fact, devices with different integration densities require processes of different grades. Therefore, wastes of cost and source have been caused when the semiconductor processes are performed to the wafer 100. Consequently, a semiconductor chip stack and manufacturing method that is able to improve process efficiency and to lower the cost is still in need.
SUMMARY OF THE INVENTIONIt is therefore a primary objective of the present invention to provide a method of manufacturing a semiconductor chip stack that is able to improve process efficiency and to lower the cost.
According to the claimed invention a method of manufacturing a semiconductor chip stack is provided. The method comprises steps of providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout respectively corresponding to the first device layout in each second chip region; respectively forming a plurality of first TSVs in the first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.
According to the method of manufacturing the semiconductor chip stack provided by the present invention, circuit layouts of one specific function device are respectively formed on different chips according to the integration density, and then the chips are electrically connected by TSV technology. Thus the desired specific function is obtained. Since different chips are to be formed with different integration densities, processes of high-grade or low-grade is performed to form the chips according to its integration density. Therefore the process efficiency is improved while the cost is lowered.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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Step 200: providing a circuit layout of a function device, the circuit layout further comprising a first device layout 312 and a second device layout 412.
In the first preferred embodiment, the function device includes a memory device such as a dynamic random access memory (DRAM) or a NAND-type non-volatile memory. It is well-known to those skilled in the art that the circuit layout of the DRAM or the NAND-type non-volatile memory further includes a memory core array layout which comprises higher integration density, and a peripheral circuit layout having logic circuits, electrostatic discharge (ESD) protection devices and I/O pads, which comprises lower integration density. In the first preferred embodiment, the first device layout is the memory core array layout of higher integration density and the second device layout is the peripheral circuit layout of lower integration density.
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Step 210: defining a plurality of first chip regions 310 on a first wafer 300, and forming the first device layout 312 in each first chip region 310;
Step 212: defining a plurality of second chip regions 410 on a second wafer 400, and forming the second device layout 412 in each second chip region 410;
It is noteworthy that Step 210 and Step 212 are performed to form the first device layout 312 and second device layout 412 on the first wafer 300 and the second wafer 400 respectively, therefore Step 210 and Step 212 can be performed simultaneously or sequentially by the related semiconductor processes. Since the integration densities of the first device layout 312 and the second device layout 412 are different, the first device layout 312 with higher integration density is formed on the first wafer 300 by high-grade processes, and the second device layout 412 with lower integration density is formed on the second wafer 400 by low-grade processes.
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Step 220: forming a plurality of first TSVs 330 and a plurality of second TSVs 430 respectively in the first wafer 300 and the second wafer 400.
Step 230: respectively cutting the first wafer 300 and the second wafer 400 to form a plurality of first chips 320 and a plurality of second chips 420.
According to Step 220 of the first preferred embodiment, the first TSVs 330 (shown in
According to Step 230, the obtained first chip 320 and the second chip 420 respectively comprise the first device layout 312 and the second device layout 412. In other words, the first chip 320 comprises a memory core array of a DRAM or an NAND-type non-volatile memory while the second chip 420 comprises a peripheral circuit of the aforementioned memory, such as logic circuits, ESD protection devices and I/O pads. Thus, the second chip 420 serves as a global interface chip.
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Step 230: stacking the first chip 320 and the second chip 420 on a carrier 502.
As shown in
According to the first preferred embodiment, the provided semiconductor chip stack 500 comprises a first chip 320 having a first circuit 312 of a first integration density formed therein and a second chip 420 having a second circuit 412 of a second integration density formed therein. The first chip 320 and the second chip 420 respectively comprise at least a first TSV 330 and at least a second TSV 430. As mentioned above, the first circuit 312 comprises a core array of a memory such as DRAM or NAND-type non-volatile memory. The second circuit 412 is corresponding to the first circuit 312, and comprises logic circuits, ESD protection devices and I/O pads of the memory. Additionally, the first chip 320 and the second chip 420 are not limited to comprise micro electro-mechanical systems (MEMS) structures.
As mentioned above, the core circuit and the peripheral circuit of a function device such as DRAM or NAND-type non-volatile memory are respectively fabricated on different chips according to its integration densities, and followed by packaging process. The chips respectively comprise the core circuit and the peripheral circuit are then electrically connected by TSVs to obtain the desired specific function. Since different chips are to be formed with different integration densities, high-grade or low-grade processes are performed to fabricate the chips according to its integration density. Therefore the process efficiency is improved while the cost is lowered.
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According to the second preferred embodiment, the first device layout 312 formed on the first chip 322 comprises at least two different core circuits 312a/312b, which are core arrays of the first memory and the second memory. And the peripheral circuits 412a/412b comprising logic circuits, ESD protection devices and I/O pads of the first memory and the second memory are formed in the second chip 422. The core circuits and the peripheral circuits of function devices are respectively fabricated on different chips according to its integration densities, and followed by packaging process. The chips respectively comprise the core circuit and the peripheral circuit are then electrically connected by TSVs to obtain the desired specific function. According to the second preferred embodiment, the first chip 322 is fabricated to comprise core arrays of different memories, therefore function of the semiconductor chip 500 is enhanced. Since different chips are to be formed with different integration densities, high-grade or low-grade processes are performed to fabricate the chips according to its integration density. Therefore the process efficiency is improved while the cost is lowered.
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Step 202: providing a third wafer 600 having a plurality of third chip regions 610 defined therein.
Step 214: As shown in
It is noteworthy that an integration density of the third device layout 612 is larger than an integration density of the second device layout 412. The first device layout 312 and the third device layout 612 respectively comprises a core array of a first memory and a core array of a third memory. For example, the first device layout 312 is a DRAM core array and the third device layout 612 is an NAND-type non-volatile memory core array. In a modification of the third preferred embodiment, both of the first device layout 312 and the third device layout 612 comprise a core array of a first memory and a core array of a third memory. For example, both of the first device layout 312 and the third device layout 612 comprise a DRAM core array and an NAND-type non-volatile memory core array. Thus the first device layout 312 and the third device layout 612 comprise same memory core arrays. According to the third preferred embodiment, the second device layout 412 comprises a peripheral circuit having logic circuits, ESD protection devices and I/O pads of the first memory and another peripheral circuit having logic circuits, ESD protection devices and I/O pads of the third memory.
Step 222: forming a plurality of first TSVs 330, a plurality of second TSVs 430 and a plurality of third TSVs 630 respectively in the first wafer 300, the second wafer 400 and the third wafer 600.
Step 232: As shown in
According to Step 222, the first TSVs 330 are formed in the first chip region 310, the of second TSVs 430 are formed in the second chip region 410, and a plurality of third TSVs 630 are formed in the third chip region 610 as shown in
Because the second device layout 412 comprises the peripheral circuits of the first memory and the second memory, the second chip 420 serves as a global interface chip of the first chip 320 and the third chip 620.
Step 242: As shown in
The first chip 320, the second chip 420 and the third chip 620 are stacked on the carrier 512 and packaged to form a semiconductor chip stack 510. In the third preferred embodiment, the second chip 420, which servers as the global interface chip, is positioned between the first chip 320 and the third chip 620, but not limited to this.
According to the third preferred embodiment, the provided semiconductor chip stack 510 comprises a first chip 320 having a core circuit 312 of a first integration density formed therein, a third chip 620 having a core circuit 612 of the first integration density formed therein, and a second chip 420 having a peripheral circuit 412 of a second integration density formed therein, and the peripheral circuit 412 is corresponding to the core circuits 312/612. The first chip 320, the second chip 420 and the third chip 620 respectively comprise at least a first TSV 330, at least a second TSV 430 and at least a third TSVs 630. As mentioned above, the core circuit 312/612 comprises core array of memories such as DRAM or NAND-type non-volatile memory while the peripheral circuit 314 comprises logic circuits, ESD protection devices and I/O pads of the abovementioned memories. Additionally, the first chip 320, the second chip 420 and the third chip 620 are not limited to comprise MEMS structures.
It is noteworthy that the core arrays of higher integration density are fabricated in the first chip 320 and the third chip 620 and the peripheral circuit of lower integration density is fabricated in the second chip 420. Therefore the semiconductor processes of high-grade are performed to the first chip 320 and the third chip 620 while the semiconductor processes of low-grade are performed to the second chip 420. Accordingly, process efficiency is improved.
According to the semiconductor chip stack and manufacturing method provided by the present invention, circuit layouts of one function device are respectively form on different chips according to the integration density, then the chips are electrically connected by FC, MCP, or preferably TSV technology. Thus the desired specific function is obtained. Since different chips are to be formed with different integration densities, processes of high-grade or low-grade is performed to form the chips according to its integration density. Therefore the process efficiency is improved while the cost is lowered. Furthermore, because TSV technology is adapted in the present invention, the provided method of manufacturing a semiconductor chip stack also can be used in different package technologies such chip-to-chip, chip-to-wafer or wafer-to-wafer processes.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1. A method of manufacturing a semiconductor chip stack comprising steps of:
- providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout;
- defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region;
- defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region;
- forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and
- respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.
2. The method of claim 1 further comprising a step of forming a plurality of second TSVs in each second chip region.
3. The method of claim 1, wherein the first device layout comprises a core array of a memory.
4. The method of claim 3, wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads of the memory.
5. The method of claim 1, wherein the first device layout comprises at least a core array layout of a first memory and a core array layout of a second memory.
6. The method of claim 5, wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads respectively of the first memory and the second memory.
7. The method of claim 1 further comprising:
- providing a third wafer having a plurality of third chip regions defined thereon;
- forming a third device layout respectively in each third chip region, an integration density of the third device layout is larger than an integration density of the second device layout; and
- cutting the third wafer to form a plurality of third chips.
8. The method of claim 7 further comprising a step of forming a plurality of third TSVs in each third chip region.
9. The method of claim 7, wherein the first device layout and the third device layout respectively comprises a core array of a first memory and a core array of a third memory, and the first memory is different from the third memory.
10. The method of claim 9, wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads respective of the first memory and the third memory.
11. The method of claim 7, wherein the first device layout and the third device layout comprises same memory core arrays.
12. The method of claim 11, wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads corresponding to the memory core arrays.
13. The method of claim 1 further comprises a step of stacking the first chip and the second chip on a carrier.
Type: Application
Filed: Feb 20, 2012
Publication Date: Aug 23, 2012
Inventors: John Hsuan (Hsinchu City), Tai-Sheng Feng (Hsinchu City)
Application Number: 13/400,558
International Classification: H01L 21/78 (20060101);