FAULT TOLERANT REDUNDANT CLOCK CIRCUIT
A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
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The present application claims benefit under 35 USC 119(e) of U.S. provisional application No. 61/116,269, filed Nov. 19, 2008, entitled “Fault Tolerant Redundant Clock Circuit”, the content of which is incorporated herein by reference in its entirety.
BRIEF DESCRIPTION OF THE DRAWINGSA clock generation circuit, in accordance with one embodiment of the present invention, is immune to single transient and single permanent faults within the redundant circuits, and generates an oscillating signal without receiving an external clock signal. The oscillation is achieved by charging and discharging a capacitor and comparing the voltage developed across the capacitor to one or more predefined threshold values.
A clock generation circuit, in accordance with another embodiment of the present invention includes n redundant clock generators whose output signals are combined into a single fault-tolerant clock signal via m voters and a logic unit. The redundancy and voters allow proper clock operation even when a fault occurs within any one of the individual clock generators.
Each clock generator 100i, where i is an integer varying from 1 to N, is shown as including, in part, a reference current source 102i, a capacitor 104i, a comparator 106i, a reference voltage generator 108i, and a switching circuit 110i. For example, clock generator 1001 is shown as including, in part, a reference current source 1021, a capacitor 1041, a comparator 1061, a reference voltage generator 1081, and a switching circuit 1101. Likewise, clock generator 100N is shown as including, in part, a reference current source 102N, a capacitor 104N, a comparator 106N, a reference voltage generator 108N, and a switching circuit 110N.
Each clock generator generates M control signals each of which is applied to a different one of M voters 150j, where j is an integer varying from 1 to M. For example, control signals Ctrl11, Ctrl12 . . . Ctrl1M generated by comparator 1061 are respectively applied to voters 1501, 1502 . . . 150M. Control signals Ctrl21, Ctrl22 . . . Ctrl2M generated by comparator 1062 are respectively applied to voters 1501, 1502 and 150M. Likewise, control signals CtrlN1, CtrlN2 . . . CtrlNM generated by comparator 106N are respectively applied to voters 1501, 1502 and 150M, as shown. Logic unit 180 is configured to generate oscillating signals OSC and
The switching circuit 110i and reference current 102i disposed in clock generator 100i are adapted to enable the voltage across the associated capacitor 104i to charge, discharge or float in response to the signals OSC and
Each comparator 106i is adapted to compare the voltage across its associated capacitor 104i to its reference voltages Vrefia and Vrefib, and to assert one of its output signals Ctrli1, Ctrli2 . . . CtrliM as a result of this comparison. Each voter 150i may be a majority voter and generates an output signal Outi representative of the majority of the input vote signals the voter receives. The M voter output signals OUT1, OUT2, . . . OUTM are inputs to a logic unit 180. The M voter output signals that are inputs to the logic unit provide information about the voltage across the capacitors 104i. In response to these signals, the logic unit decides the state of the clock signals OSC and
Clock generator 3501 is shown as including, in part, a switching circuit 310, a reference current source 302, a capacitor 304, a comparator 306, and a reference voltage generator 308. Reference voltage generator 308, shown as including an amplifier 320 and resistors 322 and 324, receives a global DC reference voltage Vrefglobal, and in response, generates reference voltages Vref and Vref2 that are supplied to comparator 306. Power supply voltages VCC, GND, the global reference voltage Vrefglobal, and hardened clock output signals OSC and
The reference currents (such as reference current 302) supplied to the three redundant clock generation circuits 3501 3502, and 3503 are independent from another to ensure fault tolerance. The internal reference voltages, namely Vref and Vref2 are generated independently within each of the three redundant clock generation circuits to further ensure fault tolerance. Although the following description is provided with reference to clock generator 3501, it is understood that the remaining two clock generators operate in the same manner.
Switching circuit 310 is shown as including MOS transistors 312, 314, 316, 318, and bipolar transistors 320, 322. Switching circuit 310 is adapted to cause the voltage across capacitor 304 to either charge to reference voltage Vref2, or to discharge to reference voltage Vref, or to float, as described further below. The voltage ramp rate across capacitor 304 is defined by the capacitance of capacitor 304 and value of reference current IREF flowing from current source 302. Output signal Set of comparator 306 is at a logic high level when the voltage at node N2 of capacitor 304 is higher than reference voltage Vref2. Likewise, output signal Set of comparator 306 is at a logic low level when the voltage at node N2 is smaller than the reference voltage Vref2. Output signal Reset of comparator 306 is at a logic high level when the voltage at node N2 is lower than reference voltage Vref, and at a logic low level when the voltage at node N2 is higher than reference voltage Vref. Comparator 306 has hysteresis to avoid jitter of the signals Set and Reset.
During a capacitor voltage ramp-up cycle, signal
When the Set signal associated with two or more of the redundant clock generators 3501, 3502 and 3503 is at a high level, voter 370's output changes state to high, thereby causing output signal OSC of RS flip-flop 374 to go high and output signal
When the Reset signal associated with two or more of the clock generators (redundant blocks) is at a high level, voter 372 changes state thereby causing output signal OSC of RS flip-flop 374 to go low and output signal
Each of voters 370 and 372 may be a majority voter. The output of each majority voter goes high when two or more of its inputs are high. Likewise, the output of each majority voter goes low when two or more of its inputs are low. Majority voter 370 receives the Set signals from redundant clock generators 3501, 3502 and 3503. Majority voter 372 receives the Reset signals from redundant clock generators 3501, 3502 and 3503. The outputs of voters 370 and 372 are respectively applied to the Set and Reset input terminals of RS flip-flop 374. Each of voters 370, 372 and RS flip-flop 374 are designed to be single-event immune, as is well known, to withstand high energy particles when deployed in non-terrestrial applications such as satellites. Therefore, as a result of the redundancy, the output signals OSC and
As described above, output signals Set and Reset of comparator 306 are used as feedback signals to switching circuit 310, thereby enabling capacitor 304 to float when the voltage at node N2 is outside the voltage range defined by voltages Vref to Vref2. These feedback signals enable the redundant clock generators 3501, 3502 and 3503 to be synchronized. In the absence of the present invention, because of the inherent mismatches in electrical characteristics of the components used in redundant blocks 3501, 3502 and 3503, the capacitors may have different ramp rates, the reference currents may have different levels, etc. which in turn may result in the respective capacitor voltages to fall outside the normal operating range and destroy the synchronization of the redundant clocks. Such synchronization problems are overcome by using the feedback signals Set and Reset within the redundant blocks 3501, 3502 and 3503, as described above.
In generating the simulation results shown in
The ramp rate of the capacitor disposed in clock generator 3503, namely plot 400, is shown as being faster than that of the other two capacitors, due to the higher reference current supplied to this capacitor. The voltage across the capacitor disposed in clock generator 3503 is shown as exceeding the reference voltage Vref2 at time T1. Accordingly, at time near T1, clock generator 3503 asserts its associated set signal Seta (see plot 415 of
The voltage developed across the capacitor disposed in clock generator 3502, namely Plot 410, is shown as exceeding the reference voltage Vref2 at time T2. Accordingly, clock generator 3502 asserts its associated set signal Set2 at time near T2 (see plot 425 of
The voltage across the capacitor disposed in redundant clock generator 3503 is shown as falling below the reference voltage Vref at time T4. Accordingly, at time near T4, signal Reset3 is asserted (see plot 420 of
Referring to
The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of switching circuit, amplifier, comparator, etc., used in the clock generator. The invention is not limited to the type or the number of redundant blocks or voters. The invention is not limited by the type of integrated circuit in which the present disclosure may be disposed. Nor is the invention limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Claims
1-10. (canceled)
11. A clock generation circuit comprising:
- a first comparator responsive to a first input signal, said first comparator being adapted to change a first output signal when the first input signal is detected as being greater than a first reference, and further to change a second output signal when the first input signal is detected as being smaller than a second reference;
- a first logic unit responsive to the first comparator and adapted to generate a a clock signal in response to the first and second output signals; and
- a first switching circuit adapted to vary the first input signal in response to the first and second output signals and the clock signal.
12. The clock generation circuit of claim 11 further comprising:
- a current source adapted to supply a reference current to the first switching circuit; and
- a capacitor adapted to charge, discharge or float in response to first switching circuit.
13. The clock generation circuit of claim 12 wherein said capacitor is disposed between the current source and the comparator.
14. The clock generation circuit of claim 11 further comprising:
- a second comparator responsive to a second input signal, said second comparator being adapted to change a third output signal when the second input signal is detected as being greater than a third reference, and further to change a fourth output signal when the second input signal is detected as being smaller than a fourth reference;
- a second switching circuit adapted to vary the second input signal in response to the third and fourth output signals and the clock signal;
- a third comparator responsive to a third input signal, said third comparator being adapted to change a fifth output signal when the third input signal is detected as being greater than a fifth reference, and further to change a sixth output signal when the third input signal is detected as being smaller than a sixth reference;
- a third switching circuit adapted to vary the third input signal in response to the fifth and sixth output signals and the clock signal;
- said logic unit being responsive to the third, fourth, fifth and sixth output signals.
15. The clock generation circuit of claim 14 further comprising first and second voters responsive to the first, second and third comparators.
16. The clock generation circuit of claim 14 wherein each of said first, second and third switching circuits comprises first, second, third, fourth, fifth and sixth transistor, said first transistor receiving a reference current at a first terminal and a first one of a pair of complementary clock signals at its second input terminal, said second transistor receiving the reference current at a first terminal and a second one of the pair of complementary clock signals at its second input terminal, said third transistor having a first terminal coupled to a third terminal of the first transistor and a second terminal receiving a first output signal of an associated comparator, said fourth transistor having a first terminal coupled to a third terminal of the second transistor and a second terminal receiving a second output signal of the associated comparator, said fifth transistor having first and second terminals coupled to a third terminal of the third transistor, and a third terminal coupled to a voltage supply or ground, said sixth transistor having a first terminal coupled to a third terminal of the fourth transistor, a second terminal coupled to the second terminal of the fifth transistor and a third terminal coupled to the voltage supply or ground.
17. A clock generation circuit comprising:
- N clock generators each comprising:
- a comparator adapted to compare an input signal to each of M reference signals and to assert M output signals in response;
- a switching circuit responsive to an associated comparator's M output signals and to a pair of oscillating feedback signals, said switching circuit adapted to generate the input signal in response;
- M voters responsive to the M output signals of the N comparators; and
- a logic unit responsive to the voters and generating the pair of oscillating feedback signals in response.
18. An electronic system comprising:
- a functional circuit having an input, and output and a clock input;
- a clock generation circuit, coupled to the clock input of the functional circuit, the clock generation circuit comprising: a comparator responsive to a first input signal, said comparator being adapted to change a first signal when the first input signal is detected as being greater than a first reference, and further to change a second signal when the first input signal is detected as being smaller than a second reference; a first logic unit responsive to the comparator and adapted to generate a clock signal in response to the first and second signals; and a first switching circuit adapted to vary the first signal in response to the first and second signals and the clock signal.
Type: Application
Filed: Jun 22, 2012
Publication Date: Oct 18, 2012
Applicant: INTERSIL AMERICAS INC. (Milpitas, CA)
Inventor: Harold William Satterfield (Rockledge, FL)
Application Number: 13/531,422