Phase Lock Loop Patents (Class 327/156)
  • Patent number: 10447285
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 15, 2019
    Inventors: Roman Staszewki, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 10447283
    Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequency. The PLL circuit includes a multiplexer coupled to the first VCO, the second VCO, and a feedback loop. The PLL circuit includes a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal using the feedback loop, and a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, where the phase frequency detector is configured to receive a reference signal and the feedback signal to tracking a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 15, 2019
    Assignees: SPEEDLINK TECHNOLOGY INC., GEORGIA TECH RESEARCH CORPORATION
    Inventors: Doohwan Jung, Thomas Chen, Hua Wang
  • Patent number: 10444745
    Abstract: A method for automated configuration of a tester equipped for testing a control unit. A first and second model of technical systems being executed in the tester. The execution of the models taking place periodically with defined sampling rates. An FPGA executes the first and/or the second model and a CPU executes the first or the second model. A first individual sampling rate is allocated for the first model and a second individual sampling rate is allocated for the second model. The first model is assigned for execution on either the CPU or the FPGA and the second model is assigned for execution on either the CPU or the FPGA. The tester is automatically configured for execution of the first model with the first allocated sampling rate on the FPGA or the CPU and of the second model with the second allocated sampling rate on the FPGA or the CPU.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 15, 2019
    Assignee: dSPACE digital signal processing and control engineering Gmbh
    Inventors: László Juhász, Jesse Lakemeier
  • Patent number: 10439555
    Abstract: A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 8, 2019
    Assignee: NXP B.V.
    Inventors: Tarik Saric, Juan Felipe Osorio Tamayo
  • Patent number: 10439620
    Abstract: A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theertham Srinivas, Jagdish Chand Goyal, Peeyoosh Mirajkar
  • Patent number: 10418983
    Abstract: A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 10418942
    Abstract: Embodiments of a reference path circuit and communication device are generally described herein. The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output frequency that is based on an integer multiple of the reference frequency. The integer multiple of the reference frequency may be within a locking range of the ILM that may be based on a resonant frequency of the ILM. The group of one or more buffer amplifiers may generate an output clock signal for input to the frequency synthesizer. The output clock signal may be based on a sign function of the ILM output signal.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel IP Corporation
    Inventors: Igal Yehuda Kushnir, Gil Horovitz, Ronen Kronfeld, Sarit Zur
  • Patent number: 10411740
    Abstract: A soft decision analyzer system is operable to interconnect soft decision communication equipment and analyze the operation thereof to detect symbol wise alignment between a test data stream and a reference data stream in a variety of operating conditions.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 10, 2019
    Assignee: United States of America as represented by the Adminsitrator of the National Aeronautics and Space Administration
    Inventors: Glen F. Steele, Chatwin Lansdowne, Joan P. Zucha, Adam M. Schlesinger
  • Patent number: 10411719
    Abstract: Disclosed are methods and apparatuses for providing direct measurement delay calibration. An apparatus may include a plurality of delay elements in a loop. The apparatus may also include a controller coupled to the plurality of delay elements. The controller may be configured to cause determining, for a predetermined time period, delay oscillations from the plurality of delay elements in the loop. The controller may also be configured to cause determining, based on the determined delay oscillations, the predetermined time period, and a quantity of the plurality of delay elements, a subset of the plurality of delay elements for delaying an input signal. The controller may also be configured to cause routing the input signal through the subset of the plurality of delay elements.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 10, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Mark S. Elliott
  • Patent number: 10404316
    Abstract: A method includes generating a reference clock using a crystal oscillator; generating a first clock based on the reference clock using a clock multiplier unit, in which a frequency of the first clock is higher than a frequency of the reference clock by a clock multiplier factor; generating a second lock based on the first clock using a frequency multiplying circuit in accordance with a frequency multiplying signal, in which a frequency of the second clock is higher than the frequency of the first clock by a factor that is equal to either five fourths or three halves, depending on whether the frequency multiplying signal is in a first state or in a second state; dividing down the second clock by a factor of two to generate a first LO (local oscillator) signal; dividing down the first LO signal by a factor of two to generate a second LO signal.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 3, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Fei Song, Chia-Liang (Leon) Lin
  • Patent number: 10388341
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tsuneo Abe
  • Patent number: 10382014
    Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: August 13, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Ljubisa Bajic, Stephen V. Kosonocky, Steven J. Kommrusch
  • Patent number: 10374620
    Abstract: A frequency divider circuit and a frequency synthesizer circuit are presented, comprising: first and second flip-flops; a phase inverter, wherein an output electrode of the first flip-flop is connected to an input electrode of the second flip-flop and an output electrode of the phase inverter, an output electrode of the second flip-flop is connected to an input electrode of the phase inverter and an input electrode of the first flip-flop, a control electrode of the phase inverter is connected to a control signal; and a control module, wherein the first flip-flop is connected to a voltage source through the control module, the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source. When the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Pandou Xue, Guangtao Feng
  • Patent number: 10367543
    Abstract: In one form, a spread spectrum clock generator includes a clock generator and a modulator. The clock generator modulates a frequency of a reference clock signal using a modulation signal to provide a spread spectrum clock signal. The clock generator has a characteristic transfer function that varies with values of a parameter. The modulator generates the modulation signal according to a desired profile conditioned by an inverse of the characteristic transfer function of the clock generator at a current value of the parameter.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 30, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Toru Dan
  • Patent number: 10367667
    Abstract: Various embodiments relate to a method for classifying received radio frequency signals, including: receiving an input signal; matched filtering the input signal to produce a correlation result signal; sampling the correlation result signal at a plurality of half-bit-grids and a plurality of bit-grids to produce a set of modulated phase correlation result samples and a set of non-modulated phase correlation result samples; calculating a minimum of the set of modulated phase correlation result samples; calculating a maximum of the set of non-modulated phase correlation result samples; and classifying the input signal as valid data or collision data based on the minimum and the maximum.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 30, 2019
    Assignee: NXP B.V.
    Inventors: Ulrich Andreas Muehlmann, Ulrich Neffe
  • Patent number: 10352733
    Abstract: A process for the acquisition of data of a counting device measuring pulses delivered by a sensor can include reading a first datum value of the counting device. The first datum value corresponds to the pulse emitted by the sensor. The process can also include storing in memory the first datum value as a source value. The process can also include measuring a time-interval between said reading and an incremental change of the first datum value of the counting device to a second datum value. The process can also include obtaining a first adjustment value Vx in response to the measured time interval.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 16, 2019
    Assignee: DEWESOFT
    Inventors: Jure Knez, Tilen Sotler
  • Patent number: 10348310
    Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Karim M. Megawer, Parag Upadhyaya, Didem Z. Turker Melek, Zhaoyin D. Wu
  • Patent number: 10348313
    Abstract: An object detection system for autonomous vehicle, comprising a radar unit and at least one ultra-low phase noise frequency synthesizer, is provided. The radar unit configured for detecting the presence and characteristics of one or more objects in various directions. The radar unit may include a transmitter for transmitting at least one radio signal; and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-low phase noise frequency synthesizer may utilize Clocking device, Sampling Reference PLL, at least one fixed frequency divider, DDS and main PLL to reduce phase noise from the returned radio signal. This proposed system overcomes deficiencies of current generation state of the art Radar Systems by providing much lower level of phase noise which would result in improved performance of the radar system in terms of target detection, characterization etc. Further, a method for autonomous vehicle is also disclosed.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: July 9, 2019
    Inventors: Yekutiel Josefsberg, Tal Lavian
  • Patent number: 10348180
    Abstract: Various examples are directed to electrical converters and systems for operating the same. An electrical converter may comprise a first converter module configured to receive a first direct current (DC) input and provide a first output. The first converter module may comprise a first switch modulated according to a first switch control signal. A second converter module may be configured to receive a second DC input and provide a second output. The second converter module may be connected in series with the first converter module. The second converter module may comprise a second switch modulated according to a second switch control signal. A phase of the first switch control signal may be offset from a phase of the second switch control signal by a first phase offset.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: July 9, 2019
    Assignees: SINEWATTS, INC., THE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE
    Inventors: Shibashis Bhowmik, Babak Parkhideh
  • Patent number: 10333535
    Abstract: An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 25, 2019
    Assignee: Altera Corporation
    Inventors: David Mendel, Carl Ebeling, Dana How, Mahesh Iyer
  • Patent number: 10333534
    Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 10321304
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for transmitting, by a first device, a transmission signal that includes a carrier signal modulated with a TM signal. Receiving a response signal from a second device in response to the transmission signal. Determining, whether the response signal includes the TM signal.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 11, 2019
    Assignee: TM IP Holdings, LLC
    Inventors: Richard C. Gerdes, Daniel L. Hodges, Quinn Colin McIntosh
  • Patent number: 10312824
    Abstract: The invention relates to a modular multilevel converter (2) having a control module (4) and a computer (10) for computing a setpoint for the internal energy of the converter stored in the capacitors of the submodules of the arms. The control module is configured to deduce, from the setpoint for the internal energy of the converter, a setpoint for the voltage across the terminals of each modeled capacitor, which setpoint is used for regulating the voltage across the points of common coupling between the converter and the DC power supply network and the voltage across the terminals of each modeled capacitor.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 4, 2019
    Assignees: SUPERGRID INSTITUTE, INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON, CENTRALESUPELEC
    Inventors: Kosei Shinoda, Abdelkrim Benchaib, Xavier Guillaud, Jing Dai
  • Patent number: 10302699
    Abstract: A measurement system may measure a fractional time delay of transmission of a signal across a medium, such as a cable. The system may use a first clock to assist in creating and injecting an injected sequence (signal) into the medium. A second, slower clock may be used for sampling the sequence after transmission of the sequence through the medium. This causes a time Vernier scale effect that results in a sampled sequence that has a one-step skip for each instances of the sequence, where the sequence has N elements in the sequence. The location of the skip within the sequence will depend on the magnitude of the delay measured as a fraction of a clock period with a resolution of N. To measure this delay, a modified version of a pseudo-random sequence generator, capable of skipping one step, is used to determine the output.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 28, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Carlos Guillermo Parodi
  • Patent number: 10305494
    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon Lee, Donghun Lee, Jaewon Lee
  • Patent number: 10304547
    Abstract: A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeonkyu Choi, Seungjun Shin
  • Patent number: 10291242
    Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Elbadry, Marco Zanuso, Tsai-Pi Hung, Francesco Gatta, Yunliang Zhu
  • Patent number: 10291386
    Abstract: A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 14, 2019
    Assignee: Cavium, LLC
    Inventor: Scott E. Meninger
  • Patent number: 10291238
    Abstract: An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Motozawa, Yoshitaka Hirai
  • Patent number: 10291214
    Abstract: Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: May 14, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Bartholomeus Jacobus Thijssen, Eric Antonius Maria Klumperink, Bram Nauta, Philip Eugene Quinlan
  • Patent number: 10284205
    Abstract: A clock generator and a method to control an associated system are described. The clock generator (e.g., a PLL) can include a charge pump that can generate a current, and a controller coupled to the charge pump. The controller can determine a characteristic impacting operation of the clock generator and control the charge pump to adjust the current based on the determined characteristic to adjust a bandwidth of the clock generator. The clock generator and method can include adjusting the bandwidth to compensate for variations (e.g. PVT variations) that impact the operation of the clock generator to maintain constant or substantially constant bandwidth independent of such variations.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Samaksh Sinha, Sai Siddharth Pothapragada
  • Patent number: 10270487
    Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, wherein the modulation frequency is higher than a frequency of the reference clock; a reference phase generating unit arranged for generating a reference phase according to the reference clock, the modulation clock, the first FCW, the second FCW, and the third FCW; a digital-controlled oscillator (DCO) arranged for to generating the oscillator clock according to the reference phase. An associated method is also disclosed.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Liao, Min-Shueh Yuan, Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10263605
    Abstract: The invention discloses a frequency extender, including a preamplifier to receive a RF input signal and output a pre-amplified RF signal, a series frequency multiplier branch, a series frequency divider branch and a multiplexer. The output port of the preamplifier couples to one input port of the multiplexer. The series frequency multiplier branch and the series divider branch are coupled to receive the pre-amplified RF signal. The output port of each frequency multiplier in the series multiplier branch and/or the output port of each frequency divider in the series divider branch are coupled to the input ports of the multiplexer respectively. The multiplexer couples to receive the pre-amplified RF signal, the frequency-multiplied RF signal and the frequency-divided signal, the multiplexer selects a signal from the received signals and outputs a multiplexer output signal based on the selected signal.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 16, 2019
    Inventor: Cemin Zhang
  • Patent number: 10263626
    Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 16, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hua Wang, David Steven Ripley, Bryan J. Roll
  • Patent number: 10256967
    Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 9, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chang-Cheng Huang, Shen-Iuan Liu, Ju-Lin Huang, Tzu-Chien Tzeng, Keko-Chun Liang, Yu-Hsiang Wang, Che-Wei Yeh
  • Patent number: 10250243
    Abstract: A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 2, 2019
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Seonggyu Lee, Yongjo Kim, SeongHwan Cho
  • Patent number: 10236898
    Abstract: A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Olivier Vincent Doare, Birama Goumballa, Cristian Pavao Moreira
  • Patent number: 10224937
    Abstract: An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 5, 2019
    Assignee: XILINX, INC.
    Inventors: Zhaoyin D. Wu, Geoffrey Zhang, Parag Upadhyaya, Kun-Yung Chang
  • Patent number: 10209735
    Abstract: An apparatus is configured to receive a two-phase input clock and output a four-phase output clock, the apparatus includes a first data latch and a second data latch configured in a ring topology with a negative feedback based on inter-connection through a four-phase level-shifted clock, the first data latch configured to receive a fourth phase and a second phase of the level-shifted clock and output a first phase and a third phase of the output clock along with a first phase and a third phase of the level-shifted clock in accordance with a first phase of the input clock, the second data latch configured to receive the first phase and the third phase of the level-shifted clock and output a second phase and a fourth phase of the output clock along with the second phase and the fourth phase of the level-shifted clock in accordance with a second phase of the input clock.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 19, 2019
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10205456
    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Cho-Ying Lu, William Yee Li, Khoa Minh Nguyen, Ashoke Ravi, Maneesha Yellepeddi, Binta M. Patel
  • Patent number: 10200045
    Abstract: A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 5, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Senta Sekido
  • Patent number: 10187069
    Abstract: A phase locked loop is disclosed comprising: a phase detector, a loop filter, a frequency controller oscillator and a lock detector. The phase detector is operable in a bang-bang mode to provide a binary phase error signal indicating whether there is a positive or negative phase difference between a reference signal and a feedback signal. The loop filter is configured to provide a control signal derived from the binary phase error signal. The frequency controlled oscillator is configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal. The lock/unlock detector is configured to determine a lock/unlock state of the phase locked loop, the lock/unlock state derived from a duty cycle and/or spectral content of the binary phase error signal.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 22, 2019
    Assignee: NXP B.V.
    Inventor: Ulrich Möehlmann
  • Patent number: 10181343
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: January 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tsuneo Abe
  • Patent number: 10177772
    Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 8, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jingcheng Zhuang, Xinhua Chen, Frederic Bossu, Yiwu Tang
  • Patent number: 10164644
    Abstract: Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Shenyang Neusoft Medical Systems Co., Ltd.
    Inventors: Peng Ning, Long Yang, Guodong Liang, Peng Gao, Liang He
  • Patent number: 10164766
    Abstract: A start-up control for a transmitter (TX) output driver is implemented to prevent the stick state problem when the TX driver is not toggling. TX output driver is set in a high impedance (HZ) mode when data zero is delivered from the digital base band (DBB) and set in an enhanced mode to deliver a stronger signal when data one is delivered from the DBB. The transmitter comprises a dual-loop PLL to synchronize the TX output pulse and the carrier. The dual-loop PLL is composed of a relaxation oscillator, a 1st Loop, and a 2nd Loop. The 1st loop is a voltage-controlled oscillator comprising the relaxation oscillator and an operational transconductance amplifier. The 2nd loop is a loop comprising a phase frequency detector, a charge pump, a loop filter and the VCO of the 1st loop.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 25, 2018
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Chen-Hsien Hung, Tao Huang, Shiau Chwun George Pwu
  • Patent number: 10158365
    Abstract: A reconfigurable frequency and delay generator is disclosed, and a representative embodiment may include a phase sampler and plurality of configurable oscillator stages, each configurable oscillator stage of the plurality of configurable oscillator stages comprising: a plurality of core inverters coupled in series, a last core inverter of the plurality of core inverters generating an output signal having a configurable output frequency; and a plurality of delay control circuits, each delay control circuit of the plurality of delay control circuits coupled to an output of a corresponding core inverter of the plurality of core inverters.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 18, 2018
    Assignee: Movellus Circuits, Inc.
    Inventors: Muhammad Faisal, Jeffrey Alan Fredenburg
  • Patent number: 10146250
    Abstract: In a general aspect, a method for adjusting an oscillator clock frequency can include applying a first control value to a first oscillator, applying a second control value, different from the first control value, to a second oscillator, measuring a frequency of each of the first and second oscillators, determining, by interpolation, a corrected frequency measurement of the second oscillator depending on a frequency deviation measured between the first and second oscillators when subjected to a third control value, on the third control value, and on the control value applied to the second oscillator, determining by interpolation a new first control value depending on the measured frequency of the first oscillator, on the corrected frequency, on the first and second control values, and on a desired frequency, and applying the new first control value to the first oscillator.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 4, 2018
    Assignee: INSIDE SECURE
    Inventors: Vincent Migairou, Julien Roche
  • Patent number: 10148272
    Abstract: A frequency generating circuit includes: a delay circuit, arranged to operably delay an output frequency signal to generate a delayed signal; a quartz crystal resonator, coupled with the delay circuit, arranged to operably conduct a band-pass filtering operation on the delayed signal to generate the output frequency signal; and a delay control circuit, coupled with the delay circuit, arranged to operably control a phase delay amount of the delay circuit to thereby control the phase of the delayed signal.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: December 4, 2018
    Inventor: Ping-Ying Wang
  • Patent number: 10141942
    Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh