Phase Lock Loop Patents (Class 327/156)
  • Patent number: 11184010
    Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yan-Guei Chen, Hsin-Yu Lue, Liang-Wei Huang, Hui-Min Huang
  • Patent number: 11183993
    Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Hundo Shin, Kameran Azadet, Martin Clara, Daniel Gruber
  • Patent number: 11176299
    Abstract: An approach for detecting potential failures and sensitivities, based on preliminary verification of timing circuits which includes feedback and combinatorial loops for is disclosed. The approach comprises relating timing events by algebraic equations, breaking loops, and feedbacks by backward reference, and then propagate signals through time and netlist.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Israel A. Wagner, Noam Jungmann
  • Patent number: 11165286
    Abstract: A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 2, 2021
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Teerasak Lee, Chee Weng Cheong, Yannick Guedon, Eng Jye Ng
  • Patent number: 11159085
    Abstract: An integrated circuit that drives a switching device provided between a first line on a ground side and a second line on a power supply side, when a power supply voltage is applied between a first input terminal connected with a first capacitor and a second input terminal, the first capacitor having one end grounded and another end connected to the first input terminal, the integrated circuit includes: a first terminal connected to a circuit element, the circuit element having one end grounded and another end connected to the first terminal; and a drive circuit that changes a voltage at the first terminal to one logic level when a drive signal of the switching device changes to the one logic level, and changes the voltage at the first terminal to another logic level when the drive signal changes to the other logic level.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryuji Yamada, Ryuunosuke Araumi, Takato Sugawara
  • Patent number: 11146274
    Abstract: An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 12, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Mikio Shiraishi
  • Patent number: 11146111
    Abstract: A power receiver includes: a secondary-side resonant coil that includes a resonant coil circuit and receives power from a primary-side resonant coil; a capacitor inserted into the resonant coil circuit; a series circuit including a first switch and a second switch; a first rectifying element having a first rectification direction; a second rectifying element having a second rectification direction; a detection circuit that detects a voltage or a current; a binarization processing circuit that outputs a rectangular wave obtained by binarizing the voltage or the current; a rectangular wave detection circuit that detects a rising or falling timing and a cycle of the rectangular wave; a reference clock generation circuit that generates a reference clock based on the rising or falling timing and the cycle; and a control circuit that generates a control clock used to switch on and off by adjusting a phase or a duty ratio.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Shimokawa, Hirotaka Oshima
  • Patent number: 11144088
    Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Jagannadha Rao V. V. V. Rapeta, Mikal Hunsaker, Ronald Swartz, Robert Fulton, L. Mark Elzinga, Young Min Park, David R. Mulvihill
  • Patent number: 11139818
    Abstract: A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 5, 2021
    Assignee: MEDIATEK INC.
    Inventors: Po-Chun Huang, Yu-Li Hsueh, Chao-Ching Hung
  • Patent number: 11133806
    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: September 28, 2021
    Assignee: Space Exploration Technologies Corp.
    Inventors: David Francois Jacquet, Mostafa Ghazali, Masoud Kahrizi, Andras Tantos
  • Patent number: 11128304
    Abstract: A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 21, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yun-Sheng Yao, Shen-Iuan Liu, Yen-Long Lee, Peng-Yu Chen, Chih-Hao Huang, Yao-Hung Kuo
  • Patent number: 11115178
    Abstract: A clock and data recovery device includes a phase detector circuitry, an analog modulation circuitry, a serial-to-parallel converter circuit, a digital modulation circuitry, and an oscillator circuit. The phase detector circuitry detects a data signal according to first and second clock signals to generate an up signal and a down signal. The analog modulation circuitry generates a first adjustment signal according to the up signal and the down signal. The serial-to-parallel converter circuit generates a first control signal according to the up signal, and to generate a second control signal according to the down signal. The digital modulation circuitry generates a digital code according to the first and the second control signals, and to generate a second adjustment signal according to the digital code. The oscillator circuit generates the first and the second clock signals according to the first adjustment signal and the second adjustment signal.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Jia-Ning Lou
  • Patent number: 11115038
    Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Laurent Truphemus, Christophe Eva
  • Patent number: 11108400
    Abstract: An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 31, 2021
    Assignee: Renesas Electronics America Inc.
    Inventor: Greg Armstrong
  • Patent number: 11094354
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11095296
    Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 17, 2021
    Assignee: INNOPHASE, INC.
    Inventors: Sara Munoz Hermoso, Per Konradsson, Yang Xu
  • Patent number: 11092994
    Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Kyu Dong Hwang
  • Patent number: 11088697
    Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: August 10, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Tsutsumi, Yuki Yanagihara, Mitsuhiro Shimozawa
  • Patent number: 11070217
    Abstract: Disclosed here is a PLL circuit that is an injection-locked PLL circuit. The PLL circuit includes a variable frequency oscillator configured in such a manner that a ring oscillator is formed during a period in which a window signal is negated and an injection edge based on a reference clock is allowed to be injected during a period in which the window signal is asserted, a feedback circuit that controls the variable frequency oscillator in such a manner that an oscillation frequency of the variable frequency oscillator gets closer to a target frequency according to the reference clock, and a window generator that receives an internal clock of the variable frequency oscillator and cuts out one pulse to generate the window signal.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: July 20, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Masanobu Tsuji
  • Patent number: 11048284
    Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Gerhard Schrom, Vaughn J. Grossnickle, Nasser A. Kurd
  • Patent number: 11043941
    Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 11043955
    Abstract: A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: June 22, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Tsutsumi, Sho Ikeda, Mitsuhiro Shimozawa
  • Patent number: 11038462
    Abstract: There is provided a semiconductor device including an oscillation circuit that includes a plurality of capacitors provided on a semiconductor substrate, a conversion circuit that converts an analog signal into a digital signal, and a switch circuit that switches the capacitors on the basis of the digital signal. Further, an oscillation frequency linearly varies with respect to a variation in the analog signal.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 15, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hidenori Takeuchi, Taiwa Okanobu, Naoya Arisaka, Hitoshi Tomiyama
  • Patent number: 11005484
    Abstract: A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu Sik Kim, Woo Seok Kim, Tae Ik Kim, Hwan Seok Yeo
  • Patent number: 10998911
    Abstract: An apparatus is disclosed that includes a phase detector circuit for generating a first pulse signal based on first and second input clock signals. A first circuit adjusts the first pulse signal by delaying transmission of a leading edge of the first pulse signal, but not a trailing edge of the first pulse signal. A charge pump circuit charges or discharges a capacitor based on the adjusted first pulse signal, and a voltage controlled oscillator (VCO) circuit generates an output clock signal with a frequency that depends on a voltage on the capacitor.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 4, 2021
    Assignee: NXP USA, Inc.
    Inventors: Firas N. Abughazaleh, David Bearden
  • Patent number: 10979252
    Abstract: Aspects of the disclosure provide for a circuit comprising a transmitter. In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path to generate the output signal when the loss of signal indication signal has a second value.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yanli Fan, Amit Rane
  • Patent number: 10976765
    Abstract: A current generating circuit generating a current relevant to a reference voltage. The current generating circuit has a reference clock generating circuit generating a reference clock signal which has a frequency relevant to the reference voltage. The current generating circuit has a phase locked loop circuit generating a calibration clock signal. The phase clocked loop circuit regulates the calibration clock signal so that the phase difference between the calibration clock signal and the reference clock signal is reduced. The current generating circuit has also an output circuit generating an output current according to the phase difference between the calibration clock signal and the reference clock signal.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventor: Zhijiang Yang
  • Patent number: 10979277
    Abstract: In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy Mark Schmidl, Swaminathan Sankaran, Gerd Schuppener, Salvatore Luciano Finocchiaro, Siraj Akhtar, Tolga Dinc, Anand Ganesh Dabak, Baher Haroun
  • Patent number: 10979059
    Abstract: Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 13, 2021
    Assignee: Ciena Corporation
    Inventors: Soheyl Ziabakhsh Shalmani, Sadok Aouini, Matthew Mikkelsen, Hazem Beshara, Tingjun Wen, Mohammad Honarparvar, Naim Ben-Hamida
  • Patent number: 10972108
    Abstract: A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 6, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Miao Li, Li Sun, Hao Liu
  • Patent number: 10965297
    Abstract: Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 30, 2021
    Inventors: Wanghua Wu, Chih-Wei Yao
  • Patent number: 10944409
    Abstract: A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventor: Igal Kushnir
  • Patent number: 10931249
    Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 23, 2021
    Assignee: KANDOU LABS, S.A.
    Inventors: Suhas Rattan, Kiarash Gharibdoust
  • Patent number: 10931288
    Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 23, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Zhiyu Ru, Tim Yee He, Siavash Fallahi, Ali Nazemi, Delong Cui, Jun Cao
  • Patent number: 10928447
    Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10924125
    Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Mao-Hsuan Chou, Chih-Hsien Chang, Ruey-Bin Sheen
  • Patent number: 10911287
    Abstract: The present disclosure provides a transmitter and a corresponding method. The method includes: pre-processing a signal to be transmitter, the signals being across a plurality of sub-bands; filtering the signal to generate a universal-filtered orthogonal frequency division multiplexing (UF-OFDM) signal, where two or more sub-bands of the plurality of sub-bands are filtered by a common filter; and transmitting the generated UF-OFDM signal.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: February 2, 2021
    Assignee: Alcatel Lucent
    Inventors: Haijing Liu, He Wang
  • Patent number: 10911053
    Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Kapil Kumar Tyagi
  • Patent number: 10901453
    Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 26, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Sho Kamezawa, Tohru Kanno
  • Patent number: 10902412
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for data synchronization. One of the methods includes that a first terminal device establishes a data channel to a specified carrier through near field communication. The first terminal device obtains an account identifier of a first account and first streaming data corresponding to the first account through the data channel, where the account identifier of the first account and the first streaming data are stored in the specified carrier. The first terminal device determines second streaming data corresponding to a second account associated with the first account, and performs data synchronization between the first account and the second account based on the first streaming data and the second streaming data.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 26, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Fen Zhai, Chunlei Gu, Lingnan Shen, Ge Chen, Jie Qi, Huifeng Jin, Xuefu Song
  • Patent number: 10896719
    Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tyler J. Gomm
  • Patent number: 10892762
    Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventor: Stefan Tertinek
  • Patent number: 10887077
    Abstract: Embodiments are disclosed for timing recovery used in conjunction with a phase detector embedded in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The input signal encodes a plurality of bits in a number of amplitude levels. The method further includes using an analog to digital converter to generate a sampled signal based on the input signal. The method further includes using a first interpolation filter to filter the sampled signal. The method further includes using a second interpolation filter to filter the sampled signal. The method further includes using a first non-linear device to process an output of the first interpolation filter. The method further includes using a second non-linear device to process an output of the second interpolation filter.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Raanan Ivry
  • Patent number: 10879879
    Abstract: A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 29, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Florian Renneke, Jaafar Mejri
  • Patent number: 10878862
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 10873443
    Abstract: According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeremy Walker, Hiu Ming Lam, Mohammad Ranjbar
  • Patent number: 10873335
    Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 22, 2020
    Assignee: Apple Inc.
    Inventors: Cristian Marcu, Feng Zhao, Wei Deng, Chunwei Chang, Robert K. Kong, Saeed Chehrazi
  • Patent number: 10855067
    Abstract: AFCI and/or GFCI units (10) with onboard trip monitoring and/or wiring error monitoring circuit (100) with an opto-isolator (50) and a controller (60) in electrical communication with the opto-isolator (50). The controller (60) monitors the opto-isolator (50) to identify a TRIP or RESET state of the circuit (100) such as one associated with a receptacle and/or a wiring error of the unit (10), e.g., receptacle.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: December 1, 2020
    Assignee: Eaton Intelligent Power Limited
    Inventors: Saivaraprasad Murahari, Lili Du, Jianguo Chen
  • Patent number: 10848164
    Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 24, 2020
    Assignee: Ciena Corporation
    Inventors: Tingjun Wen, Sadok Aouini, Naim Ben-Hamida, Mahdi Parvizi, Matthew Mikkelsen
  • Patent number: 10848132
    Abstract: An apparatus and associated method are provided involving one or more registers configured to store a plurality of values including a first value corresponding with a first capacitance, and a second value corresponding with a second capacitance. Further included is a decoder configured to decode the values into corresponding capacitive settings. Also included is one or more capacitive elements in electrical communication with the decoder. Such one or more capacitive elements are configured to exhibit different capacitances, based on the capacitive settings. Also included is control circuitry in electrical communication with the decoder and the one or more registers. Such control circuitry is configured to control a transition of the capacitance of the one or more capacitive elements from the first capacitance to the second capacitance, by creating a plurality of additional values between the first value and the second value for being decoded by the decoder.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 24, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventor: Ping Shi