Abstract: Radar System The disclosure relates to a radar system having multiple radar transceiver modules, in which each module has a clock signal that is synchronised with a clock signal generated by a leader transceiver module.

Abstract: In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

Abstract: In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

Abstract: An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

Abstract: A frequency-detecting circuit, a DCC, and an electronic device. The frequency-detecting circuit includes a control-signal generating circuit generating a first control signal and a second control signal delayed relative to the first control signal; a charging and discharging path, under control of the second control signal, during a period with a pulse width when the second control signal is at a high level, performing the discharging process, and performing the charging process during another period when the second control signal is at a low level; and a control-voltage generating circuit, sampling values of a voltage of an output terminal of the charging and discharging path before the discharging process during a period with a pulse width when the first control signal is at the high level, to output a corresponding first voltage signal.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: Described herein is a fully-differential receiver for use with an implantable medical device (IMD) and configured to receive conducted communication signals that are transmitted by another IMD or an external device. The fully-differential receiver includes a fully-differential preamplifier, a fully-differential buffer, a first comparator, a second comparator, and an AC coupling network coupled between differential outputs of the fully-differential buffer and a coupled together differential pair of inputs of the first and second comparators. A differential pair of inputs of the fully-differential receiver comprise the differential pair of inputs of the fully-differential preamplifier, and a differential pair of outputs of the fully-differential receiver comprise a first output of the first comparator and a second output of the second comparator. In order to conserve power, the fully-differential receiver is selectively changed from operating in a first mode to operating in a second mode, and vice versa.

Abstract: Systems, methods and apparatus for wireless charging are disclosed. A charging device has a resonant circuit that includes a transmitting coil. The charging device also has a driver circuit configured to power the resonant circuit, a pulse width modulator and a controller configured to provide a control signal to the pulse width modulator the control signal configuring the pulse width to provide a modulated drive signal to the driver circuit. The pulse width modulator is configured to provide the modulated drive signal to the resonant circuit. The resonant circuit is configured to operate as a low-pass filter that blocks frequency components of the modulated drive signal that correspond to the reference signal. The driver circuit is configured to use the modulated drive signal to produce a charging current in the resonant circuit. The charging current causes power to be wirelessly transferred to a receiving device through the transmitting coil.

Abstract: A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.

Abstract: A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

Abstract: A bipolar TDC apparatus with a phase detection and signal switching circuitry and a phase error measurement circuitry. The phase detection and signal switching circuitry include a multiplexer and phase detector, together referred to as PD_MUX. The PD_MUX is used to handle the order of the two input signal phases of a TDC, or in other words, to enable TDC the bipolarity detection of the phase error. The apparatus detects first the polarity of the phase error and then prepares the right phase order when they arrive at the TDC measurement elements of the phase error measurement circuitry to ensure that always the earlier one starts the TDC and the later one triggers the measurement event. As such, the phase measurement circuitry (or measurement block) provides the phase error magnitude information, while the PD_MUX provides the sign—polarity information.

Abstract: A translation reference loop frequency synthesizer for generating an output signal with sub-Hz frequency steps over a full octave. The synthesizer has a phase lock loop circuit and a translation reference loop. The phase lock loop circuit generates a phase lock oscillator output signal based on a phase lock feedback signal and a phase lock reference signal. The translation reference loop generates the phase lock reference signal based on mixing a translation reference frequency signal and a translation reference loop divided signal. The translation reference loop includes a series of translation loop dividers for generating the translation reference loop divided signal by dividing a frequency of the phase lock oscillator output signal. The translation reference loop includes a translation reference frequency generator for generating the translation reference frequency signal.

Abstract: An electronic circuit including an output circuit capable of reducing breakage while satisfying the characteristics of an output signal is provided. For this purpose, the electronic circuit includes output signal generation elements 201 and 202 configured to generate an output signal, switches 203 and 204, and a voltage monitor circuit 205 configured to monitor a voltage applied to an output terminal 112. Here, the output signal generation elements 201 and 202 are connected to the output terminal 112 via the switches 203 and 204, and the voltage monitor circuit 205 is configured to be able to measure a voltage higher than a power supply voltage VDD connected to the output signal generation element 201 and controls the switches 203 and 204 so as to disconnect the output signal generation elements 201 and 202 and the output terminal 112 when the voltage of the output terminal 112 becomes equal to or higher than a predetermined value set higher than the power supply voltage VDD.

Abstract: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: A system having a micromechanical clocking system component a clocking system component. The system includes a micromechanical oscillation element, which is able to be induced to an oscillation with a natural frequency, and a first circuit, which generates from the natural frequency of the oscillation element a clock frequency which is pre-calibrated to a predefined setpoint clock frequency; a memory for the remaining deviation of the clock frequency from the setpoint clock frequency, the deviation having been individually determined for the clocking system component; and a processing unit which generates a reference time basis for at least a part of the system on the basis of the generated clock frequency and the stored deviation.

Abstract: Some example embodiments herein disclose an electronic apparatus and method for reducing or minimizing coarse lock time of Phase Locked Loop (PLL). The method includes controlling a voltage transient in the ABC current DAC of the PLL using the plurality of switchable voltage clamps, where the ABC current DAC includes a plurality of MOSFETs. Further, the method includes dividing the loop filter capacitor of the PLL into two segments to reduce the LPF settling time. Further, the method includes minimizing or reducing the coarse lock time of the PLL using the controlled voltage transients and the divided loop filter capacitor.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit and a phase control circuit. The phase detector samples input data signal according to first clock signals to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device generating a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device generating a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates second clock signals according to the frequency control signal. The phase control circuit controls phases of the second clock signals according to the phase control signal to generate the first clock signals.

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

Abstract: A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.

Abstract: A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

Abstract: A line card in a network box receives a SyncE clock signal and an input synchronization (SYNC) signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: For cross-channel spectral analysis of measurement data from multiple recording units with independent sampling clocks, a processing method corrects phase mismatch between the data received over the different channels. Blocks of sampled measurement data are buffered in a hardware logic circuit and timestamps are associated with successive blocks through a hardware interrupt to a GPS receiver of each recording unit. For each first channel data block, the block's starting point, a closest point in time in a data block of the second channel, and the starting point of that second channel data block are determined, using GPS timestamps associated with those data blocks, nominal sampling rate and block size. Phase correction based on the time offset between starting points of the pairs of data blocks and the interval between starting points of successive blocks is applied in the frequency domain after a time-to-frequency domain transformation. Multiple frames of phase-corrected spectra may then be averaged.

Abstract: Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, the phase-lock acceleration circuit includes a pulse width extraction control circuit and a current injection switch module; the control output terminal of the pulse width extraction control circuit is connected to the current injection control terminal of the current injection switch module, and the stepping current control terminal of the current injection switch module and the driving input terminal of the pulse width extraction control circuit are both connected to the preset control signal output end of a phase frequency detector for use in controlling, according to pulse width changes of signals outputted by the preset control signal output end, the current injection switch module to inject charges until the phases of a reference clock signal and feedback clock signal inputted by the phase frequency detector are synchronized.

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Abstract: A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.

Abstract: A transmitter/receiver (1) up-converts, using an LO signal as a local oscillation signal, an IF signal having a predetermined frequency band, thereby generating a transmission signal RFTX. Moreover, the transmitter/receiver (1) generates a (LO+IF)2 signal and a (LO?IF)2 signal based on the IF signal and the LO signal. Using the LO signal obtained by adding-up of the (LO+IF)2 signal and the (LO?IF)2 signal, a reception signal RFRX is down-converted. Thus, a local oscillation signal generation unit of a receiving unit is not necessary.

Abstract: A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

Abstract: A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Abstract: An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

Abstract: A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.

Abstract: A method for a slave device for calibrating an output timing for transmitting data to a master device is provided. The master and slave devices are communicatively coupled via an interface. The method includes: receiving, from the master device, one or more consecutive first signal edges indicating a synchronization event; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device and generated using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values of the master device for the one or more predetermined second signal edges; and adjusting the output timing based on a comparison of the one or more predetermined second signal edges and the one or more sampled values of the master device for the one or more predetermined second signal edges.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.

Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.