Phase Lock Loop Patents (Class 327/156)
  • Patent number: 11515880
    Abstract: A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: November 29, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Hiraku
  • Patent number: 11509450
    Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: November 22, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Paul Rowland
  • Patent number: 11509410
    Abstract: A method for a slave device for calibrating an output timing for transmitting data to a master device is provided. The master and slave devices are communicatively coupled via an interface. The method includes: receiving, from the master device, one or more consecutive first signal edges indicating a synchronization event; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device and generated using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values of the master device for the one or more predetermined second signal edges; and adjusting the output timing based on a comparison of the one or more predetermined second signal edges and the one or more sampled values of the master device for the one or more predetermined second signal edges.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: November 22, 2022
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Furtner
  • Patent number: 11500336
    Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 15, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Yogesh Darwhekar, Subhashish Mukherjee, Narala Raghavendra Reddy
  • Patent number: 11451234
    Abstract: A delay locked loop (DLL) circuit that includes a delay line, a pattern injecting circuit, a pattern detecting circuit and a counter is introduced. The delay line may align a phase of a reference clock signal with a phase of a feedback clock signal. The pattern injecting circuit injects a predetermined pattern to the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detecting circuit detects the predetermined pattern in the feedback clock signal. The counter determines a delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method of measuring a delay of the DLL circuit is also introduced.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: September 20, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: John Austin, Joseph Iadanza, Fran Keyser
  • Patent number: 11437999
    Abstract: A phase locked loop (PLL) comprises: a reference oscillator to generate a reference clock having a reference frequency; a voltage controlled oscillator (VCO) to generate a VCO clock having a VCO frequency controlled in response to a control signal applied to the VCO; a first integrator to integrate the reference frequency into a first ramp slope; a second integrator to integrate the VCO frequency into a second ramp slope; and a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope and that is conveyed by the control signal, such that the control signal is configured to drive the VCO frequency toward the reference frequency to minimize the slope difference and frequency lock the VCO frequency to the reference frequency.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 6, 2022
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Tzi-Wei Lee
  • Patent number: 11429141
    Abstract: A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 30, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventors: Tomohiro Sasa, Hajime Tsukahara
  • Patent number: 11418198
    Abstract: In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 16, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Farshid Nowshadi, John Bruce
  • Patent number: 11417371
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11418201
    Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: August 16, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Debapriya Sahu, Rittu Sachdev
  • Patent number: 11387834
    Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: July 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pranav Kumar, Abhrarup Barman Roy, Apoorva Bhatia, Arpan Sureshbhai Thakkar, Jagdish Chand
  • Patent number: 11381248
    Abstract: A phase detection method and apparatus, and a storage medium and an electronic apparatus are provided. A sampling operation is performed on a clock signal to be detected to obtain binary sequences. Phase intervals of the clock signal to be detected in initial sampling periods are determined, according to the binary sequences, as first phase intervals. Based on a reference phase interval in the first phase intervals, a standardization operation is performed on other phase intervals in the first phase intervals to obtain second phase intervals, wherein the reference phase interval is a phase interval determined within a first sampling period after the sampling operation is triggered, and the other phase intervals are phase intervals determined within sampling periods following the first sampling period. The second phase intervals are converged, and phase information of the clock signal to be detected is obtained according to the converged second phase intervals.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 5, 2022
    Assignee: ZTE CORPORATION
    Inventors: Rui Pang, Boming Wang, Qin Yang
  • Patent number: 11356109
    Abstract: A frequency synthesizer includes a clock multiplier unit configured to receive a first clock and output a second clock in accordance with a multiplication factor; a divide-by-three circuit configured to receive the second clock and output a third clock; a first divide-by-two circuit configured to receive the second clock and output a fourth clock; a second divide-by-two circuit configured to receive the fourth clock and output a fifth clock; a first multiplexer configured to receive the third clock and the fourth clock and output a seventh clock in accordance with a first selection signal; a second multiplexer configured to receive the third clock and the fifth clock and output an eighth clock in accordance with a second selection signal; and a mixer configured to receive the seventh clock and the eighth clock and output an output clock.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 7, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 11356104
    Abstract: A phase locked loop circuit includes a phase comparator that compares phases of a reference signal through a first frequency divider and a local signal through a second frequency divider to output a phase comparison signal; a loop filter that smooths the phase comparison signal to output the control voltage signal; a controller that sets frequency division ratios of the first and the second frequency dividers; a free-running voltage generator that generates a free-running voltage signal of the voltage control oscillator; a measurement circuit that measures a voltage of the control voltage signal; a storage circuit that stores therein the voltage of the control voltage signal; and a low-pass filter that transmits, to the voltage control oscillator, a corrected free-running voltage signal based on a free-running voltage correction value calculated by the free-running voltage generator based on the control voltage signal before the frequency division ratios are changed.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 7, 2022
    Assignee: JVCKENWOOD Corporation
    Inventor: Ryo Kuboshima
  • Patent number: 11343670
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for transmitting, by a first device, a transmission signal that includes a carrier signal modulated with a TM signal. Receiving a response signal from a second device in response to the transmission signal. Determining, whether the response signal includes the TM signal.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 24, 2022
    Assignee: TM IP HOLDINGS, LLC
    Inventors: Richard C. Gerdes, Daniel L. Hodges, Quinn Colin McIntosh
  • Patent number: 11342926
    Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 24, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: James D. Barnette, William Anker, Xue-Mei Gong
  • Patent number: 11336288
    Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.
    Type: Grant
    Filed: May 9, 2021
    Date of Patent: May 17, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Hung-Chuan Pai, Marco Zanuso
  • Patent number: 11329653
    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 10, 2022
    Assignee: Space Exploration Technologies Corp.
    Inventors: David Francois Jacquet, Mostafa Ghazali, Masoud Kahrizi, Andras Tantos
  • Patent number: 11287534
    Abstract: Apparatus and methods determine the rotational position of a spinning object. A satellite positioning system can be used to determine the spatial position of an object, which in turn can be used to guide the object. However, when the object is spinning, such as an artillery shell, then the rotational orientation should be known in order to properly actuate the control surfaces, such as fins, which will also be spinning.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 29, 2022
    Assignee: Interstate Electronics Corporation
    Inventors: Steven B. Alexander, Richard Redhead
  • Patent number: 11290117
    Abstract: A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 29, 2022
    Inventor: Joseph Frank Kosednar, Jr.
  • Patent number: 11290118
    Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 29, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Theertham, Jagdish Chand, Yogesh Darwhekar, Subhashish Mukherjee, Jayawardan Janardhanan, Uday Kiran Meda, Arpan Sureshbhai Thakkar, Apoorva Bhatia, Pranav Kumar
  • Patent number: 11277096
    Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: March 15, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Gagan Midha, Anurup Mitra, Kallol Chatterjee
  • Patent number: 11277140
    Abstract: In certain aspects, a sampler includes a sampling capacitor, a precharge switch coupled to the sampling capacitor, one or more discharge circuits coupled to the sampling capacitor, and a reference-voltage circuit coupled to the sampling capacitor. The reference-voltage circuit is configured to generate a reference voltage based on a supply voltage, and generate a voltage difference between a voltage on the sampling capacitor and the reference voltage.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Dongmin Park, Alvin Siu-Chi Li, Masoud Moslehi Bajestan, Yiwu Tang
  • Patent number: 11271584
    Abstract: Disclosed is an integrated circuit, which includes a DTC block including DTCs, receiving a first reference signal and a first division signal, and outputting a second reference signal and a second division signal based on the first reference signal, the first division signal, and control codes, a TDC comparing phases of the second reference signal and the second division signal and outputting a comparison signal, a digital loop filter filtering the comparison signal, an oscillator generating an output signal based on the filtered comparison signal, a delta-sigma modulator outputting a first signal and a quantized noise signal based on first and second division ratio signals, a divider dividing a frequency of the output signal based on the first signal and outputting the first division signal, and a probability modulator generating the control codes based on the quantized noise signal. Probability density functions of the control codes are time-invariant.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 8, 2022
    Assignee: Korean Advanced Institute of Science and Technology
    Inventors: Jaehyouk Choi, Taeho Seong, Yongsun Lee, Chanwoong Hwang, Hangi Park
  • Patent number: 11264998
    Abstract: A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: March 1, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ravinder Reddy Rachala
  • Patent number: 11256285
    Abstract: A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Young Suk Seo, Gyu Tae Park
  • Patent number: 11245405
    Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 8, 2022
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Laurent Truphemus, Christophe Eva
  • Patent number: 11245263
    Abstract: The present application proposes a method of locating oscillation sources of wind power integrated system based on energy spectrums. The method include: collecting information of voltage and current at the terminal of each generator and obtaining a dynamic energy curve of each generator over time; choosing the generators whose curve shows an upward trend in the dynamic energy over time curve into alternative generators; obtaining and processing energy spectrums of synchronous generator, DFIG with PLL, and/or an analogical energy spectrum of DFIG with virtual inertia among the alternative generators; selecting generator with maximum proportion of dominant oscillation mode as an oscillation source reference generator; and calculating the similarity coefficients between energy spectrums of each remaining candidate generator and the oscillation source reference generator, determining the oscillation source generators.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 8, 2022
    Assignee: North China Electric Power University
    Inventors: Jing Ma, Dong Zhao, Yuanpei Gu, Yaqi Shen
  • Patent number: 11218155
    Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 4, 2022
    Assignee: Ciena Corporation
    Inventors: Tingjun Wen, Sadok Aouini, Naim Ben-Hamida, Mahdi Parvizi, Matthew Mikkelsen
  • Patent number: 11216240
    Abstract: Embodiments provide a MEMS microphone, comprising an output interface for providing an output signal of the MEMS microphone, and comprising a memory, wherein the output interface is configured to provide, in a normal mode of operation, a microphone signal as the output signal of the MEMS microphone, and wherein the output interface is configured to provide, in an initialization mode of operation, a data signal as the output signal of the MEMS microphone, wherein the data signal carries an information stored in the memory.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 4, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: David Andrew Russell, Florian Brame, Dietmar Straeussnigg
  • Patent number: 11209499
    Abstract: The present invention provides a distribution board having a main breaker and a plurality of branch breakers, the distribution board being wired to branch power supplied to the main breaker into each branch breaker, the distribution board including: a plurality of noise detection sections configured to correspond to the respective branch breakers one-to-one and each configured to output a detection signal based on a noise component of not less than a predetermined frequency generated on a secondary side of each branch breaker; and processor configured to separately receive the detection signal output from each noise detection section and determine whether the detection signal is high frequency noise at a threshold or more.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: December 28, 2021
    Assignee: Nitto Kogyo Corporation
    Inventors: Atsushi Miyamoto, Hiroyuki Ito
  • Patent number: 11196424
    Abstract: An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 7, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jose Luis Flores, Venkateswar Reddy Kowkutla, Ramakrishnan Venkatasubramanian
  • Patent number: 11188117
    Abstract: An apparatus is provided for low latency adaptive clocking, the apparatus comprises: a first power supply rail to provide a first power; a second power supply rail to provide a second power; a third power supply rail to provide a third power; a voltage divider coupled to the first, second, and third power supply rails; a bias generator coupled to voltage divider and the third power supply rail; an oscillator coupled to the bias generator and the first supply rail; and a clock distribution network to provide an output of the oscillator to one or more logics, wherein the clock distribution network is coupled to the second power supply rail.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Praveen Mosalikanti, Nasser Kurd
  • Patent number: 11184010
    Abstract: A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 23, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yan-Guei Chen, Hsin-Yu Lue, Liang-Wei Huang, Hui-Min Huang
  • Patent number: 11183993
    Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 23, 2021
    Assignee: Intel Corporation
    Inventors: Hundo Shin, Kameran Azadet, Martin Clara, Daniel Gruber
  • Patent number: 11176299
    Abstract: An approach for detecting potential failures and sensitivities, based on preliminary verification of timing circuits which includes feedback and combinatorial loops for is disclosed. The approach comprises relating timing events by algebraic equations, breaking loops, and feedbacks by backward reference, and then propagate signals through time and netlist.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Israel A. Wagner, Noam Jungmann
  • Patent number: 11165286
    Abstract: A data demodulating circuit includes a sensing circuit sensing a power signal applied to a coil at first and second times, and outputting an analog value representing a difference in voltage of the power signal at the first and second times. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to produce a digital code. A compensation circuit, over a period of time, compares a present value of the digital code to a first value of the digital code during the period, and subtracts a given value from the present value of the digital code if the present value is greater than the first value but add the given value to the present value of the digital code if the present value is less than the first value. An accumulator accumulates output of the compensation circuit, and a filter filters output of the accumulator.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 2, 2021
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Teerasak Lee, Chee Weng Cheong, Yannick Guedon, Eng Jye Ng
  • Patent number: 11159085
    Abstract: An integrated circuit that drives a switching device provided between a first line on a ground side and a second line on a power supply side, when a power supply voltage is applied between a first input terminal connected with a first capacitor and a second input terminal, the first capacitor having one end grounded and another end connected to the first input terminal, the integrated circuit includes: a first terminal connected to a circuit element, the circuit element having one end grounded and another end connected to the first terminal; and a drive circuit that changes a voltage at the first terminal to one logic level when a drive signal of the switching device changes to the one logic level, and changes the voltage at the first terminal to another logic level when the drive signal changes to the other logic level.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 26, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryuji Yamada, Ryuunosuke Araumi, Takato Sugawara
  • Patent number: 11144088
    Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Jagannadha Rao V. V. V. Rapeta, Mikal Hunsaker, Ronald Swartz, Robert Fulton, L. Mark Elzinga, Young Min Park, David R. Mulvihill
  • Patent number: 11146274
    Abstract: An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 12, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Mikio Shiraishi
  • Patent number: 11146111
    Abstract: A power receiver includes: a secondary-side resonant coil that includes a resonant coil circuit and receives power from a primary-side resonant coil; a capacitor inserted into the resonant coil circuit; a series circuit including a first switch and a second switch; a first rectifying element having a first rectification direction; a second rectifying element having a second rectification direction; a detection circuit that detects a voltage or a current; a binarization processing circuit that outputs a rectangular wave obtained by binarizing the voltage or the current; a rectangular wave detection circuit that detects a rising or falling timing and a cycle of the rectangular wave; a reference clock generation circuit that generates a reference clock based on the rising or falling timing and the cycle; and a control circuit that generates a control clock used to switch on and off by adjusting a phase or a duty ratio.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 12, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Shimokawa, Hirotaka Oshima
  • Patent number: 11139818
    Abstract: A fast-locking phase-locked loop (PLL) and an associated fast-locking method thereof are provided. The fast-locking PLL may include a gear-shifting loop filter, which is configured to have a dynamic bandwidth. The gear-shifting loop filter may include a resistor set and a capacitor set coupled to the resistor set, where the resistor set is configured to have a dynamic resistance, and the capacitor set is configured to have a dynamic capacitance. More particularly, the dynamic resistance is switched from a first resistance to a second resistance and the dynamic capacitance is switched from a first capacitance to a second capacitance, to make the dynamic bandwidth be switched from a first bandwidth to a second bandwidth.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 5, 2021
    Assignee: MEDIATEK INC.
    Inventors: Po-Chun Huang, Yu-Li Hsueh, Chao-Ching Hung
  • Patent number: 11133806
    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.
    Type: Grant
    Filed: April 26, 2020
    Date of Patent: September 28, 2021
    Assignee: Space Exploration Technologies Corp.
    Inventors: David Francois Jacquet, Mostafa Ghazali, Masoud Kahrizi, Andras Tantos
  • Patent number: 11128304
    Abstract: A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 21, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yun-Sheng Yao, Shen-Iuan Liu, Yen-Long Lee, Peng-Yu Chen, Chih-Hao Huang, Yao-Hung Kuo
  • Patent number: 11115178
    Abstract: A clock and data recovery device includes a phase detector circuitry, an analog modulation circuitry, a serial-to-parallel converter circuit, a digital modulation circuitry, and an oscillator circuit. The phase detector circuitry detects a data signal according to first and second clock signals to generate an up signal and a down signal. The analog modulation circuitry generates a first adjustment signal according to the up signal and the down signal. The serial-to-parallel converter circuit generates a first control signal according to the up signal, and to generate a second control signal according to the down signal. The digital modulation circuitry generates a digital code according to the first and the second control signals, and to generate a second adjustment signal according to the digital code. The oscillator circuit generates the first and the second clock signals according to the first adjustment signal and the second adjustment signal.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Jia-Ning Lou
  • Patent number: 11115038
    Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Laurent Truphemus, Christophe Eva
  • Patent number: 11108400
    Abstract: An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 31, 2021
    Assignee: Renesas Electronics America Inc.
    Inventor: Greg Armstrong
  • Patent number: 11092994
    Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Gi Moon Hong, Kyu Dong Hwang
  • Patent number: 11094354
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11095296
    Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 17, 2021
    Assignee: INNOPHASE, INC.
    Inventors: Sara Munoz Hermoso, Per Konradsson, Yang Xu