Phase Lock Loop Patents (Class 327/156)
  • Patent number: 10848132
    Abstract: An apparatus and associated method are provided involving one or more registers configured to store a plurality of values including a first value corresponding with a first capacitance, and a second value corresponding with a second capacitance. Further included is a decoder configured to decode the values into corresponding capacitive settings. Also included is one or more capacitive elements in electrical communication with the decoder. Such one or more capacitive elements are configured to exhibit different capacitances, based on the capacitive settings. Also included is control circuitry in electrical communication with the decoder and the one or more registers. Such control circuitry is configured to control a transition of the capacitance of the one or more capacitive elements from the first capacitance to the second capacitance, by creating a plurality of additional values between the first value and the second value for being decoded by the decoder.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 24, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventor: Ping Shi
  • Patent number: 10848164
    Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 24, 2020
    Assignee: Ciena Corporation
    Inventors: Tingjun Wen, Sadok Aouini, Naim Ben-Hamida, Mahdi Parvizi, Matthew Mikkelsen
  • Patent number: 10840887
    Abstract: In accordance with an embodiment, a method of operating an RF system includes filtering a wideband RF signal using an adjustable center frequency bandpass filter to produce a filtered RF signal; amplifying the filtered RF signal to produce an amplified RF signal; and band stop filtering the amplified RF signal to produce a band stopped RF signal.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: November 17, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Stefan Helmut Schmalzl, Peter Pfann, Ruediger Bauder, Hans-Joerg Timme
  • Patent number: 10840916
    Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 17, 2020
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Ofir Degani
  • Patent number: 10833682
    Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 10, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Timothy A. Monk, Douglas F. Pastorello
  • Patent number: 10823693
    Abstract: In an embodiment, an integrated circuit includes: a switched capacitor coupled between a supply voltage node and a divider node, where a thermistor external to the integrated circuit is to couple to the divider node; an analog-to-digital converter (ADC) coupled to the divider node to receive a voltage at the divider node and generate a digital value based thereon; and a controller coupled to the ADC to determine a temperature associated with the thermistor based at least in part on the digital value.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: November 3, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Euisoo Yoo, Thomas Edward Voor, John M. Khoury
  • Patent number: 10819358
    Abstract: Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: October 27, 2020
    Assignee: NXP B.V.
    Inventor: Sebastien Darfeuille
  • Patent number: 10819357
    Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventors: Da In Im, Young Suk Seo
  • Patent number: 10804907
    Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungjin Kim, Jihyun Kim, Taeik Kim
  • Patent number: 10804908
    Abstract: Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel IP Corporation
    Inventors: Thomas Mayer, Christian Wicpalek
  • Patent number: 10802535
    Abstract: A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Koji Ito
  • Patent number: 10804914
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 13, 2020
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Patent number: 10804909
    Abstract: A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae-Pyeong Kim
  • Patent number: 10797855
    Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 6, 2020
    Assignee: INTEL CORPORATION
    Inventors: Amir Laufer, Itamar Levin, Kevan A. Lillie
  • Patent number: 10797709
    Abstract: Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 6, 2020
    Assignee: Analog Bits Inc.
    Inventors: Alan C. Rogers, Raghunand Bhagwan
  • Patent number: 10790835
    Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 29, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Staffan Ek, Tony Påhlsson, Henrik Sjöland
  • Patent number: 10778164
    Abstract: An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 15, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Wei Liang
  • Patent number: 10771068
    Abstract: A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 8, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Michael W. Harper, Michael B. Spear, Gary A. Van Huben
  • Patent number: 10771073
    Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics International N.V.
    Inventor: Nitin Gupta
  • Patent number: 10763841
    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Amit Rane
  • Patent number: 10761822
    Abstract: Provided are systems and methods for generating program code for an integrated circuit, where instructions in the code synchronize computation engines that support non-blocking instructions. In various examples, a computing device can receiving an input data set including operations to be performed by an integrated circuit device and dependencies between the operations. The input data set can include a non-blocking instruction, and an operation that requires that the non-blocking instruction be completed. The computing device can generate instructions for performing the operation including a particular instruction to wait for a value to be set in a register of the integrated circuit device. The computing device can further generate program code including the non-blocking instruction and the instructions for performing the operation, wherein the non-blocking instruction is configured to set the value in the register.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Drazen Borkovic, Jindrich Zejda, Taemin Kim, Ron Diamant
  • Patent number: 10749664
    Abstract: An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: August 18, 2020
    Assignee: Ambarella International LP
    Inventors: Xuan Wang, Jingxiao Li, Tianwei Liu, Yuan-Fu Lin
  • Patent number: 10739729
    Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Tarun Mahajan, Dheeraj Shetty, Ramnarayanan Muthukaruppan
  • Patent number: 10715151
    Abstract: A coarse tuning synthesizer for wireless communication includes a digital control unit, a digital-to-analog converter, and a comparator. The digital control unit includes an output node coupled to a first input node of a VCO (voltage controlled oscillator). The digital-to-analog converter includes a first node coupled to the first input node of the VCO. The comparator includes an output node coupled to an input node of the digital control unit. The comparator also includes a first input node coupled to a second node of the digital-to-analog converter and a second input node coupled to an output node of the VCO.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yuehai Jin, Xinhua Chen
  • Patent number: 10715155
    Abstract: Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: July 14, 2020
    Assignee: Ciena Corporation
    Inventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida
  • Patent number: 10707883
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: July 7, 2020
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Patent number: 10692443
    Abstract: A synchronous backlight device and an operation method thereof are provided. The synchronous backlight device includes a pulse width modulation (PWM) control circuit and a backlight driving circuit. The PWM control circuit receives the video sync information from a video processing circuit and generates a PWM control signal. Wherein, the video sync information defines a plurality of video frame periods, the PWM control circuit at least divides each of the video frame periods into a first period and a second period, the lengths of the first periods of the video frame periods are equal to one another. The frequency of the PWM control signal in the first periods is different from the frequency of the PWM control signal in the second periods. The backlight driving circuit drives the backlight source of a display panel in accordance with the PWM control signal.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 23, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chung-Wen Wu, Wen-Chi Lin, Sih-Ting Wang
  • Patent number: 10685686
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Patent number: 10680626
    Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 9, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Shih-Chi Shen, Chi-Hsueh Wang, Hsin-Hung Chen
  • Patent number: 10680623
    Abstract: A local oscillator (LO) distribution system is described. The LO system includes a plurality of phase-locked loop (PLL) modules coupled to each other in a one-way, circulant coupling topology. Each PLL module receives a reference clock signal and outputs an output LO signal. Each PLL module provides a local LO signal to an adjacent downstream PLL module, where the local LO signal is a frequency divided version of the output LO signal. Each PLL module receives an adjacent LO signal from the adjacent upstream PLL module. The phase of the output LO signal is made to be coherent with the phase of the reference clock signal and the phase of the adjacent LO signal, using a feedback loop.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: June 9, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Andrei Buliga
  • Patent number: 10665177
    Abstract: A circuit arrangement for controlling a backlight source and an operation method are provided. The circuit arrangement includes a generator. The generator receives a sync signal and generates a pulse width modulation signal synchronous with the sync signal to control the backlight source. The sync signal indicates a frequency of a video including a series of image frames. The sync signal includes a sync period corresponding to a frame of the video. The pulse width modulation signal includes a first waveform pattern in a first sub-period of the sync period and a second waveform pattern in a second sub-period of the sync period. Each of the first waveform pattern and the second waveform pattern includes at least one active pulse. The first waveform pattern is substantially identical to the second waveform pattern.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 26, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chung-Wen Wu, Wen-Chi Lin, Jiun-Yi Lin
  • Patent number: 10666267
    Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao Chieh Li, Chia-Chun Liao, Min-Shueh Yuan, Robert Bogdan Staszewski
  • Patent number: 10656441
    Abstract: An optical modulator apparatus may include a plurality of segment drivers, each segment driver having a unique offset voltage and driving but a portion or a segment of an electro-optical modulator. A modulating electrical signal may be applied to the segment drivers via a plurality of electrical delays. Parameters of the segment drivers may be selected so as to approximate a pre-defined transfer function, which may include a linear or a non-linear transfer function.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Ran Ding, Thomas Wetteland Baehr-Jones, Peter D. Magill, Michael J. Hochberg, Alexander Rylyakov
  • Patent number: 10659061
    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
  • Patent number: 10651054
    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 12, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 10637397
    Abstract: Method and apparatus for determining a clock frequency for an electronic processor are provided. One embodiment provides a clock generator for determining a clock frequency for an electronic processor and providing a clock signal to the electronic processor. The clock generator includes a crystal oscillator producing a reference signal and a phase locked loop receiving the reference signal and configured to generate the clock signal based on the reference signal. The clock generator also includes a tuning logic controller electrically coupled to the phase locked loop. The tuning logic controller is configured to program the phase locked loop to a first frequency and determine an integrated circuit process corner of the electronic processor. The tuning logic controller is also configured to determine a second frequency based on the integrated circuit process corner and program the phase locked loop to the second frequency.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 28, 2020
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Mark Rozental, Claudine Tordjman, Richard S. Young, Uri Vallach
  • Patent number: 10635130
    Abstract: Devices, methods, and systems are described that generate process, voltage and temperature tolerant clock generators, which can be used in low power and low cost applications. The clock generators eliminate the need for a crystal oscillator, are simple to implement, and can use a single frequency calibration step to initially tune the frequency to a reference frequency value, and to allow the clock generator to operate in the presence of process, voltage or temperature variations. One example clock circuit includes a voltage-controlled oscillator that provides a clock output, a gain circuit to receive a reference voltage as one input and a changeable voltage on another input. The clock circuit also includes a frequency-to-voltage convertor circuit that receives a reference current and produces the changeable voltage provided to gain circuit, while a ratio of the reference voltage to the reference current is constant.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 28, 2020
    Assignee: Atlazo, Inc.
    Inventor: Masoud Ensafdaran
  • Patent number: 10637696
    Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 28, 2020
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
  • Patent number: 10623010
    Abstract: An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Wing-Fai Loke, Chih-Wei Yao
  • Patent number: 10623035
    Abstract: The present disclosure relates to a wireless communication network node comprising an antenna arrangement, a transmitter arrangement that is arranged to transmit output signals of a first frequency band, and a receiver arrangement that is arranged to receive input signals of a second frequency band. The node further comprises a first power distribution device that is arranged to distribute power between said antenna arrangement and both of said transmitter arrangement and said receiver arrangement. The node further comprises an oscillator that is arranged to supply an additional signal of a third frequency band that is added to the output signals. The frequencies comprised in the third frequency band exceed the frequencies comprised in the first frequency band. The node further comprises a receiver filter that is arranged to prevent the additional signal to reach the receiver arrangement.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: April 14, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Bo Granstam
  • Patent number: 10607672
    Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soong-Man Shin, Hyungjin Kim, YoungWóok Kim
  • Patent number: 10598726
    Abstract: A self-test circuit and a self-test method for a comparator are provided. A first output terminal of the comparator is coupled to an input terminal of a first inverter, and a second output terminal of the comparator is coupled to an input terminal of a second inverter. The comparator operates in a reset phase or a comparison phase according to a clock. The self-test method includes steps of: coupling the first output terminal and the second output terminal so that the comparator enters a test mode; and in the test mode, controlling the comparator to operate in the reset phase or the comparison phase according to the clock. In the test mode, the first output terminal and the second output terminal have substantially the same voltage.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 24, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Liang-Huan Lei, Shih-Hsiung Huang, Chih-Lung Chen
  • Patent number: 10594305
    Abstract: Provided is an oscillator arranged to output an oscillation signal of an oscillation frequency having an increasing and decreasing component that increases and decreases in one period, and an offset component for each period.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Rohm Co., Ltd.
    Inventor: Shun Fukushima
  • Patent number: 10594329
    Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 17, 2020
    Assignee: Si-Ware Systems S.A.E.
    Inventor: Ahmed Elkholy
  • Patent number: 10585449
    Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 10, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10587274
    Abstract: Various embodiments a PLL-based clock unit is disclosed. An exemplary clock unit includes a PLL, a low-jitter XO to provide a low-jitter input clock and a low-cost TCXO to provide a low-temperature-drift clock. The clock unit additionally includes a holdover module coupled to the PLL and configured to receive the low-jitter input clock and a reference input clock; record a relationship between the low-jitter input clock and the reference input clock during a normal operation mode; and output the recorded relationship to the PLL as a control signal during a holdover operation mode when the reference input clock is unavailable. This clock unit additionally includes a statistical module to compute a relationship between the low-jitter input clock and the low-temperature-drift clock; and a control module to dynamically adjust the output of the holdover module based on the determined relationship so that the output clock of the clock unit maintains both low-jitter and low-temperature-drift characteristics.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 10, 2020
    Inventors: Deyi Pi, Chang Liu, Jinliang Liu
  • Patent number: 10566958
    Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 18, 2020
    Assignee: NVIDIA Corp.
    Inventors: Sanquan Song, Olakanmi Oluwole, John Poulton, Carl Thomas Gray
  • Patent number: 10558238
    Abstract: The present disclosure relates to a frequency source with an adjustable frequency, and related system, method and electronic device, in particular to a frequency source with an adjustable frequency comprising an input terminal for receiving an input voltage signal, wherein the frequency source identifies a frequency of the input voltage signal. The present disclosure relates to a system comprising the frequency source, a method for identifying the frequency of the voltage signal, and an electronic device comprising the frequency source.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: February 11, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liming Xiu
  • Patent number: 10551867
    Abstract: The invention relates to a device for generating a plurality of clock signals or high-frequency signals. The devices includes a reference signal generator, which is connected to an oscillator and generates at its output a reference signal with a reference frequency fx. The device also includes at least one signal processor, for example, a DDS, which is connected to the reference frequency generator via a first signal line and to which the reference signal with the reference frequency fx is supplied, and which is configured to generate an output signal having a frequency less than fx.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 4, 2020
    Assignee: TRUMPF Huettinger GmbH + Co. KG
    Inventors: Andre Grede, Daniel Gruner, Armin Bannwarth, Christian Bock, Christoph Hofstetter, Alberto Pena Vidal, Nikolai Schwerg, Manuel vor dem Brocke, Markus Winterhalter
  • Patent number: 10547439
    Abstract: Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 28, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jian Liu, Chi-Kung Kuan