Abstract: A semiconductor device has a current controlled oscillation circuit configured to generate an oscillation clock in response to a current supplied, a first circuit configured to output a first signal when a phase of the oscillation clock is later than a phase of reception data, and to output a second signal when a phase of the oscillation clock is earlier than a phase of the reception data, and a current control circuit configured to control a current to be supplied to the current controlled oscillation circuit such that the number of times of output of the first signal from the first circuit matches the number of times of output of the second signal from the first circuit.

Abstract: Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

Abstract: A system having a micromechanical clocking system component a clocking system component. The system includes a micromechanical oscillation element, which is able to be induced to an oscillation with a natural frequency, and a first circuit, which generates from the natural frequency of the oscillation element a clock frequency which is pre-calibrated to a predefined setpoint clock frequency; a memory for the remaining deviation of the clock frequency from the setpoint clock frequency, the deviation having been individually determined for the clocking system component; and a processing unit which generates a reference time basis for at least a part of the system on the basis of the generated clock frequency and the stored deviation.

Abstract: Some example embodiments herein disclose an electronic apparatus and method for reducing or minimizing coarse lock time of Phase Locked Loop (PLL). The method includes controlling a voltage transient in the ABC current DAC of the PLL using the plurality of switchable voltage clamps, where the ABC current DAC includes a plurality of MOSFETs. Further, the method includes dividing the loop filter capacitor of the PLL into two segments to reduce the LPF settling time. Further, the method includes minimizing or reducing the coarse lock time of the PLL using the controlled voltage transients and the divided loop filter capacitor.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

Abstract: A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit and a phase control circuit. The phase detector samples input data signal according to first clock signals to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device generating a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device generating a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates second clock signals according to the frequency control signal. The phase control circuit controls phases of the second clock signals according to the phase control signal to generate the first clock signals.

Abstract: A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.

Abstract: A shared bus time interleaves 1 PPS signal and control and coordination information between a primary timing source and line cards that need to be synchronized using the 1 PPS signals. The shared bus utilizes 1 second frames divided into time slots. The 1 PPS signals are interleaved at predetermined locations in the frame so the delays introduced by interleaving the 1 PPS data in time can be precisely removed. While the bus is not being used for 1 PPS signals, the bus is available to send control and coordination information between the line cards and the primary timing source, avoiding the use of another system and increasing utilization of an available communication path.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter configured to count a number of pulses generated by the free-running oscillator and logic configured to compare the number of pulses with an expected number of pulses (corresponding to a target frequency) to determine a difference value and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse, to trigger an update of the number of pulses to be compared.

Abstract: A line card in a network box receives a SyncE clock signal and an input synchronization (SYNC) signal. A phase-lock loop (PLL) in the line card receives the SyncE clock signal as a reference clock signal and generates an output SyncE clock signal. The line card regenerates a SYSCLK signal using a digitally controlled oscillator that receives a timing signal from the SyncE PLL and receives a control signal from control logic on the line card. The frequency and phase information contained in the SYNC signal is utilized to control the DCO. The SYSCLK signal is divided to generate an output SYNC signal. The control logic uses the time difference between the input SYNC signal and a SYNC feedback signal to control the DCO to provide a zero delay SYNC output signal. The output SYNC signal and the SYSCLK signal control a time of day counter in the line card.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: For cross-channel spectral analysis of measurement data from multiple recording units with independent sampling clocks, a processing method corrects phase mismatch between the data received over the different channels. Blocks of sampled measurement data are buffered in a hardware logic circuit and timestamps are associated with successive blocks through a hardware interrupt to a GPS receiver of each recording unit. For each first channel data block, the block's starting point, a closest point in time in a data block of the second channel, and the starting point of that second channel data block are determined, using GPS timestamps associated with those data blocks, nominal sampling rate and block size. Phase correction based on the time offset between starting points of the pairs of data blocks and the interval between starting points of successive blocks is applied in the frequency domain after a time-to-frequency domain transformation. Multiple frames of phase-corrected spectra may then be averaged.

Abstract: Disclosed are a control signal pulse width extraction-based phase-locked acceleration circuit and a phase-locked loop system, the phase-lock acceleration circuit includes a pulse width extraction control circuit and a current injection switch module; the control output terminal of the pulse width extraction control circuit is connected to the current injection control terminal of the current injection switch module, and the stepping current control terminal of the current injection switch module and the driving input terminal of the pulse width extraction control circuit are both connected to the preset control signal output end of a phase frequency detector for use in controlling, according to pulse width changes of signals outputted by the preset control signal output end, the current injection switch module to inject charges until the phases of a reference clock signal and feedback clock signal inputted by the phase frequency detector are synchronized.

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Abstract: A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.

Abstract: A transmitter/receiver (1) up-converts, using an LO signal as a local oscillation signal, an IF signal having a predetermined frequency band, thereby generating a transmission signal RFTX. Moreover, the transmitter/receiver (1) generates a (LO+IF)2 signal and a (LO?IF)2 signal based on the IF signal and the LO signal. Using the LO signal obtained by adding-up of the (LO+IF)2 signal and the (LO?IF)2 signal, a reception signal RFRX is down-converted. Thus, a local oscillation signal generation unit of a receiving unit is not necessary.

Abstract: A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

Abstract: A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.

Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Abstract: An oscillating signal generator circuit includes an oscillator circuit, a feedback circuit, and a voltage regulator circuit. The oscillator circuit is configured to generate a first and second oscillating signal at a first and second output terminal according to a first reference voltage. The first and second oscillating signals are a differential pair of signals. The oscillator circuit includes a common mode sensing circuit coupled between the first and second output terminals. The common mode sensing circuit is configured to sense a common mode component of the first and second oscillating signals so as to generate a sense voltage. The feedback circuit, coupled to the common mode sensing circuit, is configured to generate a feedback voltage according to the sense voltage. The voltage regulator circuit is coupled to the oscillator circuit and the feedback circuit, and configured to regulate a supply voltage so as to generate the first reference voltage.

Abstract: The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

Abstract: A semiconductor device includes a clock generating circuit and a jitter measurement circuit. The clock generating circuit is input with a control value for changing a cycle of the clock thereof. The jitter measurement circuit has a first logic circuit operated with using an output clock of the clock generating circuit as an input and a first delay element, and is configured to output the presence/absence of a jitter of the clock generating circuit.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: A method for a slave device for calibrating an output timing for transmitting data to a master device is provided. The master and slave devices are communicatively coupled via an interface. The method includes: receiving, from the master device, one or more consecutive first signal edges indicating a synchronization event; recovering a reference clock of the master device based on the one or more consecutive first signal edges; transmitting one or more predetermined second signal edges to the master device and generated using the recovered reference clock; receiving, from the master device, data indicating one or more sampled values of the master device for the one or more predetermined second signal edges; and adjusting the output timing based on a comparison of the one or more predetermined second signal edges and the one or more sampled values of the master device for the one or more predetermined second signal edges.

Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.

Abstract: A delay locked loop (DLL) circuit that includes a delay line, a pattern injecting circuit, a pattern detecting circuit and a counter is introduced. The delay line may align a phase of a reference clock signal with a phase of a feedback clock signal. The pattern injecting circuit injects a predetermined pattern to the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detecting circuit detects the predetermined pattern in the feedback clock signal. The counter determines a delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method of measuring a delay of the DLL circuit is also introduced.

Abstract: A phase locked loop (PLL) comprises: a reference oscillator to generate a reference clock having a reference frequency; a voltage controlled oscillator (VCO) to generate a VCO clock having a VCO frequency controlled in response to a control signal applied to the VCO; a first integrator to integrate the reference frequency into a first ramp slope; a second integrator to integrate the VCO frequency into a second ramp slope; and a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope and that is conveyed by the control signal, such that the control signal is configured to drive the VCO frequency toward the reference frequency to minimize the slope difference and frequency lock the VCO frequency to the reference frequency.

Abstract: A data processing device includes a data processing circuit and a data processing control circuit. The data processing circuit is configured to perform data processing on processing target data by use of an external clock, the processing target data being included in a data signal received from an outside, the external clock being included in the data signal. The data processing control circuit is configured to detect a state of the external clock and control execution of the data processing on the processing target data in accordance with the state of the external clock. The data processing control circuit is configured to operate with a clock having a lower impedance than an impedance of the external clock, and discard the processing target data received during a period in which an abnormality of the external clock is detected, in a case of detecting the abnormality of the external clock.

Abstract: A phase-locked loop (PLL) device includes: 1) a detector configured to output an error signal to indicate a phase offset between a feedback clock signal and a reference clock signal; 2) a charge pump coupled to the detector and configured to output a charge pump signal based on the error signal; 3) an integrator with a feedback path, an input node, a reference node, and an output node, wherein the input node is coupled to the charge pump and receives the charge pump signal; 4) a voltage-controlled oscillator (VCO) coupled to the output node of the integrator via a resistor; and 5) a feedforward circuit coupled directly to the detector and configured to apply an averaged version of the error signal to correct a voltage level received by the VCO.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.

Abstract: A phase detection method and apparatus, and a storage medium and an electronic apparatus are provided. A sampling operation is performed on a clock signal to be detected to obtain binary sequences. Phase intervals of the clock signal to be detected in initial sampling periods are determined, according to the binary sequences, as first phase intervals. Based on a reference phase interval in the first phase intervals, a standardization operation is performed on other phase intervals in the first phase intervals to obtain second phase intervals, wherein the reference phase interval is a phase interval determined within a first sampling period after the sampling operation is triggered, and the other phase intervals are phase intervals determined within sampling periods following the first sampling period. The second phase intervals are converged, and phase information of the clock signal to be detected is obtained according to the converged second phase intervals.

Abstract: A frequency synthesizer includes a clock multiplier unit configured to receive a first clock and output a second clock in accordance with a multiplication factor; a divide-by-three circuit configured to receive the second clock and output a third clock; a first divide-by-two circuit configured to receive the second clock and output a fourth clock; a second divide-by-two circuit configured to receive the fourth clock and output a fifth clock; a first multiplexer configured to receive the third clock and the fourth clock and output a seventh clock in accordance with a first selection signal; a second multiplexer configured to receive the third clock and the fifth clock and output an eighth clock in accordance with a second selection signal; and a mixer configured to receive the seventh clock and the eighth clock and output an output clock.

Abstract: A phase locked loop circuit includes a phase comparator that compares phases of a reference signal through a first frequency divider and a local signal through a second frequency divider to output a phase comparison signal; a loop filter that smooths the phase comparison signal to output the control voltage signal; a controller that sets frequency division ratios of the first and the second frequency dividers; a free-running voltage generator that generates a free-running voltage signal of the voltage control oscillator; a measurement circuit that measures a voltage of the control voltage signal; a storage circuit that stores therein the voltage of the control voltage signal; and a low-pass filter that transmits, to the voltage control oscillator, a corrected free-running voltage signal based on a free-running voltage correction value calculated by the free-running voltage generator based on the control voltage signal before the frequency division ratios are changed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for transmitting, by a first device, a transmission signal that includes a carrier signal modulated with a TM signal. Receiving a response signal from a second device in response to the transmission signal. Determining, whether the response signal includes the TM signal.

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

Abstract: A high-density logic circuit device low-frequency phase-locked loop system includes a digital logic input-output module; an internal clock; an instant-lock module; an instant-adjust error module; a high-speed count comparator; a multiplication factor-is-zero-state detect module with a reset function; a pulse generator; and a high-speed pulse generator. The high-speed count comparator includes a high-speed counter and a high-speed comparator. The input-output module receives an input frequency and transmits an output frequency. The instant lock module locks the output frequency in phase to a leading edge the input frequency within two internal propagation delays. The instant-adjust error module emits a pulse request until a last pulse is identified. The high-speed count comparator receives the pulse request and emits the output frequency. The pulse generators receive the input frequency and internal clock pulses and output a frequency-in pulse.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Abstract: Apparatus and methods determine the rotational position of a spinning object. A satellite positioning system can be used to determine the spatial position of an object, which in turn can be used to guide the object. However, when the object is spinning, such as an artillery shell, then the rotational orientation should be known in order to properly actuate the control surfaces, such as fins, which will also be spinning.

Abstract: Disclosed herein is a fine capacitance tuning circuit for a digitally controlled oscillator. The tuning circuit has low and high frequency tuning banks formed by varactors that have their top plates connected to one another. A controller initially sets states of switches selectively connecting the bottom plates of the varactors of the low frequency bank to a low voltage, a high voltage, or to an RC filter, in response to an integer portion of a control word. A sigma-delta modulator initially sets the states of switches selectively connecting the bottom plates of the varactors of the high frequency bank to either the low voltage or the high voltage, in response to a fractional portion of the control word. The controller modifies the states of the switches of the tuning banks in a complementary fashion, based upon comparisons between the fractional portion of the control word and a series of thresholds.