NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ RELIABILITY
Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.
This application is a continuation application of prior application Ser. No. 13/009,979, filed on Jan. 20, 2011 in the United States Patent and Trademark Office, which claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2010-0011553, filed Feb. 8, 2010, the disclosures of which are incorporated herein in their entirety by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to non-volatile memory devices storing multi-bit data.
2. Description of the Related Art
Generally, semiconductor memory devices are the most essential microelectronic elements for digital logic designs such as computers and applications based on microprocessors pertaining to a range from satellites to consumer electronic technologies. Therefore, the advancements of technologies of fabricating semiconductor memories, including process improvement and technology development obtained through scaling for higher integration and speed, contribute to establishment of performance standards of other digital logics.
Semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. In the volatile memory devices, logic information is stored by establishing the logic state of a flip-flop in case of a static random access memory and charging a capacitor in case of a dynamic random access memory. In the volatile memory devices, data is stored and read while power is supplied, whereas data is lost when power is shut off.
In the nonvolatile memory devices such as MROM, PROM, EPROM, EEPROM, and PRAM, data is retained even when power is shut off. The data storage state of the nonvolatile memory devices is permanent or reprogrammable according to applied fabrication technologies. The nonvolatile memory devices are used to store programs and microcodes in various applications such as computers, avionics, communications, and consumer electronic technologies. A combination of volatile and nonvolatile memory storage modes in a single chip may also be used in devices such as nonvolatile RAMs (nvRAMs) in a system that requires quick and reprogrammable nonvolatile memories. In addition, specific memory structures including some additional logic circuits have been developed to optimize the performance for application-oriented tasks.
In the nonvolatile semiconductor memory devices, it is not easy for general users to renew stored contents because MROM, PROM, and EPROM are not free to erase and write. However, since nonvolatile semiconductor memory devices such as EEPROM and PRAM are possible to electrically erase and write, their applications are being expanded to auxiliary memory units or system programming that requires continuous renewal.
SUMMARY OF THE INVENTIONMemory systems according to embodiments of the invention include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi bit (e.g., N bit, where N>2) memory cells therein. A control circuit is also provided. The control circuit, which is electrically coupled to the nonvolatile memory array, is configured to program at least two pages of data into a first row of nonvolatile multi bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. According to some of these embodiments of the invention, each of the read voltages in the first sequence of read voltages is equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.
Additional aspects and advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
According to additional embodiments of the invention, the control circuit is configured to program the at least two pages of data into the first row by (i) converting at least two pages of write data into at least two pages of converted data having different binary values relative to the at least two pages of write data; and (ii) adjusting threshold voltages of the nonvolatile multi bit memory cells in the first row to correspond to the at least two pages of converted data. This control circuit is also configured to read the at least two pages of converted data from the first row as the at least two pages of write data.
Methods of operating nonvolatile memory devices according to embodiments of the invention include programming a row of N bit memory cells in the nonvolatile memory device with at least three pages of data using a first sequence of read voltages to verify accuracy of the at least three pages of data, and then reading the row of N bit memory cells containing the at least three pages of data using a second sequence of read voltages that is different from the first sequence of read voltages. In particular, these methods may include converting four pages of write data into four pages of converted data having different binary values relative to the four pages of write data. In addition, the programming may include programming the row of N bit memory cells in the nonvolatile memory device with the four pages of converted data using the first sequence of read voltages to verify accuracy of the four pages of converted data. The reading may also include reading the row of N bit memory cells containing the four pages of converted data as the four pages of write data.
According to additional embodiments of the invention, methods of operating nonvolatile memory devices having N bit memory cells therein may include converting at least three pages of write data into at least three pages of converted data having different binary values relative to the at least three pages of write data, and programming a row of N bit memory cells in the nonvolatile memory device with the at least three pages of converted data using a first sequence of read voltages to verify accuracy of the at least three pages of converted data stored within the row of N bit memory cells. An operation may also be performed to read the row of N bit memory cells containing the at least three pages of converted data as the at least three pages of write data, using a second sequence of read voltages that is different from the first sequence of read voltages.
The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:
These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
Exemplary embodiments of the inventive concept will be described below in more detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.
Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures.
In the drawings, exemplary embodiments of the inventive concept are exaggerated for clarity of illustration and are not limited to illustrated specific shapes. Throughout the specification and drawings, like reference numerals denote like elements.
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Also, when one part (or element, device, etc.) is referred to as being “connected/coupled” to another part (or element, device, etc.), it should be understood that the former may be “directly connected” to the latter, or “indirectly connected” to the latter through at least one intervening part (or element, device, etc.). The terms of a singular form may include plural forms unless otherwise specified. Also, the meaning of “include,” “comprise,” “including,” or “comprising,” specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components.
Developments of multi-level data storage technologies have been accelerated to improve price competitiveness. For example, the number of data bits stored in a memory cell is increasing. As the number of data bits stored in a memory cell increases, various limitations such as coupling, error rate, program frequency, and read frequency are being anticipated. It becomes important to determine the ordering of bit patterns that may minimize the above limitations. The ordering of bit patterns may also be called a bit allocation manner. Here, the bit pattern may refer to a line of bits stored in one memory cell. For example, when 4-bit data is stored in one memory cell, the bit pattern may have one of values existing between “0000” and “1111”, and the ordering of bit patterns, i.e., the bit allocation manner may be variously configured according to the number of the data bits stored in the memory cell. The orderings of bit patterns (i.e., bit allocation manners) according to an exemplary embodiment are shown in
The bit patterns shown in
A read operation of data stored in a memory cell may be a process of determining whether a threshold voltage of the memory cell corresponds to any state and obtaining corresponding 4-bit data according to the determination result. The read operation may be performed by a page unit and may be performed to find whether data of respective memory cells in respective pages are ‘0’ or ‘1’ by checking whether the threshold voltage of the memory cell is higher or lower than a state boundary by which data are divided into ‘0’ or ‘1’.
For example, when the memory cells are programmed to have the ordering of bit patterns shown in
When the memory cells are programmed to have the ordering of bit patterns shown in
Multi-bit data programmed according to a determined ordering of bit patterns may be read by a read method corresponding to the determined ordering of bit patterns. That is, a method for programming multi-bit data according to the ordering of bit patterns may correspond to one read method. For example, multi-bit data stored according to the ordering of bit pattern shown in
When data are programmed according to the orderings of the bit patterns shown in
As seen from the above description, it is difficult to determine a bit allocation manner suitable to application of various algorithms for improvement of the threshold voltage distribution as well as implementation of uniform error probability distribution. A memory system according to an exemplary embodiment of the inventive concept may implement uniform error probability distribution, and may use program and read manners suitable to application of various algorithms for improvement of the threshold voltage distribution, which will be described in detail below.
For example, it will be assumed that the respective bit patterns corresponding to the states E and P1 to P15 are allocated as shown in
The non-volatile memory device 300 may be configured to perform the program/read operations in response to the request of the controller 200. The non-volatile memory device 300 may be configured such that transmitted data are programmed according to the program manner (i.e., program manner corresponding to the ordering of bit patterns of the converted data) shown in
A row decoder 320 may be configured to perform selection and driving of the rows of the memory cell array 310. A voltage generator 330 may be controlled by a control logic 340, and may be configured to generate voltages (e.g., program voltage, pass voltage, erase voltage, and read voltage) necessary for the program, erase, and read operations. The read/write circuit 350 may be controlled by the control logic 340, and may operate as a detection amplifier or a write driver according to the operation mode. For example, during the read operation, the read/write circuit 350 may operate as a sense amplifier for detecting data from memory cells (or selected memory cells) of a selected row. The read data may be provided to the outside through the input/output circuit 360 by a predetermined input/output unit. During the program operation, the read/write circuit 350 may operate as a write driver for driving the memory cells of a row selected according to program data. The read/write circuit 350 may include page buffers each corresponding to respective bit lines or bit line pairs. When the respective memory cells store multi-bit/multi-level data, the respective page buffers of the read/write circuit 350 may be configured to have two or more latches. The input/output circuit 360 may be configured to interface with external devices (e.g., memory controller or host)
The control logic 340 may include a read scheduler 341 configured to control the read operation and a program scheduler 342 configured to control the program operation. The read scheduler 341 may control the read operation according to the read manner (e.g., read manner shown in
In an exemplary embodiment, the read scheduler 341 may be configured to be programmable by an external device (e.g., controller). For example, the read algorithm of the read scheduler 341 may be programmable through setting of a register set by the controller 200 upon power-up. The program scheduler 342 may be configured to be programmable in a similar way to the read scheduler 341. On the contrary, the read and program algorithms of the read and program schedulers 341 and 342 may be fixed in hardware.
In an exemplary embodiment, the plurality of storage devices in the same column may be connected to each other in series to form a NAND string. One terminal of the NAND string may be connected to a corresponding bit line through a select transistor controller by the string select line SSL, and the other terminal of the NAND string may be connected to a common source line CSL through a select transistor controlled by a ground select line GSL. In another exemplary embodiment of the odd-even bit line architecture, the bit lines may be divided into even bit lines BLe and odd bit lines BLo. In the odd-even bit line architecture, storage devices in a common word line and connected to the odd bit lines may be programmed at a first time, whereas storage device pertaining to a common word line and connected to the even bit lines may be programmed at a second time. Data may be programmed in other blocks, and may be read from other memory blocks. This operation may be simultaneously performed.
When read/program operations are requested from the host 100, the controller 200 may temporarily store program data provided from the host 100. The program data provided from the host 100 may not be directly sent to the non-volatile memory device 300 by the controller 200. For data conversion, the controller 200 may wait until 4-page data to be stored in memory cells of a selected word line are gathered. Once 4-page data are gathered, the data converter 201 of the controller 200 may convert 4-page data temporarily stored in a buffer memory (not shown) to suit the data to application of various algorithm for compensating for cell distribution deterioration. For example, when a pattern of fourth to first page data bits is “1101” corresponding to a P1 state, the bit pattern “1101” may be converted to the bit pattern “0111”. When a pattern of fourth to first page data bits is “1100” corresponding to a P2 state, the bit pattern “1100” may be converted to the bit pattern “0011”. Bit patterns corresponding to other states may also be converted in the same way as described above. Although the program data are converted, the state to be programmed may not be changed. That is, when the data corresponding to the P1 state is inputted, the converted bit pattern may also correspond to the P1 state.
The converted data may be sent to the non-volatile memory device 300. The program scheduler 342 of the non-volatile memory device 300 may program the converted data in the memory cells of the selected word line. The memory cells of the selected word line may be programmed according to the program manner shown in
Thereafter, the data stored in the memory cells of the selected word line are requested from the host 100, the non-volatile memory device 300 may read the data requested to be read from the memory cells of the word line, and may sent the read data to the controller 200. The controller 200 may send the read data to the host 100 directly without a conversion process, which will be described in detail below.
When the first page data stored in the memory cells of the selected word line is requested from the host 100, the non-volatile memory device 300 may read the first page data by performing a read operation three times by using the read voltages VR2, VR7 and VR13, not the read voltage VR8. The read page data may be data (corresponding to the first page data of the box BO of
As seen from the above description, the controller 200 may convert data such that the data have the ordering of bit patterns suitable to application of various algorithms for improvement of the threshold voltage distribution. The converted data may be stored in the non-volatile memory device 300. The non-volatile memory device 300 may read data according to the ordering of bit patterns suitable to implementation of uniform error probability distribution. The read data may be sent to the host 100 through the controller 200 without a data conversion process. The ordering of bit patterns corresponding to the read operation may be different from the ordering of bit patterns corresponding to the program operation. That is, the program data sent to the non-volatile memory device 300 may be different from the read data sent from the non-volatile memory device 300. For example, embodiments of the invention include at least one nonvolatile memory array 310 having a plurality of rows of nonvolatile multi bit (e.g., N bit, where N>2) memory cells therein. (See, e.g.,
When a program operation is performed at a factory in an application in which a non-volatile memory device is used like ROM, a buffer load of a controller may be removed by converting data in advance to program the converted data in the non-volatile memory device. In this case, the data conversion may be performed according to the program manner corresponding to the ordering of bit patterns of
The flash memory devices are non-volatile memory devices that can retain stored data even when power is shut off. With an increase of the use of mobile devices such as cellular phones, Personal Digital Assistants (PDAs), digital cameras, portable game consoles, and MP3s, the flash memory devices are more widely used as code storages as well as data storages. The flash memory devices may be used for home applications such as HDTVs, DVDs, routers, and Global Positioning Systems (GPS). A computing system including a non-volatile memory device according to an exemplary embodiment of the inventive concept is schematically illustrated in
The computing system may include a microprocessor 3100 electrically connected to a bus 3001, a user interface 3200, a modem 3300 such as a baseband chipset, a memory controller 3400, and a flash memory device 3500 serving as a storage medium. The flash memory device 3500 may be configured in the substantially same as that of
In an exemplary embodiment of the inventive concept, the memory cells may be configured with variable resistance memory cells. An exemplary variable resistance memory cell and a memory device including the same are disclosed in U.S. Pat. No. 7,529,124, the entire contents of which are hereby incorporated by reference.
In another exemplary embodiment of the inventive concept, memory cells may be implemented using one of various cell structures having a charge storage layer. The cell structure having the charge storage layer may include a charge trap flash structure using a charge trap layer, a stack flash structure with multi-layered arrays, a flash structure without a source-drain, and a pin-type flash structure.
A memory device having a charge trap flash structure as a charge storage layer is disclosed in U.S. Pat. No. 6,858,096, U.S. Pat. Pub. No. 2004-0169238, and U.S. Pat. Pub. No. 2006-0180851, the entire contents of which are hereby incorporated by reference. The flash structure without a source/drain is disclosed in Korean Pat. No. 673020, the entire contents of which are hereby incorporated by reference.
A flash memory device and/or a memory controller according to an exemplary embodiment of the inventive concept may be mounted using various types of packages. For example, the flash memory device and the memory controller according to an embodiment of the inventive concept may be mounted using packages such as Package on Package (PoP), Ball Grid Arrays (BGA), Chip Scale Packages (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), and Wafer-level Processed Stack Package (WSP).
According to exemplary embodiments of the inventive concept, it is possible to adopt the ordering of bit patterns suitable to application of various algorithms for improvement of threshold voltage distribution, and the ordering of bit patterns suitable to implementation of uniform error probability distribution and read latency.
The above-disclosed subject matter is to be considered illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
Claims
1. A method of programming multi-bit data in a nonvolatile memory cell array, the method comprising:
- gathering full page data to be stored in selected memory cells in a row of the nonvolatile memory cell array;
- converting the full page data into converted data having different binary values relative to the full page data; and
- storing the full page data in the selected memory cells using the converted data by performing at least two or more program sequences.
2. The method of claim 1, wherein the full page data stored in the selected memory cells is read according to a reading operation with a uniform read latency.
3. The method of claim 1, wherein the full page data has a first state ordering of bit patterns, and the converted data has a second state ordering of bit patterns.
4. The method of claim 3, wherein the full page data is stored in the selected memory cells using the converted data having the second state ordering of bit patterns by performing three program sequences.
5. The method of claim 4, further comprising:
- reading the full page data stored in the selected memory cells according to a read operation corresponding to the first state ordering of the bit patterns.
6. The method of claim 1, wherein the full page data comprise first, second, and third page data.
7. The method of claim 1, wherein:
- the performing the at least two or more program sequences comprises performing a first program sequence with a first program state and preforming a second program sequence with at least two second program states; and
- the first program state of the first program sequence is disposed between the at least two second program states of the second program sequence.
8. The method of claim 1, wherein:
- the performing the at least two or more program sequences comprises performing a first program sequence and performing a next program sequence; and
- the first program sequence includes a number of program states, and the number of program states of the first program sequence is less than the number of program states of the next program sequence.
9. The method of claim 8, wherein:
- the program states of the first program sequence comprise an utmost program state having a threshold voltage distribution lower than a threshold voltage of an utmost program state of the next program sequence.
10. The method of claim 1, wherein:
- the full page data stored in the selected memory cells comprises a plurality of pages;
- each page of the plurality of the pages is read according to one or more corresponding reading operations;
- the number of the corresponding reading operation for each page is different from that for one or more other pages; and
- a difference between the numbers of the corresponding read operations is equal to or less than 1.
11. The method of claim 1, wherein the full page data to be stored in the selected memory cells are retained in a buffer until the storing the converted data is completed.
12. The method of claim 1, wherein the performing of the at least two or more program sequences in the storing of the full page data in the selected memory cells comprises performing three program sequences.
13. The method of claim 12, wherein the performing of the three program sequences comprises:
- gathering the full page data,
- converting the full page data into first converted data,
- storing the first full page data using the first converted data according to a first program sequence,
- gathering the full page data again;
- storing the full page data according to a second program sequence,
- gathering the full page data again, and
- storing the full page data according to a third program sequence.
14. A programming method of a nonvolatile memory device, the method comprising:
- gathering data of a plurality of pages to be stored in the multi-bit memory cells in a row of the nonvolatile memory cell array; and
- storing the data with a plurality of program sequences,
- wherein at least one program sequence of the plurality of program sequences comprises converting the data corresponding to each of the multi-bit memory cells into converted data having different binary values from binary values of the data and programming the converted data in the multi-bit memory cells, and
- wherein an increment of threshold voltages in every state within each program sequence of the plurality of the program sequences is uniform.
15. The program method of claim 14, wherein the converted data are variable at least two of the respective program sequences.
16. The program method of claim 14, wherein the converted data are same in the program sequences.
17. A programming method of a nonvolatile memory device, the method comprising:
- gathering data of a plurality of pages to be stored in the multi-bit memory cells in a row of the nonvolatile memory cell array;
- storing the data with a plurality of program sequences,
- wherein at least one program sequence of the plurality of program sequences comprises converting the data corresponding to each of the multi-bit memory cells into converted data having different binary values from binary values of the data and programming the data using the converted data in the multi-bit memory cells such that the data programmed in the multi-bit memory cells are read according to a number of reading operations,
- wherein a state ordering of bit patterns of the data programmed in the multi-bit memory cells includes performing a number of the reading operations at each page such that a difference among numbers of the reading operations is not greater than 1.
18. A nonvolatile memory system, comprising:
- a nonvolatile memory having a nonvolatile memory cells; and
- a controller configured to receive full pages of data in a data buffer, to convert the full pages of data stored in the data buffer into full pages of converted data having different binary values relative to the full pages of data, and to store the full pages of converted data in selected memory cells in a row of the memory cell array by performing at least two or more program sequences.
19. The nonvolatile memory system of claim 18, wherein the nonvolatile memory cells have a cell structure having a flash structure without a source-drain.
20. The nonvolatile memory system of claim 18, wherein the nonvolatile memory cells have a cell structure having a charge trap flash structure using a charge trap layer.
21. The memory device of claim 20, wherein the cell structure comprises a three dimensional array structure.
22. The memory device of claim 18, wherein:
- the controller receives host data from an external host and to convert the host data; and
- the nonvolatile memory comprises a voltage generator and a control logic to receive the converted data from the controller and to control the voltage generator such that the received data is programmed and the programmed data is read according to different arrangements of different voltage sets corresponding to full pages of the data.
23. The memory device of claim 18, wherein:
- the controller gathers the full pages of data in the data buffer each time when the nonvolatile memory stores a portion of the full pages of the converted data by performing a corresponding one of the at least two or more program sequences.
24. A nonvolatile memory device comprising:
- the non-volatile memory device having a memory cell array having nonvolatile memory cells, and configured to gather full pages of data in a data buffer, to convert the full pages of data stored in the data buffer into converted data having different binary values relative to the full pages of data, and to store the converted data in selected memory cells in a row of the memory cell array by performing at least two or more program sequences.
25. A method of programming multi-bit data in a nonvolatile memory cell array, the method comprising:
- gathering full page data to be stored in selected memory cells in a row of the nonvolatile memory cell array;
- converting the full page data into first data having different binary values relative to the full page data;
- storing the first data in the selected memory cells by performing a first program sequence;
- gathering the full page data when the first data is stored;
- storing second data of the full page data in the selected memory cells by performing a second program sequence;
- gathering the full page data when the second data is stored; and
- storing third data of the full page data according to a third program sequence,
- wherein a number of program states of the first program sequence is less than a number of program states of the second program sequence, and the number of program states of the second program sequences is equal to or less than a number of program states of the third program sequence, and
- wherein a threshold voltage distribution of an utmost program state of the program states of the first program sequence is lower than a threshold voltage of an utmost program state of the program states of the second program sequence, and the threshold voltage distribution of the utmost program state of the second program sequence is lower than a threshold voltage of an utmost program state of the program states of the third program sequence.
26. A method of programming multi-bit data in a nonvolatile memory cell array, the method comprising:
- gathering full page data to be stored in selected memory cells in a row of the nonvolatile memory cell array;
- converting the full page data into first data having different binary values relative to the full page data;
- storing the first data in the selected memory cells by performing a first program sequence;
- gathering the full page data when first data is stored;
- storing second data of the full page data in the selected memory cells by performing a second program sequence;
- gathering the full page data when the second data is stored; and
- storing third data of the full page data in the selected memory cells according to a third program sequence,
- wherein the full page data stored in the selected memory cells are read according to a number of reading operations, and
- wherein the full page data is stored in the selected memory cells according to a state ordering of bit patterns, and the reading of the stored full page data includes performing the number of the reading operations at each page such that a difference among numbers of the reading operations is not greater than 1.
Type: Application
Filed: Aug 23, 2012
Publication Date: Dec 13, 2012
Inventor: Donghyuk CHAE (Seoul)
Application Number: 13/593,036
International Classification: G11C 16/04 (20060101);