Abstract: A semiconductor memory device includes i first word lines connected to the i first memory cells, i second word lines connected to the i second memory cells, a driver capable of supplying voltage to each of the i first word lines and each of the i second word lines, and a logic control circuit controlling both a write operation including a verify operation and a read operation including a verify operation. In the semiconductor memory device, when an order of performing a sense operation for determining whether or not a threshold voltage of the k-th first memory cell has reached a j-th threshold voltage in the verify operation is different from that of in the read operation, a voltage applied to the k-th first word line in the verify operation is different from a voltage applied to the k-th first word line in the read operation.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: A method for decoding a 360-degree image includes: receiving a bitstream obtained by encoding a 360-degree image; generating a prediction image by making reference to syntax information obtained from the received bitstream; combining the generated prediction image with a residual image obtained by dequantizing and inverse-transforming the bitstream, so as to obtain a decoded image; and reconstructing the decoded image into a 360-degree image according to a projection format. Here, generating the prediction image includes: checking, from the syntax information, prediction mode accuracy for a current block to be decoded; determining whether the checked prediction mode accuracy corresponds to most probable mode (MPM) information obtained from the syntax information; and when the checked prediction mode accuracy does not correspond to the MPM information, reconfiguring the MPM information according to the prediction mode accuracy for the current block.

Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.

Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

Abstract: Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

Abstract: A method includes determining that a criteria involving a memory device is met and performing a defect scan involving memory dice of the memory device in response to the criteria being met. The method further includes determining, as part of performing the defect scan, whether at least one memory die of the memory device has experienced degradation. The defect scan is performed as part of a quality and reliability assurance test or a reliability demonstration test, or both.

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.

Abstract: A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.

Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

Abstract: A controller controls a semiconductor memory device including a plurality of memory blocks. The controller includes a block manager, a map data manager, and a command generator. The block manager manages information on the plurality of memory blocks. The map data manager manages map data for data stored in the plurality of memory blocks. The command generator generates a program command for controlling a program operation of the semiconductor memory device. The command generator generates a program command for storing data in a first memory block among the plurality of memory blocks, and determines a second memory block to store dummy data based on information from the block manager when the first memory block is full by a program operation corresponding to the program command.

Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

Abstract: A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition.

Abstract: A method of operating a memory controller includes: collecting hard decision information based on data read from memory cells of a monitoring unit using a normal read level; collecting soft decision information based on data read from the monitoring unit using one or more offset read levels that are different from the normal read level; storing first strong error information determined based on the hard decision information and the soft decision information in a memory in the memory controller; and updating second strong error information determined for the monitoring unit in the memory after the first strong error information is stored. The second strong error information is used to correct an error in data read in response to a read request from a host.

Abstract: According to one embodiment, a detection circuit includes a first filter circuit configured to output a first voltage, a ramp circuit configured to output a ramp voltage, a comparator configured to output a first result of comparison between the first voltage and the ramp voltage and a second result of comparison between a second voltage and the ramp voltage, and a controller, wherein the controller determines a first period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the first voltage and the ramp voltage is inverted, and determines a second period of time between a time when the ramp voltage output is started and a time when a magnitude correlation between the second voltage and the ramp voltage is inverted.

Abstract: There is provided a method for operating a memory device for performing a program operation of programming data in selected memory cells among a plurality of memory cells. The method includes: applying a program voltage to the selected memory cells; verifying program states of memory cells programmed to any one program state among a plurality of program states distinguished based on a plurality of threshold voltages among the selected memory cells; and verifying an erase state of memory cells programmed to an erase state among the selected memory cells.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: A method includes selectively configuring a first subset of non-volatile memory blocks to operate in a single-level mode, configuring the first subset of non-volatile memory blocks to collectively operate as a pseudo single-level cache, writing data associated with performance of a memory operation to the first subset of non-volatile memory blocks, and migrating the data from the first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller may sense a first threshold voltage of the selected memory cell. In response to the sensed first threshold voltage being between a first pre-program verify level and a first program verify level, the controller may bias the selected memory cell to a first voltage level. The first pre-program verify level might be less than a final pre-program verify level and the first program verify level might be less than a final program verify level.

Abstract: The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.

Abstract: Provided herein is a page buffer, a semiconductor memory device with the page buffer, and a method of operating the semiconductor memory device. The page buffer includes a plurality of data latch components coupled to a sensing node, a bit line controller coupled between a bit line and the sensing node, the bit line controller configured to control a node value of the sensing node based on a program state of a memory cell that is coupled to the bit line during a program verify operation, and a sub-latch component configured to latch verification data based on the node value during the program verify operation, wherein each data latch component sets the node value to a first logic value when a program state that corresponds to program data has a threshold voltage distribution that is higher than that in a target program state during the program verify operation.

Abstract: A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

Abstract: A storage device may include a memory device including a memory block coupled to physical word lines each including pages, and a memory controller configured to control the memory device such that, in response to a power off event occurring during a program operation on a selected page, fine program operations are performed on to-be completed pages, which precede the selected page, on which foggy program operations have been completed and on which the fine program operations have not yet been performed. The program operation may include a foggy program operation of programming memory cells included in the pages so that each memory cell has a threshold voltage corresponding to any one of intermediate states corresponding to states, and a fine program operation of programming the memory cells having the threshold voltages corresponding to the intermediate states so that each memory cell has a threshold voltage corresponding to any one state.

Abstract: An operation method includes buffering data chunks to be programmed in the multi-level cells in a write buffer; backing up at least one backup data chunk of the data chunks to a backup memory; determining a program sequence of the data chunks, the program sequence for programming a non-backup data chunk among the data chunks to the multi-level cells through a second step program operation of the multi-step program operation; and controlling the memory device to program the data chunks in the multi-level cells, based on the program sequence, by performing first and second step program operations of the multi-step program operation in a first page of the multi-level cells, the second step program operation performed in the first page later than another first step program operation performed in a second page subsequent to the first page.

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.

Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

Abstract: A storage device includes a memory device including a plurality of sequential areas and a random area other than the plurality of sequential areas, the plurality of sequential areas storing pieces of data corresponding to consecutive logical addresses input from a host, a buffer memory device configured to temporarily store write data corresponding to a write request provided from the host and an operation controller configured to generate combined data by adding dummy data to the write data having a size less than a program unit size of the memory device, a size of the dummy data corresponding to a difference between the size of the write data and the program unit size, store the combined data in the memory device, and store combined data information, relating to the combined data stored in the memory device, in the buffer memory device.

Abstract: A storage system communicates with a host system and includes a storage device including storage medium divided into a plurality of blocks including high reliability blocks and reserve blocks, and a controller. The controller provides the host system with block information identifying the high reliability blocks among the plurality of blocks, receives a block allocation request from the host system, wherein the block allocation request is defined with reference to the block information and identifies at least one high reliability block to be used to store metadata, and allocates at least one high reliability block to a meta region in response to the block allocation request. The controller includes a bad block manager that manages an allocation operation performed in response to the block allocation request, and a repair module that repairs an error in metadata stored in one of the high reliability blocks.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

Abstract: A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a control logic circuit configured to control the peripheral circuit so that the program operation is performed. The control logic circuit controls a peripheral circuit so that memory cells to be programmed to first to (N?1)-th program states are programmed in a double program method using a main verify voltage and a sub verify voltage less than the main verify voltage during a verify operation and memory cells to be programmed to the N-th program state are programmed in a normal program method using the main verify voltage during the verify operation, when the verify operation of the memory cells corresponding to the (N?1)-th program state has failed.

Abstract: A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive read requests from a host device. When a read request is received corresponding to one or more pages from a first plane and one or more pages from a second plane, the controller is configured to determine a decode time for the pages of the first plane and the pages of the second plane. Based on the decode times for pages of the first plane and pages of the second page, pages of the first plane that have a similar decode time to pages of the second plane are read in parallel.

Abstract: Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

Abstract: A memory device having an improved operation speed may include a memory block including memory cells, a peripheral circuit configured to perform a program operation of increasing each of threshold voltages of the memory cells, and a control logic configured to control the peripheral circuit to perform the program operation. The program operation may include a plurality of program loops, each of the plurality of program loops may include a program voltage apply operation and a verify operation, and the control logic may control the peripheral circuit to perform verification on a highest program state during a verify operation included in a next program loop of any one program loop, when verification of a next higher program state among the plurality of program states is passed during a verify operation included in the any one program loop among the plurality of program loops.