Multiple Values (e.g., Analog) Patents (Class 365/185.03)
  • Patent number: 11462272
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Jae Hyeon Shin, In Gon Yang, Sungmook Lim
  • Patent number: 11461046
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a memory device including a plurality of memory blocks, and a memory controller configured to: manage an accumulated erase count value and an open block erase count value of each of the plurality of memory blocks, and select a target memory block on which a program operation is to be performed based on the accumulated erase count value and the open block erase count value of each of the plurality of memory blocks.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Na Ra Shin, Jung Sik Choi
  • Patent number: 11443809
    Abstract: Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Tae Hun Park, Nam Kyeong Kim
  • Patent number: 11437511
    Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 6, 2022
    Assignee: Sony Group Corporation
    Inventors: Joseph M. Steigerwald, Tahir Ghani, Jenny Hu, Ian R. C. Post
  • Patent number: 11437092
    Abstract: Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shih-Lien Linus Lu
  • Patent number: 11437104
    Abstract: A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Patent number: 11430500
    Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Haruka Sakuma, Kiwamu Sakuma, Masumi Saitoh
  • Patent number: 11430525
    Abstract: According to one embodiment, a memory device, includes a first memory cell, and a second memory cell adjacent to the first memory cell; and a sequencer configured to, when data is read from the first memory cell: perform a first read operation on the second memory cell; perform a second read operation on the first memory cell; perform a third read operation on the first memory cell by applying a voltage different from that applied in the second read operation to a gate of the second memory cell; and generate first data stored in the first memory cell and second data for correcting the first data, based on results of the first to third read operations.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoko Araya, Mitsuaki Honma
  • Patent number: 11430491
    Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng, Szu-Chun Tsao
  • Patent number: 11422752
    Abstract: A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: August 23, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeen Park, Jong Min Lee
  • Patent number: 11423980
    Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 23, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuki Shimizu, Kosuke Yanagidaira
  • Patent number: 11417401
    Abstract: A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 16, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Mario Sako, Hiromitsu Komai, Masahiro Yoshihara
  • Patent number: 11412867
    Abstract: A framed collectible for displaying a continuously-looping playback of a digital video file is provided, wherein a display panel is controlled by a display controller to play at least one video file in a continuous loop on the display panel only while an output signal from a magnet sensor indicates no proximity to a magnet proximal to the back side of the display panel. The display controller has a printed circuit board that incorporates at least one processor and at least one memory that contains at least one video file. The memory, which in an embodiment can be flash memory, is factory programmed and therefore the memory content cannot be changed by an end user. Packaging for storage and shipping of the framed collectible is also provided, which incorporates a magnet that is sensed by the magnet sensor to keep continuously-looping video playback switched off while the device is stored.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: August 16, 2022
    Assignee: INFINITE OBJECTS, INC.
    Inventors: Joseph Saavedra, Kensuke Sembo, Nicholas Dangerfield, Alexander Chung, Ralph Bishop
  • Patent number: 11416391
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Patent number: 11393525
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoki Nakagawa, Koji Kato, Toshifumi Hashimoto
  • Patent number: 11393538
    Abstract: A data storage device having a reduced overhead according to an embodiment of the disclosed technology may include a plurality of memory chips each including a plurality of planes, and a memory controller configured to perform recovery algorithms that recover data corresponding to failed read operations among read operations performed on the plurality of memory chips, and the memory controller may generate a read voltage to be used in a first recovery algorithm using an address related to a selected read operation among the failed read operations and perform the first recovery algorithm on a memory location associated with the failed read operations using the read voltage.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 19, 2022
    Assignee: SK HYNIX INC.
    Inventor: Ok Kyun Oh
  • Patent number: 11393534
    Abstract: A processing device determines a measured slope value of a portion of a programming voltage distribution of memory cells of a memory sub-system. The measured slope value of the portion of the programming voltage distribution is compared to a threshold slope value to generate a comparison result. An adjusted program voltage level is determined in view of the comparison result. A programming process is executed using the adjusted program voltage level as a starting voltage level.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 19, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Bruce A. Liikanen, Michael Sheperek, Larry J. Koudele
  • Patent number: 11386940
    Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 11380390
    Abstract: A memory device includes a memory cell array including M memory cells connected to one bit line and configured to distributively store N-bit data, where N is a natural number of 2 or more and M is a natural number of 2 or more and less than or equal to N, the M memory cells including a first memory cell and a second memory cell having different sensing margins, and a memory controller including a page buffer, the memory controller configured to distributively store the N-bit data in the M memory cells and to sequentially read data stored in the M memory cells to obtain the N-bit data, and an operation logic configured to execute an operation using the N-bit data, the memory controller configured to provide different reading voltages to the first memory cell and the second memory cell.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Garam Kim
  • Patent number: 11373720
    Abstract: The present disclosure describes analog memories for use in a computer, such as a computer using a combination of analog and digital components/elements used in a cohesive manner.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 28, 2022
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Peter Linder, Laurence Ray Simar, Jr., Erik James Welsh, Gene Alan Frantz
  • Patent number: 11367472
    Abstract: A semiconductor storage device of embodiments is a semiconductor storage device including a memory cell array including a plurality of non-volatile memory cells, a sequencer configured to control a sequence based on read operation of reading data from the memory cell array, and a column decoder, the sequencer controlling the sequence of changing a ready/busy signal from ready to busy after receiving a read command and an address signal, reading data from the memory cell array using a sense amplifier after changing the ready/busy signal to the busy, changing the ready/busy signal from the busy to the ready after storing data in the data latch circuit, receiving a data output command after changing the ready/busy signal to the ready, and, in a case where a first condition occurs, writing log data including the data stored in the data latch circuit in a memory area of the memory cell array.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 21, 2022
    Assignee: Kioxia Corporation
    Inventor: Makoto Iwai
  • Patent number: 11367489
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 11367505
    Abstract: The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 11366718
    Abstract: A memory system includes a memory device including a plurality of cells associated with multiple pages and a controller. The controller selects a read bias set in response to a read address and modifies the read bias set to generate modified read bias set using one of a plurality of modification arrays. The controller performs a read operation on the select page using the modified read bias set. For a select read bias of the read bias set, the controller accumulates a fail bit count corresponding to a read operation using a select modified read bias of the modified read bias set into the plurality of accumulators using subtraction or addition. When an absolute value of a certain accumulator of the fail bit count is greater than a threshold, the controller shifts the select read bias in a correction direction by a specific magnitude corresponding to the accumulator sign.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventor: Teodor Vlasov
  • Patent number: 11355202
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 7, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Hironori Uchikawa
  • Patent number: 11348645
    Abstract: A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device; separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons; separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons; and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: May 31, 2022
    Assignee: CHINA FLASH CO., LTD.
    Inventors: Hong Nie, Jingwei Chen
  • Patent number: 11341403
    Abstract: A synapse system of a neuromorphic device may include a pre-synaptic neuron; a pre-synaptic line extending from the pre-synaptic neuron in a first direction; a post-synaptic neuron; a post-synaptic line extending from the post-synaptic line in a second direction; a selecting controller; a selecting line extending from the selecting controller in a third direction; and a synapse electrically connected with the pre-synaptic line, the post-synaptic line, and the selecting line.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11342263
    Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang-Gn Yun, Jaesun Yun, Joon-Sung Lim
  • Patent number: 11335407
    Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Phong Sy Nguyen, James Fitzpatrick, Kishore Kumar Muchherla
  • Patent number: 11334144
    Abstract: According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuusuke Nosaka, Kouji Watanabe, Tomonori Tsuhata, Shingo Akita
  • Patent number: 11328777
    Abstract: Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Theodore T. Pekny
  • Patent number: 11317742
    Abstract: A framed collectible for displaying a continuously-looping playback of a digital video file is provided, wherein a display panel is controlled by a display controller to play at least one video file in a continuous loop on the display panel only while an output signal from a magnet sensor indicates no proximity to a magnet proximal to the back side of the display panel. The display controller has a printed circuit board that incorporates at least one processor and at least one memory that contains at least one video file. The memory, which in an embodiment can be flash memory, is factory programmed and therefore the memory content cannot be changed by an end user. Packaging for storage and shipping of the framed collectible is also provided, which incorporates a magnet that is sensed by the magnet sensor to keep continuously-looping video playback switched off while the device is stored.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: May 3, 2022
    Assignee: Infinite Objects, Inc.
    Inventors: Joseph Saavedra, Kensuke Sembo, Nicholas Dangerfield, Alexander Chung, Ralph Bishop
  • Patent number: 11321167
    Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as single bit per memory cell data to increase the performance of the programming process. Subsequently, the control die performs an adaptive folding process which comprises reading the single bit per memory cell data from the memory die, adaptively performing one of multiple decoding options, and programming the data back to the memory die as multiple bit per memory cell data.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Alex Bazarsky, Idan Alrod
  • Patent number: 11322204
    Abstract: A semiconductor memory device includes first and second memory cells, adjacent first and second word line connected to gates of the first and second memory cells, respectively, a word line driver for the first and second word lines, a bit line connected to the first and second memory cells, a sense amplifier circuit configured to detect data stored in the memory cells via the bit line and apply a voltage to the bit line, and a control circuit configured to control the word line driver and the sense amplifier circuit to execute a write operation. During a write operation performed on the first memory cell to increase a threshold voltage of the first memory cell to a target state, the control circuit changes the bit line voltage of the bit line according to a difference between the target state and a threshold voltage state of the second memory cell.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 3, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Taira Shibuya
  • Patent number: 11322210
    Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 3, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Marie Takada, Masanobu Shirakawa
  • Patent number: 11315643
    Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 26, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa
  • Patent number: 11315631
    Abstract: A three-dimensional (3D) memory device includes a memory cell array, a first sense amplifier and a second sense amplifier. The memory cell array includes lower memory cells respectively arranged in regions where lower word lines intersect with bit lines and upper memory cells respectively arranged in regions where upper word lines intersect with the bit lines. The first sense amplifier is connected to a first lower word line and performs a data sensing operation on a first lower memory cell connected between a first bit line and the first lower word line. The second sense amplifier is connected to a first upper word line and performs a data sensing operation on a first upper memory cell connected between the first bit line and the first upper word line. The data sensing operations of the first and second sense amplifiers are performed in parallel.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Makoto Hirano, Jinyoung Kim
  • Patent number: 11309042
    Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Viktor Markov, Alexander Kotov
  • Patent number: 11309019
    Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Patent number: 11301168
    Abstract: A storage system and method for user-defined data archiving are provided. In one embodiment, the method comprises: receiving a write command from a host; determining whether the storage system received an indicator from the host indicating that data of the write command is archive data; in response to determining that the storage system received the indicator, storing the data in the multi-level memory cells; and in response to determining that the storage system did not receive the indicator, storing the data in the single-level memory cells. Other embodiments are provided.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Laxmi Bhoopali, Ramanathan Muthiah, Kshitij Gupta, Niraj Srimal
  • Patent number: 11302398
    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: April 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Katsuaki Isobe, Noboru Shibata, Toshiki Hisada
  • Patent number: 11302403
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Patent number: 11295819
    Abstract: A controller utilizes dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells. One or more iterations of DSBB may be performed to provide a read level. Each iteration of the DSBB includes performing a first sense read, performing a second sense read, determining a read error, and adjusting the initial read level. The first sense read is performed at a first offset of an initial read level of memory cells. The second sense read is performed at a second offset of the initial read level of memory cells. A read error is determined from the first sense read and the second sense read. The read level is adjusted by the read error. A read of the randomized data pattern is conducted with the adjusted read level of a last iteration of the DSBB.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jonas Goode, Richard Galbraith, Henry Yip, Idan Alrod, Eran Sharon
  • Patent number: 11288009
    Abstract: The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device performs a first read, a second read, and a third read of data from the memory component using a center value corresponding to a read threshold voltage value, a negative offset value, and a positive offset value, respectively. The processing device performs a most probable bit operation on the first set of data, the second set of data, and the third set of data to generate a most probable bit sequence corresponding to the data associated with the memory component. The processing device can store or output the generated most probable bit sequence.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen
  • Patent number: 11289173
    Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Boh-Chang Kim
  • Patent number: 11282580
    Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. The controller circuit is configured to program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data, program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data, the second portion neighboring the one or more wordlines.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mayank Gupta, Phani Raghavendra Yasasvi Gangavarapu, Arun Balakrishnan
  • Patent number: 11276461
    Abstract: Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Jonathan W. Oh, Fulvio Rori
  • Patent number: 11270765
    Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: March 8, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Tokumasa Hara, Noboru Shibata
  • Patent number: 11264092
    Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit and a judging circuit. The cell array includes plural multi-level memory cells in an m×n array. The cell array is connected with m word lines and n lines. The current supply circuit provides one of plural reference currents according to a current control value. The path selecting circuit is connected with the current supply circuit and the n bit lines. The judging circuit is connected with the path selecting circuit, and generates n output data. A first path selector of the path selecting circuit is connected with a path selecting circuit and a first bit line. A first judging device of the judging circuit is connected with the first path selector and generates a first output data.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: March 1, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Fu Chang, Wei-Ming Ku, Hung-Yi Liao
  • Patent number: 11265502
    Abstract: A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 1, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Norihiko Sumitani, Yosuke Higashi