Multiple Values (e.g., Analog) Patents (Class 365/185.03)
  • Patent number: 10977117
    Abstract: An operating method of memory system may include: reading target data stored in a target memory page, using a plurality of read voltages, respectively; sequentially storing read data corresponding to the target data in a plurality of latches including a first latch and a second latch, respectively; performing a first error correction code (ECC) decoding operation on first read data stored in the first latch; and performing a second ECC decoding operation on second read data stored in the second latch, when the first ECC decoding operation fails.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Jiman Hong
  • Patent number: 10970160
    Abstract: A BER corresponding to a group of memory cells programmed via a programing signal having one or more program step characteristics is determined. The determined BER and a target BER is compared. In response to the determined BER being different than the target BER, one or more program step characteristics are adjusted to adjust the determined BER to the target BER.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Bruce A. Liikanen
  • Patent number: 10964402
    Abstract: Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 30, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Han-Ping Chen, Henry Chin, Ashish Baraskar
  • Patent number: 10964390
    Abstract: An apparatus and method of skip coding user data is provided. According to skip coding, for each cell in which an upper page is 0, data is stored in a half page. For each portion of data in which the upper page is 1, data is not stored in the half page. Thus, cells of a NAND memory may each store 3.5 bits, in one of twelve available states.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 30, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Hiroki Yabe
  • Patent number: 10964392
    Abstract: A memory system includes a controller suitable for providing first data, a cache program command corresponding to the first data, second data, and a normal program command corresponding to the second data; and a memory device suitable for programming the first data to a target die according to the cache program command, setting the target die to a normal state after the program operation for the first data is completed, and programming the second data to the target die according to the normal program command.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Lee
  • Patent number: 10964377
    Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 30, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Keita Kimura, Kenri Nakai, Mario Sako
  • Patent number: 10957407
    Abstract: A computer-implemented method, according to one approach, is for calibrating read voltages for a block of memory. The computer-implemented method includes: determining a current operating state of a block which includes more than one word-line therein, and where more than one read voltage is associated with each of the word-lines. Moreover, for each of the word-lines in the block: one of the read voltages associated with the given word-line is selected as a reference read voltage, and an absolute shift value is calculated for the reference read voltage. A relative shift value is determined for each of the remaining read voltages associated with the given word-line, where the relative shift values are determined with respect to the reference read voltage. Furthermore, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Charalampos Pozidis, Nikolas Ioannou, Roman Alexander Pletka, Radu Ioan Stoica, Sasa Tomic, Timothy Fisher, Aaron Daniel Fry
  • Patent number: 10956067
    Abstract: Disclosed herein is a memory controller controlling data transfer between a host system and a flash memory. The memory controller is configured to operate on one of a plurality of operation states including first and second operation states. In the first operation state, a first memory area included in the flash memory is used in a first storage mode that stores information of less than n bits in one cell, and a second memory area included in the flash memory is used in a second storage mode that stores information of n bits or more in one cell. In the second operation state, the first memory area is used in the second storage mode, and the second memory area is used in the first storage mode.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 23, 2021
    Assignee: TDK CORPORATION
    Inventor: Kazuo Shida
  • Patent number: 10957405
    Abstract: A memory system includes a semiconductor storage device including a memory cell array including a plurality of groups of memory cells, and a control circuit configured to perform, upon receipt of a write command, a write operation on one of the groups of memory cells, and a memory controller is configured to, when transmitting the write command to perform the write operation on the one of the groups of memory cells, determine a first write voltage value for the write operation based on a total number of write operations or erase operations that have been performed on the one of the groups of memory cells, and transmit the write command to the semiconductor storage device together with the determined first write voltage value.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hideki Yamada, Masanobu Shirakawa
  • Patent number: 10957409
    Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: March 23, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinlei Jia, Shan Li, Yali Song, Lei Jin, Hongtao Liu, Jianquan Jia, XiangNan Zhao, Yuan-Yuan Min
  • Patent number: 10957381
    Abstract: Devices and techniques are disclosed herein to address high latency associated with large-scale un-map or trim commands associated with flash memory. In an example, a method can include receiving a trim command for a partition of a storage system, identifying a record of a partition table of the storage system corresponding to the partition, updating a partition count of the record with a count value of a partition counter of the storage system, and incrementing the partition counter.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 10957387
    Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Kiran Pangal, Sanjay Rangan
  • Patent number: 10949344
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Patent number: 10943650
    Abstract: A memory system comprising a plurality of memory cells each including a storage element having a first terminal and a control terminal. The method for operating the memory system includes applying a first program voltage to control terminals of storage elements and applying a basic reference voltage to first terminals of the storage elements during a first program operation, performing a group verification by comparing threshold voltages of the storage elements with a middle voltage, performing a first program test to check if the threshold voltages of the storage elements are greater than a first programming threshold voltage, and performing a second program operation according to a result of the group verification and a result of the first program test. The middle voltage is smaller than the first programming threshold voltage.
    Type: Grant
    Filed: May 12, 2019
    Date of Patent: March 9, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Ke Liang, Chun Yuan Hou, Qiang Tang
  • Patent number: 10943666
    Abstract: A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 9, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Duk Ju Jeong
  • Patent number: 10936392
    Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jung Sheng Hoei, Peter Sean Feeley, Sampath K. Ratnam, Sead Zildzic, Kishore Kumar Muchherla
  • Patent number: 10936391
    Abstract: A memory management method and a storage controller are provided. The method includes performing a decoding operation to a first data stored in a first word line among multiple word lines of a rewritable non-volatile memory module to determine whether the decoding operation is successful or failed, and obtain a first error value of the first word line; when the decoding operation is determined as successful, determining whether to mark the first word line as a bad word line according to the first error value and a first threshold; and when the decoding operation is determined as failed, obtaining a second error value of a second word line adjacent to the first word line, and determining whether to mark both of the first and second word lines as the bad word line according to the first error value, the second error value, and a first threshold.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 2, 2021
    Assignee: SHENZHEN EPOSTAR ELECTRONICS LIMITED CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10937504
    Abstract: A memory device includes a plurality of memory cells arranged in N rows, N being a positive integer. A method includes programming a first row of the N rows; after programming the first row, programming a (2m+1)th row, m being an integer between 1 and N/2?1; and immediately after programming the (2m+1)th row, programming a (2m)th row; and after programming an (N?2)th row, programming an Nth row. Even rows closer to the first row are programmed before even rows farther away from the first row.
    Type: Grant
    Filed: December 15, 2019
    Date of Patent: March 2, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhipeng Dong, Venkatagirish Nagavarapu, Haibo Li
  • Patent number: 10930355
    Abstract: A methodology and structure for accounting for fabrication difference in memory holes is described. Increasing the distance of the memory holes from the sources of etchant or other fabrication material results in different characteristics of the memory from the outer memory holes to the inner memory holes. These difference can be accounted for by grouping the memory holes and altering the parameters of the program or verify operations based on the groupings. The bitline voltage for the inner grouping can be less than the bitline voltage for the outer groupings. The sense timing can be greater for the outer groupings relative to the inner groupings. This can result in voltage threshold for the inner groupings and outer groupings overlying each other to improve memory performance.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 23, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng, Deepanshu Dutta
  • Patent number: 10923212
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10908986
    Abstract: Read operations are performed in a memory device which efficiently provide baseline read data and recovery read data. In one aspect, on-die circuitry, which is on a die with an array of memory cells, obtains recovery read data before it is requested or needed by an off-die controller. In another aspect, data from multiple reads is obtained and made available in a set of output latches for retrieval by the off-die controller. Read data relative to multiple read thresholds is obtained and transferred from latches associated with the sense circuits to the set of output latches. The read data relative to multiple read thresholds can be stored and held concurrently in the set of output latches for retrieval by the off-die controller.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Robert Ellis, Daniel Helmick
  • Patent number: 10910061
    Abstract: Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 2, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Mark Reiten
  • Patent number: 10909444
    Abstract: A computer-implemented method, the method comprising: in an initial setup of weights for a floating gate including rows, columns, and a separate input line: comparing a current weight to a desired weight; performing a feedback to the input line to set a voltage to change the floating gate field effect transistor (FET) threshold voltage (VT) and the current weight; and checking that the current weight is within a predetermined tolerance of the desired weight; and performing a stochastic pulse update on the floating gate based on the checking.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: February 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 10908842
    Abstract: A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 2, 2021
    Inventors: Eun Chu Oh, Younggeun Lee, Youngjin Cho, Jin-Hyeok Choi
  • Patent number: 10910067
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Patent number: 10910044
    Abstract: An apparatus includes a pair of memory cells configured to represent data using joint data states where one of the joint data states comprises an error-prone joint data state. The apparatus further includes an encoder configured to convert user data into joint data states according to a dual-cell gray-code encoding scheme in which the error-prone joint data state does not encode user data.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 2, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Masahiro Kano
  • Patent number: 10902923
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 10902934
    Abstract: A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Boh-Chang Kim
  • Patent number: 10896368
    Abstract: Numerous embodiments are disclosed for an analog neuromorphic memory system for use in a deep learning neural network. In one embodiment, the analog neuromorphic memory system comprises a plurality of vector-by-matrix multiplication systems, each vector-by-matrix multiplication system comprising an array of memory cells, a low voltage row decoder, a high voltage row decoder, and a low voltage column decoder; a plurality of output blocks, each output block providing an output in response to at least one of the plurality of vector-by-matrix multiplication systems; and a shared verify block configured to concurrently perform a verify operation after a program operation on two or more of the plurality of vector-by-matrix systems.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: January 19, 2021
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly
  • Patent number: 10891063
    Abstract: Methods of operating an electronic system include allocating a group of memory cells of a plurality of groups of memory cells having a particular rank of a plurality of ranks for storing data of a particular data level of a plurality of data levels, determining a need for an additional group of memory cells for storing data of the particular data level, moving or discarding data from a different group of memory cells storing data of a different data level of the plurality of data levels in response to determining the need for the additional group of memory cells for storing data of the particular data level, and allocating the different group of memory cells for storing data of the particular data level.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Carla L. Christensen, Avani F. Trivedi, Tracy D. Evans
  • Patent number: 10892015
    Abstract: In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 12, 2021
    Inventors: Kang-Bin Lee, Il-Han Park, Jong-Hoo Jo
  • Patent number: 10885988
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 5, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 10885990
    Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of the unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to the selected string which neighbors the unselected string.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xinlei Jia, Shan Li, Kaiwei Li, Jianquan Jia, Lei Jin, Kaikai You, Ying Cui, Yali Song, Wei Hou, Zhiyu Wang, Hongtao Liu
  • Patent number: 10885975
    Abstract: A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Larry J. Koudele, Bruce A. Liikanen
  • Patent number: 10878917
    Abstract: A memory system includes a semiconductor storage device and a memory controller for the semiconductor storage device. The semiconductor storage device includes a plurality of blocks including a plurality of memory cell transistors. The plurality of blocks includes a first block and a second block. The memory cell transistor in the first block stores data having a first number of bits during a first period and stores data having a second number of bits larger than the first number during a second period that begins after the first period ends.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshikazu Takeyama
  • Patent number: 10878902
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 10877504
    Abstract: A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 29, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Hassan Elwan
  • Patent number: 10877692
    Abstract: A memory system includes a plurality of first memory chips connected to a first bus, a plurality of second memory chips connected to a second bus, and a controller that is connected to the first and second buses and configured to execute a write operation by performing processes that include selecting one of the plurality of first memory chips based on first information including data reading speed information and/or data writing speed information for the plurality of first memory chips, and selecting one of the plurality of second memory chips based on second information including data reading speed information and/or data writing speed information for the plurality of second memory chips.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koichi Inoue
  • Patent number: 10878921
    Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kosuke Yanagidaira, Mario Sako
  • Patent number: 10872670
    Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ugo Russo, Violante Moschiano, William C. Filipiak, Andrea D'Alessandro
  • Patent number: 10866763
    Abstract: Apparatuses, systems, and methods are disclosed for dynamic read operations. A controller monitors one or more read statistics during a read operation for data of a non-volatile memory die. The controller determines whether one or more read statistics satisfy a threshold for a read operation. The controller dynamically modifies a read operation based on determining that one or more read statistics fail to satisfy a threshold.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 15, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eyall Shadmi, Omer Fainzilber
  • Patent number: 10860421
    Abstract: A memory system may include: a multi-level cell memory device; and a controller suitable for controlling the memory device, wherein the controller includes a processor suitable for searching for the last programmed word line in an open memory block when the memory system is powered up after a sudden power-off, and controlling sequential read operations on data of the memory device in a plurality of logical pages corresponding to the last programmed word line, wherein the processor ends the sequential read operations depending on whether error correction on sequentially read data fails, receives from a host the error correction-failed data and data on which the sequential read operations are not performed, and controls the memory device to program the received data.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyung-Bum Kim
  • Patent number: 10861536
    Abstract: A semiconductor memory device includes: a first memory cell transistor; a bit line electrically connected to a first end of the first memory cell transistor; a source line electrically connected to a second end of the first memory cell transistor; and a control circuit. When a read operation for reading read data from the first memory cell transistor is performed, the control circuit is configured to apply a first voltage to the bit line in a first period, apply a second voltage, higher than the first voltage, to the bit line, and also apply a third voltage, lower than the first voltage, to the source line in a second period subsequent to the first period, and sense a threshold voltage of the first memory cell transistor in a third period subsequent to the second period.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: December 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
  • Patent number: 10861561
    Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Elisha Halperin, Evgeny Blaichman, Amit Berman
  • Patent number: 10861554
    Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 8, 2020
    Assignee: Rambus Inc.
    Inventors: Brent S. Haukness, Ian Shaeffer, Gary Bela Bronner
  • Patent number: 10854274
    Abstract: Apparatuses, systems and methods for dynamic timing of row pull-down operations are described herein. When a word line is accessed, the row decoder may drive that word line to an active voltage, and then to an intermediate voltage. The row decoder may maintain that word line at the intermediate voltage until another word line in the same group of word lines as the accessed word line receives an access command, at which point the first word line is driven to an inactive voltage. For example, if the word lines are grouped by bank, then after an access to a first word line, the first word line may be maintained at the intermediate voltage until a second wordline in the same bank as the first word line is accessed. This may help to mitigate the effect on other nearby word lines of driving a word line to the inactive voltage.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Adam J. Grenzebach, Timothy B. Cowles, Beau D. Barry
  • Patent number: 10847231
    Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Chenrong Xiong, Fan Zhang, Naveen Kumar, Yu Cai
  • Patent number: 10847229
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory cell; a bit line and a word line, coupled to the memory cell; and a page buffer configured to perform a read operation on the memory cell, wherein the page buffer senses a program state of the memory cell as one of at least three program states by performing a first evaluation operation, a first sensing operation, a second evaluation operation, and a second sensing operation when one read voltage is applied to the word line during the read operation.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Wook Jo
  • Patent number: 10847230
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a memory string including memory cells including first to third memory cells, and a selection transistor connected to the memory cells, and first to third word lines that are connected to gates of the first to third memory cells of the memory string. The memory controller reads data of the first to third memory cells by applying first to third read voltages to the first to third word lines, respectively. The memory controller reads second data by applying a fourth read voltage to the second word line in parallel to processing of decoding first data, obtains likelihood information on the basis of the first data, the second data, and at least one of the third data and the fourth data, and decodes data on the basis of the likelihood information.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Ando, Shuou Nomura
  • Patent number: 10839907
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, the duration of a programming voltage can change as the number of cells to be programmed changes.
    Type: Grant
    Filed: August 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do