Dual PCI-X/PCI-E Card
A dual bus interface PCB includes a main chipset component, a first type bus interface connector, and a second type bus interface connector. The PCB can be configured at fabrication time to enable a variety of configurations for operation. Optionally, the PCB can also be provided at least one memory chip and a NIC (Network Interface Card) chip. By virtue of having a dual interface, the PCB can be used with either the first type or the second type bus. Furthermore, the dual interface PCB eliminates the need by chipset manufacturers to carry multiple PCB variations of the same product in order to support various bus interfaces. In one embodiment, the PCB is a dual PCI-X/PCI-E interface PCB.
Latest Broadcom Coporation Patents:
- Probing-based auto moding
- System and method of a television for providing information associated with a user-selected information element in a television program
- Frame Chaining for Bridged Traffic
- MANAGING DEVICES WITHIN A VEHICULAR COMMUNICATION NETWORK
- Digital to analog converter with reduced ringing
This application is a continuation of U.S. application Ser. No. 11/037,177, filed Jan. 19, 2005, which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention herein relates in general to a dual bus interface printed circuit board (PCB) and more particularly to a PCB provided with both a PCI-X (Peripheral Component Interconnect—Extended) bus interface and a PCI-E (Peripheral Component Interconnect—Express) bus interface.
2. Background Art
In the field of I/O Interconnect, PCI (Peripheral Component Interconnect) is a widely adopted I/O bus standard in a wide variety of computer platforms. To meet the growing demand for bandwidth by new applications, PCI has gone through several changes in the last decade leading to extension standards such as PCI-2.2 and PCI-X (PCI—Extended). These extension standards however are all built on the same architecture, protocols, signals, and connector as the conventional PCI, the reuse having been mainly supported by the combination of backward compatibility and the ease of migration from the conventional PCI to the newer standards.
The conventional PCI architecture is based on a multi-drop, parallel bus implementation, with one local bus being shared by multiple peripheral devices to communicate with the central processing unit (CPU). When first developed, the PCI architecture solved some of the limitations of the previous bus standards such as ISA (Industry Standard Architecture) and EISA (Extended ISA), by allowing direct access of peripheral devices to the CPU. However, with the exponential growth of CPU power, bus technology based on the conventional PCI architecture is becoming more and more a bottleneck to enhanced system performance. The main reason for that being that a shared bus technology suffers from a scalability problem, limiting the number of peripherals that can be efficiently supported by a system.
At its current state, the conventional PCI bus technology is theoretically very close to its practical limits, with only minor performance gains possible at large costs in form factor. It is for this reason therefore that the conventional PCI architecture is slowly giving way to a new standard known as the PCI-E (PCI—Express) standard.
The PCI-E architecture is based on a series of point-to-point connections, with each connection employing a packet-based transfer scheme and supporting bidirectional communication. To meet the varying bandwidth needs of different system components, PCI-E can be easily scaled from one to 32 lanes, with a single lane providing 250 MB/sec of dedicated bandwidth in each direction. In addition to providing ample bandwidth, PCI-E also supports advanced power management, hot plugging, and its packet-based transfer protocol allows for time dependent data delivery and quality of service arbitration for high priority data streams.
Although PCI-E clearly provides major performance improvements compared to the conventional PCI standard and its extensions (parallel PCI), serial PCI-E is not backward compatible with parallel PCI, and the shift from parallel PCI to PCI-E is likely to be a slow one. It is expected that parallel PCI will coexist in many platforms with PCI-E to support today's lower bandwidth applications, until a compelling need, such as a new form factor, causes a full migration to fully PCI-E systems.
Foreseeing the coexistence of PCI and PCI-E in future platforms, chip makers have been designing dual PCI-X/PCI-E chipsets that can be operated with either of the two bus standards. Currently available PCBs, however, are designed for use with only a single bus standard, providing a single bus connector per card. As a result, dual bus chipsets have to be mounted on multiple PCB variations to support the various bus interface types, denying the user the interface duality of the chipset component, and running higher fabrication costs to chipset manufacturers.
The likely coexistence of the PCI-X and the PCI-E bus standards in future computer platforms necessitates efficient solutions to ensure the interoperability of the two. As PCI-E is not backward compatible with the conventional PCI standard, of which PCI-X is an extension, chipset manufacturers currently resort to carrying multiple PCB variations of the same product in order to support various bus interfaces. This solution is clearly a costly and inefficient one from a fabrication process point of view.
What is needed therefore is a dual interface PCB card that provides both PCI-X and PCI-E functionality.
BRIEF SUMMARY OF THE INVENTIONThe present invention is directed to a PCB having multiple different bus interface connectors, and a chipset that supports the multiple bus interfaces. In an embodiment, the present invention includes a dual PCI-X/PCI-E interface PCB. As a result, the dual interface functionality of a PCI-X/PCI-E chipset can be fully taken advantage of by the user, operating the chipset on either a PCI-X or a PCI-E bus. Furthermore, chipset fabrication costs can be reduced as well as the fabrication process simplified, by the production of a single dual bus interface PCB instead of multiple board variations to support various bus interface types.
Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.
The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION OF THE INVENTION OverviewIn the example of
In another example embodiment, shown in
In the example of
In an embodiment, connector ports 150A or 150B are optionally attached to the PCB at the end of the fabrication process. The PCB configuration would have been determined then, and, connector ports 150A or 150B would be attached as necessary. In another embodiment, each of connector ports 150A and 150B include a set of 8 SATA/SAS (Serial Advanced Technology Attachment/Serial Attached SCSI) connector ports.
A mounting bracket 220B is attached to edge B of the PCB. The bracket 220B allows the PCB to be fixed from edge B to a computer system's case, such that PCI-X connector 120B can be inserted into a matching PCI-X slot on the computer system's motherboard.
In this example of
In
The PCB 100 can be used with either a PCI-X or a PCI-E bus interface. The switching from using one interface to using the other is achieved by transferring the mounting bracket from one edge to the other, rotating the PCB 180° degrees, and plugging the desired bus interface connector into a matching bus slot on the computer system's motherboard.
The present invention puts forward a novel solution in the form of a dual interface PCB. The dual interface PCB of the current invention is easily configurable at fabrication time, and can support a number of different variations.
While the invention is described herein in view of a dual PCI-X/PCI-E interface PCB, the scope of the invention should not be limited by the type of interfaces supported by the PCB. It also should be noted that the PCB layouts provided in the accompanying drawings have been presented by way of example only, and not limitation.
CONCLUSIONWhile specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present invention. It will be apparent to a person skilled in the pertinent art that this invention can also be employed in a variety of other applications.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims
1. A circuit board assembly, comprising:
- a circuit board;
- a first bus interface connector mounted to the circuit board, the first bus interface connector configured for a first interface protocol;
- a second bus interface connector mounted to the circuit board, the second bus interface configured for a second interface protocol;
- an integrated circuit chip mounted to the circuit board and configured to interface with at least one of the first and second bus interface connectors;
- a first connector port selectively coupled to the integrated circuit chip when the first bus interface connector is enabled; and
- a second connector port selectively coupled to the integrated circuit chip when the second bus interface connector is enabled.
2. The circuit board assembly of claim 1, wherein the circuit board is insertable into a motherboard by selectively inserting either the first or the second interface connector into a corresponding slot of the motherboard.
3. The circuit board assembly of claim 1, wherein the integrated circuit chip is mounted to a first surface of the circuit board, and wherein the first and second connector ports are mounted onto a second surface of the circuit board.
4. The circuit hoard assembly of claim 3, wherein the first and second connector ports are mounted in a central region of the second surface of the circuit board.
5. The circuit board assembly of claim 1, further comprising:
- a first set of signal traces routed from the integrated circuit chip to the first bus interface connector; and
- a second set of signal traces routed from the integrated circuit chip to the second bus interface connector.
6. The circuit board assembly of claim 1, wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-X) bus interface connector.
7. The circuit board assembly of claim 1, wherein the first and second connector ports comprise SATA/SAS connector ports.
8. The circuit board assembly of claim 1, further comprising:
- a memory chip mounted to the circuit board and coupled to the integrated circuit chip.
9. The circuit board assembly of claim 1, wherein the integrated circuit chip comprises a RAID controller.
10. The circuit board assembly of claim 9, wherein the first and second connector ports connect the RAID controller to an array of disk drives.
11. The circuit board assembly of claim 1, wherein the first bus interface connector and the second bus interface connector are mounted on opposite edges of the circuit board.
12. The circuit board assembly of claim 1, further comprising:
- a Network Interface Card (NIC) chip mounted to the circuit board and coupled to the integrated circuit; and
- an Ethernet connected mounted to the circuit board and coupled to the NIC chip.
13. The circuit board assembly of claim 1, wherein the first bus interface connector and the second bus interface connector are both enabled.
14. A circuit board assembly, comprising:
- a circuit board;
- a first bus interface connector mounted to the circuit board, the first bus interface connector configured for a first interface protocol;
- a second bus interface connector mounted to the circuit board, the second bus interface configured for a second interface protocol;
- a first connector port mounted to the circuit board, the first connector port enabled when the first interface protocol is used by the circuit board assembly; and
- a second connector port mounted to the circuit board, the second connector port enabled when the second interface protocol is used by the circuit board assembly.
15. The circuit board assembly of claim 14, further comprising:
- an integrated circuit chip mounted to the circuit board and configured to interface with at least one of the first and second bus interface connectors.
16. The circuit board assembly of claim 15, wherein the first connector port is coupled to the integrated circuit chip when the first interface protocol is used by the circuit board assembly, and wherein the second connector port is coupled to the integrated circuit when the second interface protocol is used by the circuit board assembly.
17. The circuit board assembly of claim 14, wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-E) bus interface connector.
18. A method of making a dual bus interface circuit board, comprising:
- mounting a first bus interface connector and a second bus interface connector onto opposite edges of a circuit board;
- mounting an integrated circuit chip on the circuit board;
- routing a first set of signal traces and a second set of signal traces from the integrated circuit chip to the first and second bus interface connectors, respectively;
- coupling a first connector port to the integrated circuit chip when the first bus interface connector is enabled; and
- coupling a second connector port to the integrated circuit chip when the second bus interface connector is enabled.
19. The method of claim 18, further comprising:
- selectively mounting resistors at first ends of at least one of the first and the second sets of signal traces to selectively enable at least one of the first and second bus interface connectors.
20. The method of claim 18, wherein the first bus interface connector comprises a Peripheral Component Interconnect-Extended (PCI-X) bus interface connector, and the second bus interface connector comprises a Peripheral Component Interconnect-Express (PCI-E) bus interface connector.
Type: Application
Filed: Sep 14, 2012
Publication Date: Mar 28, 2013
Applicant: Broadcom Coporation (Irvine, CA)
Inventor: Charles J. PURWIN (Litchfield, NH)
Application Number: 13/618,247