Abstract: A hub includes: a multi-function control unit; a microprocessor; at least one sharing port connected to the multi-function control unit, which controls the at least one sharing port to connect with a computing device; a USB audio control unit connected to the multi-function control unit; an audio processing module connected to the USB audio control unit and the microprocessor; a wireless module connected to the audio processing module and the microprocessor and used for wireless communication with a mobile device; and an audio input and output module connected to the audio processing module and the microprocessor, and including an audio cable jack used for connecting with an audio input and output device, and/or a built-in speaker and a microphone. The microprocessor controls the audio processing module to select and process audio signal sharing among the computing device, the mobile device, and the audio input and output device.

Abstract: Systems and/or methods for use in connection with digital downloading jukeboxes are provided. Such systems and/or methods may be used to provide enhanced communications capabilities, e.g., to registered users of jukeboxes. In certain exemplary embodiments, users may become registered users directly at a jukebox. Registered users also may, in certain exemplary embodiments, receive coupons for free plays, import playlists from hardware devices and/or software applications, receive special pricing when playing certain instances of media, play playlists in whole or in part, create and/or manage playlists directly at a jukebox, establish and manage connections with other registered users, etc. Still further, in certain exemplary embodiments, one or more channels may be predefined and/or set up for a jukebox.

Abstract: Embodiments of systems, devices, and methods relate to a modular diagnostics interface system. An example modular diagnostics interface system includes one or more insertable measurement boards configured to communicably couple with a backplane of a modular measurement rack, and configured to collect a measured current from a component of a beamline.

Abstract: An electronic component system includes a chassis that includes a body, an electrically isolated portion, and an insulator disposed between the electrically isolated portion and the body, wherein the insulator is comprised of a first electrically insulating material. The electronic component system further includes a first electronic component mounted to the electrically isolated portion, and a second electronic component mounted to the body and electrically connected to the first electronic component.

Abstract: Aspects relate to techniques for controlling signal voltage levels across a wired data link for data communication between apparatuses. A first device can advertise multiple supported signal voltage levels to a peer device connected by the wired data link. The devices can implement the same signal voltage level(s) or different signal voltage levels. The peer devices can compare and select a compatible signal voltage level for data communication. The first device can provide a signal voltage indication signal that is configurable to a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels can indicate that the first device can operate the data link at a plurality of signal voltages. In some examples, the wired data link can be a peripheral component interconnect express (PCIe) link.

Abstract: A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

Abstract: An information handling system may detect whether each one of a plurality of peripheral component interconnect express (PCIe) slots is populated or unpopulated, and update a PCIe bus configuration map to indicate whether each of the PCIe slots is populated. The system may also allocate PCIe bus resources to each of the PCIe slots based on the PCIe bus configuration map, wherein the allocating of the PCIe bus resources includes prioritizing populated PCIe slots over unpopulated PCIe slots.

Abstract: Disclosed are an electronic device, an expansion card assembly and a server device. The electronic device comprises a hard disk slot and the expansion card assembly. The expansion card assembly is arranged in the hard disk slot in a pluggable manner; the hard disk slot comprises a first type of interface and a second type of interface. The first type of interface is used for communicating with the hard disk, and the second type of interface is used for communicating with the expansion card assembly. Therefore, the expansion card assembly is expanded by means of the hard disk slot in the electronic device, so that the expansion requirement of the expansion card assembly is met.

Abstract: A communication device insertable into an external electronic device is provided.

Abstract: A PCIe switch working mode updating method and apparatus, an electronic device, and a computer-readable storage medium, which are applied to a controller. The PCIe switch working mode updating method includes: determining a required switch firmware version of a system according to system configuration information; determining the current switch firmware version according to the current port definition state of a PCIe switch; determining, according to the required switch firmware version and the current switch firmware version, whether a switch port reallocation operation needs to be executed; and under the condition that the switch port reallocation operation needs to be executed, sending, to the PCIe switch, a data file corresponding to the required switch firmware version, so that the PCIe switch updates a working mode according to the data file.

Abstract: A Voltage Regulator Module (VRM) includes a first voltage rail circuit board oriented in a first plane having formed therein a first plurality of conductors and configured to produce a first rail voltage, a second voltage rail circuit board oriented in a second plane that is substantially parallel to the first plane having formed therein a second plurality of conductors and configured to produce a second rail voltage. The VRM also includes a first capacitor circuit board oriented in a third plane that is substantially perpendicular to the first plane and a second capacitor circuit board oriented in a fourth plane that is substantially parallel to the third plane. The VRM includes a plurality of conductors intercoupling the first voltage rail circuit board, the first capacitor circuit board, the second voltage rail circuit board, and the second capacitor circuit board.

Abstract: A memory card identification method and a mobile device are provided. The memory card identification method includes: sending an initialization command of a first-type memory card communications protocol to a to-be-identified memory card; detecting whether there is a response in a command pin of the memory card; and identifying the memory card as a first-type memory card or a second-type memory card based on a response status of the command pin.

Abstract: A computer system includes symmetrical sets of motherboard serial channels which couple processor devices on a motherboard with a common serial link interface. The common serial link interface can be coupled with an endpoint device to establish symmetrical serial links between the endpoint device and the processor devices. The computer system can include a riser card which can be coupled with the serial link interface. The riser card can include an endpoint device interface and serial channels which can couple the processor devices with the endpoint device via symmetrical limited selections of the motherboard serial channels. The riser can include additional interfaces which can couple the processor devices with additional expansion devices.

Abstract: The present disclosure discloses a server management framework and a server. The server management framework includes: a management board, wherein the management board comprises a baseboard management controller, a platform controller hub, and a management board complex programming logic device (CPLD), and a first end of the management board CPLD is connected to the platform controller hub; and a motherboard, wherein the motherboard comprises a central processing unit and a motherboard CPLD, a first end of the motherboard CPLD is connected to the central processing unit, and a second end of the motherboard CPLD is connected to a second end of the management board CPLD, so that the baseboard management controller communicates with the management board CPLD through the motherboard CPLD, and the platform controller hub communicates with the baseboard management controller through the motherboard CPLD and the management board CPLD.

Abstract: An instruction simulation device and a method thereof are provided. The simulation device includes a monitor, which is configured to determine whether a ready-for-execution instruction is an instruction under a new/extended instruction set sharing the same instruction set architecture as that of the processor. If the ready-for-execution instruction is an extended instruction, it is converted into a simulation program which consists of a compatible instruction sequence further composed of at least one native instruction of the processor or a compatible instruction recognizable/executable by the processor. An execution result of the extended instruction is simulated by executing the simulation program, thereby extending the service life of an electronic appliance embodied with the disclosed simulation device therein.

Abstract: The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.

Abstract: A method of automatic identification of PCIe configuration of a server and preventing operation if each slimline connector connected with a PCIe device is found connected to an incorrect slot of a mother board utilizes a combination of first and second signals of two null interfaces of the first connector as that ID signal and a combination of third and fourth signals of the two interfaces of a second connector as that ID signal. The CPLD receiving the ID signals detects whether the first and second slimline connectors are in their specified and correct slots. Powering on of computer is not permitted if incorrect connection is found, and a warning prompt is generated. A PCIe channel width for each slimline is automatically configured if no incorrect connection is found. A server applying the method is also disclosed.

Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Abstract: Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.

Abstract: A computer may receive a request to generate a snapshot view of the enterprise network infrastructure. The computer may implement a multithread process to contemporaneously query a plurality of blade servers and server enclosures within the entire network infrastructure. The computer may contemporaneously receive a plurality of information files from the queried network resources (e.g. the blade servers, server enclosures). In active state modes, the computer may push firmware update binaries to the network resources. In a server processing and an active state mode, the computer may implement a multithreaded process to push the firmware update binaries to standalone servers or blade servers that can be accessed directly. In a blade enclosure processing and an active state mode, the computer may implemented a nested multi-threader, using child threads nested within a parent thread to a blade server enclosure to push firmware update binaries to blade servers in the enclosure.

Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

Abstract: A mother board with a central processing unit and two riser slots configured to cooperate with one riser card for connecting two expansion cards to the mother board. The first riser slot and the second riser slot may be connected by metal traces to the central processing unit, and the two riser slots may be spaced apart by a distance greater than 8 cm.

Abstract: Method, systems and apparatuses may provide for technology that extracts one or more motion features from filtered position data associated with a projectile in a game and identifies a turning point in a trajectory of the projectile based on the one or more motion features. The technology may also automatically designate the turning point as a highlight moment if one or more of the turning point or the trajectory satisfies a proximity condition with respect to a target area in the game.

Abstract: Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes coupling into a communication fabric a plurality of communication interfaces provided by a baseboard hosting a plurality data processing devices. The method includes establishing a one-hop latency in the communication fabric between the plurality of data processing devices and peripheral card slots, and establishing a two-hop latency in the communication fabric between the plurality of data processing devices and additional peripheral card slots. The method also includes establishing interconnect pathways between a plurality of communication switches that provide the one-hop latency through one or more cross-connect communication switches that provide the two-hop latency.

Abstract: A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

Abstract: In one example, an adapter card may include a circuit board having a male interface to be inserted into a discrete graphics card slot and a peripheral component interconnect express (PCIe) slot to communicatively couple a PCIe device. Further, the adapter card may include a voltage converter circuit disposed on the circuit board to convert a first voltage associated with the discrete graphics card slot to a second voltage corresponding to the PCIe device and a level shifter circuit disposed on the circuit board to modify a signal level in the discrete graphics card slot to a signal level in the PCIe device.

Abstract: Example implementations relate to route demultiplexed signal pairs. In some examples, a motherboard of a computing device can include a chipset, a first Peripheral Component Interconnect Express (PCIe) bus, a second PCIe bus, a riser slot, and a demultiplexer connected to the chipset to selectively route particular signal pairs from the chipset to at least one of the first PCIe bus, the second PCIe bus, and the riser slot based on whether a riser card is connected to the riser slot.

Abstract: A system and a method of interface communication being compatible with SFP+ optical modules and QSFP+ switch are provided. The system includes an adapter card. The adapter card includes a set of SFP+ golden fingers that comply with the SFP+ protocol, a set of QSFP+ golden fingers that comply with the QSFP+ protocol, and a microcontroller unit. The adapter card communicates with the SFP optical module through the SFP+ golden fingers, and communicates with the QSFP switch through the QSFP+ golden fingers. The microcontroller unit is used to extend and process the pin information in the adapter card, and to convert the two different protocols of SFP+ and QSFP+, so that the module under the SFP+ protocol can respond under the port of QSFP+, so as to realize the data communication between the SFP+ optical module and the QSFP+ switch.

Abstract: A mobile ticketing module includes: a terminal interface able to interact with a ticketing terminal; and a communication module comprising at least one antenna able to interact with a user device. A payment processing system includes: a ticketing terminal; a consumer interaction module communicatively coupled to the ticketing terminal; and a server communicatively coupled to the consumer interaction module. An automated method of processing payment requests, the method includes: receiving, at a consumer interaction module, a payment request from a ticketing terminal; sending the payment request to an authorization server; receiving a response from the authorization server; sending the response to the ticketing terminal; and receiving, at the consumer interaction module, a ticket. The consumer interaction module may be able to interact with various mobile device applications. The module may facilitate payment processing, administration of loyalty programs, advertising, and micro positioning.

Abstract: A medical system may utilize a modular and extensible sensing device to derive a two-dimensional (2D) or three-dimensional (3D) human model for a patient in real-time based on images of the patient captured by a sensor such as a digital camera. The 2D or 3D human model may be visually presented on one or more devices of the medical system and used to facilitate a healthcare service provided to the patient. In examples, the 2D or 3D human model may be used to improve the speed, accuracy and consistency of patient positioning for a medical procedure. In examples, the 2D or 3D human model may be used to enable unified analysis of the patient's medical conditions by linking different scan images of the patient through the 2D or 3D human model. In examples, the 2D or 3D human model may be used to facilitate surgical navigation, patient monitoring, process automation, and/or the like.

Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.

Abstract: A method and a control chip for performing access control of a memory device are provided, wherein the control chip is coupled to a host device. The method includes: utilizing a first transmission interface of the control chip to determine whether the memory device supports a second transmission interface different from the first transmission interface to generate a determination result; and according to user permissions of a user regarding the host device, determining whether to allow the control chip to decide whether to utilize the second transmission interface to access the memory device based on the determination result. In addition, if the user permissions satisfy a predetermined condition, a user interface of the host device may display a pop-up window in order to allow the user to decide which one of the first transmission interface and the second transmission interface to utilize for accessing the memory device.

Abstract: An memory subsystem of an information handling system includes a memory module and a controller. The memory module includes a Registering Clock Driver (RCD) configured to receive a clock signal. The RCD includes a delay setting and a clock delay circuit to provide a selectable delayed clock signal based upon the delay setting. The memory module further includes a power management integrated circuit (PMIC) with a plurality of switching regulators. The PMIC receives the delayed clock signal and clocks the switching regulators based upon the delayed clock signal. The controller sets the first delay setting.

Abstract: In general, in one aspect, the invention relates to a method for processing data, the method includes obtaining, by a host operating system (OS) on a host computing device, a notification of a power down. The further includes, in response to the notification, performing a data storage analysis on data stored in host OS memory to identify a plurality of processing tasks to perform on the data, making a first determination, based on the data storage analysis, that data processing is to be offloaded to a graphics processing unit, and in response to the first determination: sending a data processing request to the processing unit, obtaining a second notification associated with processed data from the graphics processing unit, and storing the processed data in a backup storage device.

Abstract: A dual interface transaction card includes a metal card body having first and second surfaces. A contact-only transaction module is secured in the card body, the contact-only transaction module including contact pads disposed on the first surface of the card body and including a first transaction circuit. A contactless transaction module is secured in a void in the metal card body. The contactless transaction module includes a second transaction circuit and an antenna. Also disclosed is a process for manufacturing the dual interface transaction card. The process includes the steps of constructing a metal card body having the first and second surfaces, securing the contact-only transaction module in the metal card body, forming the void in the metal card body, and securing the contactless transaction module in the void.

Abstract: A device can include a processor; memory; a display; a bezel that defines a bezel region and a display region for the display; one or more media capture components where the one or more media capture components include a camera operatively coupled to the processor, where the camera includes an aperture disposed in the bezel region; a switch that includes an operational state for a circuit electrically coupled to the at least one of the one or more media capture components and a nonoperational state for the circuit; and a movable shutter that controls the switch, where the movable shutter includes a closed orientation that obscures a field of view of the camera and that corresponds to the nonoperational state of the switch and an open orientation that does not obscure the field of view and that corresponds to the operational state of the switch.

Abstract: A projector includes: a determination unit determining whether a daisy chain function executed by the projector when daisy-chained to another device is set as enabled or not; and a setting unit setting a display source to which an image signal to be a source of an image displayed by the projector is inputted, to one of the plurality of interfaces. The setting unit sets a supporting interface supporting the daisy-chaining as the display source when it is determined by the determination unit that the daisy chain function is set as enabled. The setting unit does not change the display source to an interface other than the supporting interface even when the image signal is not inputted to the supporting interface.

Abstract: A dual-connector storage system and method for simultaneously providing power and memory access to a computing device are provided. In one embodiment, the storage system comprises a memory, a first connector, a second connector, and a controller. The controller is configured to provide power received from the second connector to a computing device connected with the first connector while also allowing the computing device to access the memory via the first connector. Other embodiments are provided.

Abstract: An aggregated performance reporting system includes a computing system in communication with a database that stores element records associated with the elements of a distributed computing environment. The computing system stores instructions that are executed to receive a search term from a user interface, and identify a count of each element type that matches the search term. The instructions then identify one or more aggregated performance indicators that are associated with each element type, issue a request to the database to retrieve those element records having the identified element types, calculate the aggregated performance indicators using parametric information included in the retrieved element records, and facilitate the display of the calculated aggregated performance indicators on a display.

Abstract: A modular controller includes an enclosure having an interior, a motherboard with a signal trace and a power trace supported within the interior of the enclosure, and one or more control section. The control section includes one or more of an input power section, an electromagnetic interference section, a logic section, a control section, a output power section, and a signal section that is supported by the motherboard to selectively flow of electrical power through the power trace using a control signal carried by the signal trace. Electrical systems and methods of making modular controllers are also described.

Abstract: A USB device and an operation method thereof are provided. The USB device includes a first switch, a second switch, a power converter, and a first USB connector. A first terminal of the first switch is configured to receive a first voltage. The power converter is configured to provide a second voltage, and the second voltage is less than the first voltage. A first terminal of the second switch is coupled to the power converter to receive the second voltage. A first power pin of the first USB connector is coupled to a second terminal of the first switch and a second terminal of the second switch.

Abstract: In accordance with some embodiments, an apparatus for privacy protection includes a peripheral interface connectable to a second device. In some embodiments, the second device is operably connectable to a personal communication device and the peripheral interface provides characteristics of communication signals associated with the personal communication device to the second device. The apparatus also includes a radio frequency (RF) detection device operable to detect energy carrying a communication signal to or from the personal communication device.

Abstract: Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

Abstract: An electronic system capable of detecting a number of hot-plug insertion/extraction cycles including a host device, at least one peripheral device, and at least one storage device is provided. The host device includes a controller and at least one connection socket. The controller has at least one detection pin. Each connection socket is coupled to a corresponding detection pin. The peripheral device includes at least one connector. The connector is hot-pluggably and electrically connected to the connection socket of the host device. The storage device stores the number of hot-plug insertion/extraction cycles of the connector in the peripheral device. When the connector of the peripheral device is connected to the connection socket of the host device, the controller reads the number of hot-plug insertion/extraction cycles from the storage device and increases the number of hot-plug insertion/extraction cycles of the connector in the peripheral device.

Abstract: A system and method are described for configuring a motherboard using expansion cards plugged into motherboard slots. In particular, each of the expansion cards can include a control signal that is supplied to the motherboard and that can configure hardware positioned on the motherboard. In one embodiment, the configuration allows a communication path to be switched on to allow the expansion cards to cross communicate.

Abstract: An information handling system includes processors disposed in sockets, and interconnect links providing point-to-point links between the sockets. One of the processors determines an arrangement of the processors, memories and the interconnect links, and determines a value for each of the processors, each of the memories, and each of the interconnect links. The processor calculates interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links. The processor also populates an interconnect bandwidth table using the interconnect link bandwidth values.

Abstract: A power storage adapter coupled to a portable information handling system using a variable power bus may receive first battery data from an embedded controller of the portable information handling system. The first battery data may be used by a battery management unit in the power storage adapter for power management of a battery. The power storage adapter may also collect second battery data from other portable information handling systems and send the second battery data back to the embedded controller.

Abstract: A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.

Abstract: A risk assessment system and method are provided that may be implemented as an embedded hardware based system and method that provide real-time pre-trade risk assessments for multiple parties, in addition to real-time market data and trading connectivity to a variety of liquidity venues. The liquidity venues may include regulated exchanges, ECNs and other financial institutions listing securities, options, futures, commodities, foreign exchange and other financial instruments.