CHANNEL ESTIMATION BASED ON NOISE POWER

Abstract

Disclosed are various embodiments providing processor configured to determine a received signal strength indication (RSSI) value for each of the plurality of channel taps. The processing circuitry identifies a maximum RSSI value among the RSSI values and may adjust a variable threshold range according to the maximum RSSI value. The RSSI value for each channel tap may be scaled according to a corresponding per tap noise power.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a utility application that claims priority to co-pending U.S. Provisional Patent Application entitled, “Cellular Baseband Processing”, having Ser. No. 61/618,049, filed Mar. 30, 2012, which is entirely incorporated herein by reference.

BACKGROUND

In radio communication, such as those facilitated by cellular networks, channel characteristics of a signal received by a receiver may vary with time. Lock target selectors are commonly used in such communication systems to select a target that a delay lock loop (DLL) is configured to track. With these varying channel conditions, a DLL may attempt to lock to a channel tap to facilitate receiving data from a transmitter associated with, for example, a base station.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a drawing of an example of processing circuitry for implementing at least a portion of a wireless communication system, in accordance with various embodiments of the present disclosure.

FIG. 2 is a diagram of an example of a plurality of channel taps implemented in the processing circuitry of FIG. 1, in accordance with various embodiments.

FIG. 3 is a diagram of an example of a plurality of channel taps implemented in the processing circuitry of FIG. 1, in accordance with various embodiments.

FIG. 4 is a flowchart illustrating examples of functionality implemented as portions of logic in the processing circuitry of FIG. 1 according to various embodiments of the present disclosure.

FIG. 5 is a flowchart illustrating examples of functionality implemented as portions of logic in the processing circuitry of FIG. 1 according to various embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure relates to systems and methods for determining whether to lock to a channel tap in a receiving device of a wireless communication system. In a wireless communication system, signals are transmitted from a transmission station and received via an antenna at a receiving device. A signal received in the wireless communication system may be, for example, a multipath signal. A multipath signal may be a wireless signal that reaches an antenna using a plurality of paths. For example, a wireless signal may be subjected to reflection, refraction, or any other physical interference that causes a wireless signal to propagate through multiple paths.

A receiving device may use a receiving antenna to receive a multipath signal. Furthermore, the receiving device may employ a set of channel taps to receive a multipath signal. Channel taps may be configured to lock to portions of the received multipath signal. In various embodiments of the present disclosure, determining whether to lock to a multipath signal by a particular channel tap may be made based on considering a channel tap power as well as a noise power associated with the received multipath signal. Furthermore, when determining whether to lock to a particular signal, a variable threshold may be used.

Reference is made to FIG. 1 which illustrates an example of processing circuitry for implementing at least a portion of a wireless communication system, in accordance with various embodiments of the present disclosure. Specifically, the non-limiting example of FIG. 1 depicts a wireless communication system 102. The wireless communication system 102 includes an antenna 104, a radio frequency (RF) front-end unit 106, processing circuitry 111, and other components for facilitating receiving signals over the wireless communication system 102.

The RF front-end unit 106 includes circuitry for receiving data via the antenna 104. The RF front-end 106 performs operations such as filtering, strengthening of signals, and conversion of signals where conversion may include such operations as analog-to-digital conversion, down-conversion, and so forth. Information is modulated in the received signal, and the same information in a given transmission may be communicated over different channels due to different paths by each respective signal. To this end, a wireless multipath signal may be received by the antenna 104 and converted into the digital domain for processing a digitally formatted multipath signal 108.

The multipath signal 108 of the RF front-end unit 106 is forwarded to the processing circuitry 111. In various embodiments, the processing circuitry 111 is implemented as at least a portion of a microprocessor. The processing circuitry 111 may be implemented using one or more circuits, one or more microprocessors, application specific integrated circuits, dedicated hardware, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, or any combination thereof. In yet other embodiments, the processing circuitry 111 may include one or more software modules executable within one or more processing circuits. The processing circuitry 111 may further include memory configured to store instructions and/or code that causes the processing circuitry 111 to execute data communication functions.

In various embodiments, the processing circuitry 111 may be a cluster path processor for supporting channel estimation processes. The processing 111 circuitry may be configured to conform to any number of wireless communication protocols such as, for example, Wideband Code Division Multiple Access (WCDMA), High-Speed Data Packet Access (HSDPA), etc. The processing circuitry 111 may be configured to implement multipath tracking/management using a delay locked loop (DLL), channel estimation, timing generation, timing alignment for downlink transmit diversity, multipath received signal strength indicator (RSSI) measurements, lock detection, or any combination thereof.

The processing circuitry 111 may comprise a plurality of channel taps 116. The plurality of channel taps 116 may be configured to receive the multipath signal. Each channel tap 116 may be associated with lock circuitry 121 for determining whether to configure a corresponding channel tap 116 to lock to at least a portion of the received multipath signal 108. By locking to portions of the multipath signal 108, the processing circuitry 111 facilitates receiving information transmitted wirelessly over the wireless communication system 102.

In various embodiments of the present disclosure, lock circuitry 121 comprises a plurality of components for determining whether to set the corresponding channel tap 116 to a lock status or to an unlock status. Lock circuitry 121 may comprise a descrambler/despreader 132, a channel estimation filter 135, a power estimation block 139, an RSSI filter 142, a noise power estimator 145, a lock detector 148, and other components.

A descrambler/despreader 132 may be configured to descramble and despread signals associated with a corresponding channel tap 116. In performing the descrambling and despreading operations, each chip of the signal is descrambled and despread such that descrambled/despread chips are accumulated over the spreading interval. The despreader operation may produce channel symbols from signals associated with the corresponding channel tap 116 by descrambling and then despreading the signal using channel spreading sequences and one or more scrambling codes.

The channel estimation filter 135 generates the instant channel estimation for each tap. The filter is designed based on channel conditions such as, for example, a degree of Doppler effect, interference, a signal-to-noise power ratio, any other channel characteristic, or any combination thereof. In various embodiments, the channel estimation filter 135 comprises a low pass filter. In some embodiments, the channel estimation filter 135 may comprise a single-pole filter that conforms to the following equation:

y_n=α·x_n+(1+α)·y_n−1

With reference to the equation above, y_n represents the output of the channel estimation filter 135, x_n represents the input to the channel estimation filter 135, α represents a predetermined constant associated with the channel estimation filter 135, and y_n represents the previous output of the channel estimation filter 135. The output of the channel estimation filter 135 may comprise one or more complex components such as, for example, an in phase (I) component and a quadrature phase (Q) component.

The power estimation block 139 may be configured to generate a power estimation based on the output of the channel estimation filter 135. In various embodiments, a power estimation block 139 operates on a complex sample associated with the output of the channel estimation filter 135. For example, the power estimation block 139 may generate a signal power estimation that is modeled as I²+Q².

RSSI filter 142 may receive the output of the power estimation block 139 for generating an RSSI signal associated with a corresponding channel tap 116. The RSSI signal may comprise a value that indicates a power measurement associated with the corresponding channel tap 116. The RSSI filter may comprise a low pass filter. In some embodiments, the RSSI filter 142 may conform to the following equation:

y_n=β·x_n+(1+β)·y_n−1

With reference to the equation above, y_n represents the output of the RSSI filter 142, x_n represents the input to the RSSI filter 142, β represents a predetermined constant associated with the RSSI filter 142, and y_n represents the previous output of the RSSI filter 142. To this end, each channel tap 116 may be associated with a corresponding RSSI signal, where the corresponding RSSI signal expresses an estimated power of the corresponding channel tap 116.

According to various embodiments, the RSSI filter 142 is configured to round its output according to a predetermined number of digits. Rather than truncating an output that is expressed as an irrational number, which may result in a direct current bias, rounding an output may result in more optimal processing. Furthermore, coefficients associated with the RSSI filter 142 may also be rounded to a predetermined number of digits.

The lock circuitry 121 may further comprise a noise power estimator 145. The noise power estimator 145 may be configured to generate an estimated noise power associated with a corresponding channel tap 116. In various embodiments, the noise power estimator provides a per channel tap noise power estimation based on the output of the corresponding descrambler/despreader 132. For example, the noise power estimator 145 may generate a noise power estimation by subtracting a pair of consecutive output symbols from the output of the descrambler/despreader 132 for calculating the noise power. Furthermore, the noise power estimator 145 may then accumulate one or more chip symbols.

The noise power estimator 145 may be further configured to adjust the output of the RSSI filter 142 based on the noise power estimation. For example, the noise power estimator 145 may scale or otherwise normalize the RSSI signal based on the noise power estimation for the corresponding channel tap 116 or set of channel taps 116.

The lock circuitry 121 may comprise a lock detector 148 for determining whether to set a corresponding channel tap 116 to a lock status or to an unlock status. In various embodiments, the lock detector 148 compares the output of the RSSI filter 142 to a predetermined threshold range. Moreover, the output of the RSSI filter 142 may be scaled according to a noise power estimation associated to a corresponding channel tap 116.

The lock circuitry 121 may comprise a preset threshold range for determining whether to set a particular channel tap 116 to a lock or unlock status. In various embodiments, the preset threshold range may be adjusted or otherwise replaced by a variable threshold 151. The variable threshold 151 may be determined based on an RSSI value generated from the RSSI filter 142, as is discussed in further detail below.

Next, a general description of the operation of the various components of the wireless communication system 102 is provided. The processing circuitry 111 receives a multipath signal 108, where a set of channel taps 116 are configured to process portions of the multipath signal 108. Each channel tap 116 may lock to the multipath signal 108 depending on channel characteristics associated with the channel tap 116. In determining whether to lock the multipath signal 108, the channel tap 116 employs lock circuitry 121. The lock circuitry 121 may be configured to ultimately set a lock status or an unlock status for a corresponding channel tap 116.

The lock circuitry 121 generates a one or more symbols associated with a channel tap output using a descrambler/despreader 132. These symbols may be passed through a channel estimation filter 135 and a power estimation block 139. Accordingly, an RSSI signal may be generated by an RSSI filter 142 for determining an RSSI value associated with the corresponding channel tap 116. RSSI value may reflect a power and/or energy associated with the corresponding channel tap 116. In various embodiments, the power and/or energy of a particular channel tap 116 may be used as a basis for determining whether to configure a particular channel tap 116 to lock to a multipath signal 108.

Furthermore, a noise power value may be determined for the corresponding channel tap 116. For example, a noise power estimator 145 may determine a noise power based on one or more symbols of a particular channel tap 116. In various embodiments of the present disclosure, the noise power value may be used as a basis for determining whether to configure a particular channel tap 116 to lock to a multipath signal 108. In other embodiments, a combination of the power/energy of a particular channel tap 116 and the noise power of the particular channel tap 116 is used to determine whether to set the particular channel tap 116 to a lock status.

For example, the RSSI signal, which correlates to the power of a particular channel tap 116, may be scaled according to the noise power of the particular channel tap 116. Accordingly, various embodiments of the present disclosure are directed to using a per tap metric that comprises an RSSI value that is scaled according to the noise power for the tap.

A lock detector 148 may determine whether to set a corresponding channel tap 116 to a lock status or to an unlock status based on the RSSI value for the tap or based on the noise-scaled RSSI value for the tap. In various embodiments, a relative or variable threshold range 151 may be used such that the variable threshold range 151 is determined based on a plurality of RSSI values associated with the set of channel taps 116. RSSI values are determined for corresponding channel taps 116 for generating a set of RSSI values. A maximum RSSI value may be selected from the set of RSSI values. The variable threshold 151 may be based at least in part upon the maximum RSSI value. For example, a lock detector 148 may be associated with a preset threshold range. This preset threshold range may be scaled or otherwise modified according to the maximum RSSI value for determining a variable threshold range 151.

In various embodiments, RSSI filter 142 associated with each channel tap 116 determines an RSSI value for identifying a maximum RSSI value among the plurality of channel taps. The maximum RSSI value and/or variable threshold range 151 may be stored in a memory included in the processing circuitry 111. The lock detector 148 may read from the memory for applying the variable threshold range 151. In other embodiments, the variable threshold range 151 may be determined based on a noise-scaled RSSI value. To this end, the maximum noise-scaled RSSI value across a set of channel taps 116 may be used to adjust the variable threshold range.

Moving on to FIG. 2, shown is an example of a plurality of channel taps 116 implemented in the processing circuitry 111 of FIG. 1, in accordance with various embodiments. The non-limiting example of FIG. 2 illustrates channel characteristics associated with a set of channel taps 116. Based on various channel characteristics, the processing circuitry 111 may determine whether to configure a particular channel tap 116 to lock to a multipath signal 108 (FIG. 1).

A multipath signal 108 may be received by a set of channel taps 116. Depending on the configuration of each channel tap 116, each channel tap 116 receives at least a portion of the multipath signal 108 according to a channel tap signal power 215 and a channel tap noise power 228. In this respect, a signal power 215 and a noise power 228 affect the input into a particular channel tap 116. As seen in the non-limiting example of FIG. 2, a signal power 215 varies across the set of channel taps 116. The noise power 228 may also independently vary across a set of channel taps 116. Based on at least the signal power 215 and the noise power 228, a decision may be made by the processing circuitry 111 whether to lock a particular channel tap 116 to a multipath signal 108.

As seen in the non-limiting example of FIG. 2 channel tap 2 is associated with the highest channel tap signal power 215 while channel tap 0 is associated with the lowest channel tap signal power 215. Channel tap 0 and channel tap n may correspond to a relatively large noise power 228. Channel tap 1 may correspond to a relatively medium noise power 228 while channel tap 2 may correspond to a relatively low noise power 228.

The signal power 215 associated with each channel tap 116 may correlate to a corresponding RSSI value. In this respect, the RSSI measurement comprises an estimation for a channel tap signal power/energy 215. In various embodiments of the present disclosure, an RSSI value is determined for each channel tap 116 by an RSSI filter 142 (FIG. 1) that is implemented as a portion of the processing circuitry 111. To this end, a set of RSSI values are determined for a set of channel taps 116 for a particular period of time. The processing circuitry 111 is configured to identify or select the maximum RSSI value 234 associated with the set of channel taps 116. The maximum RSSI value 234 approximates the largest channel tap power 215 associated with the set of channel taps 116.

In various embodiments of the present disclosure, the maximum RSSI value 234 is used to adjust a variable threshold range 151 (FIG. 1) used by a lock detector 148 (FIG. 1), as is discussed in further detail with respect to at least FIG. 3.

Turning to FIG. 3, shown is an example of a plurality of channel taps 116 implemented in the processing circuitry 111 of FIG. 1, in accordance with various embodiments. The non-limiting example of FIG. 3 illustrates the use of RSSI signals/values associated with the set of channel taps 116 to adjust a variable threshold 151. FIG. 3 alternatively provides a non-limiting example of using a noise-scaled RSSI value for adjusting the variable threshold 151. Furthermore, the non-limiting example of FIG. 3 depicts determining whether to set a channel tap 116 to a lock status or unlock status based on a variable threshold range 151 used by a lock detector 148 (FIG. 1).

For each channel tap 116, an RSSI signal that expresses a signal power 215 (FIG. 2) for the channel tap 116 may be determined. Furthermore, a noise power 228 (FIG. 2) may be estimated for each channel tap 116. Based at least upon an RSSI signal and a noise power, a noise-scaled RSSI signal may be determined for each channel tap 116. For example, an RSSI signal for a particular channel tap 116 may be scaled according to the corresponding noise power estimation for the particular channel tap 116. Thus, in some embodiments, a noise-scaled RSSI signal is generated by the processing circuitry 111. In alternative embodiments, a non-scaled RSSI is generated by the processing circuitry 111.

The non-limiting example of FIG. 3 depicts a set of channel taps 116 where each channel tap 116 corresponds to a per tap metric 306. In various embodiments, the per tap metric 306 comprises an estimated RSSI value (e.g., non-scaled RSSI value) for the corresponding channel tap 116. In alternative embodiments, the per tap metric 306 comprises a noise-scaled RSSI value for the corresponding channel tap 116. For example, channel tap 2 is associated with the largest per tap metric 306. A large per tap metric 306 indicates that channel tap 2 is associated with a relatively large signal power 215, a relatively small noise power 228, or any combination thereof. Furthermore, as seen in the non-limiting example of FIG. 3, channel tap n has a relatively small per tap metric 306 based on the fact that channel tap n is associated with a relatively high noise power 228 and/or tap n is associated with a relative low signal power 215.

The non-limiting example of FIG. 3 further illustrates various embodiments of the present disclosure directed to adjusting a variable threshold range 151. The processing circuitry 111 may be associated with a preset upper threshold and a preset lower threshold for determining a preset threshold range. According to various embodiments, the preset upper threshold may be scaled according to the maximum RSSI value 234 (FIG. 2) for determining a relative upper threshold 312. For example, the relative upper threshold 312 may be determined by multiplying the maximum RSSI value 234 with a predetermined multiplier or by offsetting the maximum RSSI value 234 by a predetermined value. To this end, the relative upper threshold 312 may be set to the maximum RSSI value 234 minus an offset value. Similarly, the preset lower threshold may also be scaled according to the maximum RSSI value 234 for determining a relative lower threshold 315. Various embodiments are not limited to using the maximum RSSI value 234 for determining a relative upper threshold 312 and relative lower threshold 315. For example, a maximum noise-scaled RSSI value may be used. That is to say, the maximum value among the set of noise-scaled RSSI values for a corresponding set of channel taps 116 may be used to determine a variable threshold 151.

Accordingly, in response to determining a maximum RSSI value 234, a threshold range may be adjusted, updated, or otherwise modified for generating a variable threshold 151. In various embodiments, the variable threshold 151 is adjusted for each time the maximum RSSI value 234 is calculated or a maximum noise-scaled RSSI value is calculated. For example, the maximum RSSI value 234 may be calculated on a per slot basis or calculated after accumulating a predetermined number of chips/symbols associated with a channel tap 116.

Furthermore, the non-limiting example of FIG. 3 depicts a portion of the operation of a lock detector 148 that is configured to be executed in the processing circuitry 111. The lock detector 148 is configured to set/maintain a lock status or unlock status for a corresponding channel tap 116. For example, the lock detector 148 compares the per tap metric 306 for each channel tap 116 to a predetermined threshold range, such as, for example, the variable threshold range 151.

If, the per tap metric 306 of a particular channel tap 116 falls below the variable threshold range 151, then the lock detector 148 sets the status of the channel top 116 to unlock. If the per tap metric 306 of a particular channel tap 116 falls above the variable threshold range 151, then the lock detector 148 sets the status of the channel top 116 to lock. If the per tap metric 306 of a particular channel tap 116 falls within the variable threshold range 151, then the lock detector 148 holds the previous lock status. For example, if the status of the channel tap 116 was previously set to unlock, then the lock detector 148 maintains the unlock status of the channel tap 116.

As seen in the non-limiting example of FIG. 3, channel tap 0 and channel tap n are both associated with per tap metrics 306 that fall below the relative lower threshold 315 such that the per tap metrics are below the variable threshold amount 151. Accordingly, the lock detector 148 responds by setting channel taps 0 and n to an unlock status. Channel tap 2 is associated with per tap metric 306 that exceeds a relative upper threshold 312 such that the per tap metric 306 is above the variable threshold amount 151. Accordingly, the lock detector 148 responds by setting channel taps 2 to a lock status. Channel tap 1 is associated with per tap metric 306 that is within the variable threshold amount 151. Accordingly, the lock detector 148 holds the current status of channel tap 1. Thus, the status does not change and channel 1 continues to either be set to lock or unlock, depending on the previous status.

Referring next to FIG. 4, is a flowchart illustrating examples of functionality implemented as portions of logic in the processing circuitry 111 of FIG. 1 according to various embodiments of the present disclosure. It is understood that the flowchart of FIG. 4 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the processing circuitry 111 as described herein. As an alternative, the flowchart of FIG. 4 may be viewed as depicting an example of steps of a method implemented in the processing circuitry 111 according to one or more embodiments. Specifically, the flowchart of FIG. 4 provides a non-limiting example of determining whether to set a particular channel tap status to lock or to unlock with respect to a multipath signal 108 (FIG. 1).

To begin, at reference number 403, the processing circuitry 111 generates symbols for each channel tap 116 (FIG. 1). The processing circuitry 111 may implement a descrambler/despreader 132 (FIG. 1) for each channel tap 116. At reference number 406, the processing circuitry 111 performs a channel estimation filter process based on symbols corresponding to each channel tap 116. The processing circuitry 111 may implement a channel estimation filter 135 (FIG. 1) for generating a channel estimation filtered signal based on the symbols for each channel tap 116.

At reference number 409, the processing circuitry 111 generates a signal power estimation for each channel tap 116. For example, the processing circuitry 111 may implement a power estimation block 139 (FIG. 1) for generating each power estimation value. At reference number 412, the processing circuitry 111 performs an RSSI filter operation. The processing circuitry 111 may implement an RSSI filter 142 (FIG. 1) for generating an RSSI value corresponding to each channel tap. The RSSI value may correlate to a signal power/signal energy 215 (FIG. 2) associated with a corresponding channel tap 116 for a particular point in time.

In various embodiments, the processing circuitry 111 may generate an RSSI value/signal on a per slot basis. In this respect, the multipath signal 108 may be transmitted according to a wireless protocol that divides wireless signals into transmission intervals such as, for example, timeslots, frames, blocks, or any other signal division unit. Accordingly, the processing circuitry 111 may be configured to generate RSSI values/signals periodically based on a transmission interval.

At reference number 415, the processing circuitry 111 determines a noise power estimation for each channel tap 116. For example, the processing circuitry 111 may implement a noise power estimator 145 (FIG. 1) for estimating a noise power 228 (FIG. 2) associated with each channel tap 116.

At reference number 418, the processing circuitry 111 scales or otherwise normalizes the RSSI value/signal for each channel tap 116 based on a corresponding noise power estimation. In various embodiments, the processing circuitry 111 scales/normalizes the RSSI value for a particular channel tap 116 based on the corresponding noise power estimation for the particular channel tap 116 and the total noise power for the set of channel taps 116. Thus, by scaling the RSSI value/signal for each channel tap 116, the processing circuitry 111 generates a per tap metric 306 (FIG. 3) comprising a corresponding scaled RSSI value/signal. Thus, reference number 418 demonstrates embodiments of the present disclosure directed to using a noise-scaled RSSI value for each channel tap 116.

In alternative embodiments, the RSSI value for each channel tap 116 is not scaled according to a noise power. In such embodiments, reference number 418 may be bypassed. In such a case, the per tap metric 306 comprises the RSSI value that is not scaled according to a per tap noise power.

At reference number 421, the processing circuitry 111 determines whether the per tap metric 306 exceeds a relative upper threshold 312 (FIG. 3). For example, the processing circuitry 111 may implement a lock detector 148 for each channel tap 116. The lock detector 148 (FIG. 1) may be configured to determine whether a per tap metric 306 exceeds a relative threshold range. If the per tap metric 306 exceeds the relative threshold range, then the processing circuitry 111 branches to reference number 424.

At reference number 424, the processing circuitry 111 sets a particular channel tap 116 to a lock status. If the scaled per tap metric 306 falls below the predetermined threshold range such that it falls below the relative upper threshold 312, the processing circuitry 111 branches to reference number 425. At reference number 425, the processing circuitry 111 determines whether the per tap metric 306 falls below a relative lower threshold 315 (FIG. 3). For example, the processing circuitry 111 may implement a lock detector 148 for each channel tap 116. The lock detector 148 may be configured to determine whether a per tap metric 306 falls below a relative threshold range. If the per tap metric 306 does not fall below the relative threshold range, then the processing circuitry 111 terminates and the lock/unlock status for the channel tap 116 holds or otherwise remains in the previous state. However, if the per tap metric 306 falls below the relative threshold range, then the processing circuitry 111 branches to reference number 427.

At reference number 427, the processing circuitry 111 sets a particular channel tap 116 to and unlock status. In various embodiments, the status of each channel tap 116 may be updated on a periodic basis such as, for example, on a per slot basis.

Referring next to FIG. 5, is a flowchart illustrating examples of functionality implemented as portions of logic in the processing circuitry 111 of FIG. 1 according to various embodiments of the present disclosure. It is understood that the flowchart of FIG. 5 provides merely an example of the many different types of functional arrangements that may be employed to implement the operation of the processing circuitry 111 as described herein. As an alternative, the flowchart of FIG. 5 may be viewed as depicting an example of steps of a method implemented in the processing circuitry 111 according to one or more embodiments. Specifically, the flowchart of FIG. 5 provides a non-limiting example of determining how to adjust a variable threshold range 151 (FIG. 1).

At reference number 505, the processing circuitry determines an RSSI value/signal for each channel tap 116 (FIG. 1) among a plurality of channel taps 116. For example, the processing circuitry 111 may implement an RSSI filter 142 (FIG. 1) for each channel tap 116. At reference number 508, the processing circuitry 111 identifies the maximum RSSI value 234 (FIG. 2) among the set of determined RSSI values. The processing circuitry 111, for example, may employ a rank or sort algorithm for selecting the largest value among the set of values.

At reference number 511, the processing circuitry 111 scales an upper bound preset threshold value. For example, the processing circuitry 111 may comprise preset threshold values that are constant. The processing circuitry 111 may multiply the preset threshold value with the maximum RSSI value 234 to determine a variable or relative upper threshold 312 (FIG. 3). Alternatively, the relative upper threshold 312 may be determined by subtracting an offset amount from the maximum RSSI value 234.

At reference number 514, the processing circuitry 111 scales a lower bound preset threshold value. The processing circuitry 111 may multiply the lower bound preset threshold value with the maximum RSSI value 234 to determine a variable or relative lower threshold 315 (FIG. 3). Alternatively, the relative upper threshold 312 may be determined by subtracting an offset amount from the maximum RSSI value 234.

Accordingly, processing circuitry 111 may store the variable/relative upper threshold 312 and the variable/relative lower threshold 315 as a variable threshold range 151. A lock detector 148 (FIG. 1) may read the variable threshold range 151 from the memory of the processing circuitry 111. To this end, the lock detector 148 uses a variable threshold range 151 to determine whether to set the status of a particular channel tap 116 to lock or unlock.

Although the flowchart of FIG. 5 uses a maximum RSSI value 234 for determining a relative upper threshold 312 and relative lower threshold 315, various embodiments of the present disclosure are not so limited. For example, a maximum noise-scaled RSSI value may be used. That is to say, the maximum value among the set of noise-scaled RSSI values for a corresponding set of channel taps 116 may be used to determine a variable threshold 151.

The flowcharts of FIGS. 4 and 5 show the functionality and operation of an implementation of portions of processing circuitry 111. If embodied in software, each item may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as the processing circuitry 111. The machine code may be converted from the source code, etc. If embodied in hardware, each item may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).

Although the flowcharts of FIGS. 4 and 5 show a specific order of execution, it is understood that the order of execution may differ from that which is depicted. For example, the order of execution of two or more blocks may be scrambled relative to the order shown. Also, two or more blocks shown in succession in FIGS. 4 and 5 may be executed concurrently or with partial concurrence. Further, in some embodiments, one or more of the items shown in FIGS. 4 and 5 may be skipped or omitted. In addition, any number of counters, state variables, warning semaphores, or messages might be added to the logical flow described herein, for purposes of enhanced utility, accounting, performance measurement, or providing troubleshooting aids, etc. It is understood that all such variations are within the scope of the present disclosure.

Also, any logic or application described herein that comprises software or code, for example, the processing circuitry 111 (FIG. 1), can be embodied in any non-transitory computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processing circuitry 111 in a computer system or other system. In this sense, the logic may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system. In the context of the present disclosure, a “computer-readable medium” can be any medium that can contain, store, or maintain the logic or application described herein for use by or in connection with the instruction execution system.

The computer-readable medium can comprise any one of many physical media such as, for example, magnetic, optical, or semiconductor media. More specific examples of a suitable computer-readable medium would include, but are not limited to, magnetic tapes, magnetic floppy diskettes, magnetic hard drives, memory cards, solid-state drives, USB flash drives, or optical discs. Also, the computer-readable medium may be a random access memory (RAM) including, for example, static random access memory (SRAM) and dynamic random access memory (DRAM), or magnetic random access memory (MRAM). In addition, the computer-readable medium may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or other type of memory device.

It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

1. A method for a processing circuit comprising:

generating a set of symbols for a channel tap among a plurality of channel taps based at least upon a multipath signal;

generating a signal power estimation based at least upon a filtering of the set of symbols by a channel estimation filter;

generating a received signal strength indication (RSSI) signal based at least upon the signal power estimation;

determining a noise power estimation for the channel tap based at least upon a portion of the set of symbols; and

scaling the RSSI signal based at least upon the noise power estimation to generate a scaled RSSI signal.

2. The method of claim 1, further comprising setting the channel tap to a lock status based at least upon the scaled RSSI signal and a predetermined threshold range.

3. The method of claim 2, wherein the predetermine threshold range is variable.

4. The method of claim 3, wherein the predetermine threshold range is adjusted according to a maximum RSSI signal among the plurality of channel taps.

5. The method of claim 3, wherein the predetermine threshold range is adjusted according to a maximum scaled RSSI signal among the plurality of channel taps.

6. The method of claim 1, wherein determining the noise power estimation comprises subtracting a pair of consecutive symbols of the set of symbols.

7. A system for signal processing, comprising:

a channel tap configured to obtain at least a portion of a multi-channel signal for generating a corresponding tap output;

a received signal strength indication (RSSI) filter configured to generate an RSSI signal based at least upon a signal power estimation of the tap output; and

a lock detector configured to set the channel tap to a lock status based at least upon the RSSI signal and a predetermined threshold amount.

8. The system of claim 7, further comprising a channel estimation filter configured to generate a channel estimation signal based at least upon the tap output.

9. The system of claim 8, wherein the channel estimation filter comprises a one-pole infinite impulse response filter.

10. The system of claim 8, further comprising a power estimator configured to generate the signal power estimation based at least upon the channel estimation signal.

11. The system of claim 7, wherein the channel tap is one of a plurality of channel taps.

12. The system of claim 11, wherein the predetermined threshold amount is configured to be adjusted according to respective signal powers corresponding to each of the plurality of channel taps.

13. The system of claim 11, wherein the predetermined threshold amount comprises an upper threshold and a lower threshold, wherein the upper threshold and lower threshold are configured to be adjusted.

14. The system of claim 13, wherein the upper threshold and lower threshold are configured to be adjusted according to a maximum RSSI signal, the maximum RSSI signal being determined among the plurality of channel taps.

15. The system of claim 7, wherein the RSSI filter is further configured to round a value expressed in the RSSI signal according to a predetermined number of digits.

16. A system comprising:

processing circuitry configured to: determine received signal strength indication (RSSI) value for each of the plurality of channel taps; identify a maximum RSSI value among the RSSI values; and adjust a variable threshold range according to the maximum RSSI value.

17. The system of claim 16, wherein the processing circuitry is further configured to modify a lock status associated with a channel tap in response to the corresponding RSSI value of the channel tap being outside the variable threshold range.

18. The system of claim 16, wherein the processing circuitry is further configured to hold a lock status associated with a channel tap in response to the corresponding RSSI value of the channel tap being within the variable threshold range.

19. The system of claim 16, wherein the processing circuitry is further configured to determine a respective noise power value for each of the plurality of channel taps.

20. The system of claim 19, wherein the processor is further configured to scale the RSSI filter signal on a per-slot basis.