LOW COMPLEXITY GATE LINE DRIVER CIRCUITRY
Gate driver circuitry that controls an array of display elements is described. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which the array of display elements is filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line, and the latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Other embodiments are also described and claimed.
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This applications claims the benefit of the earlier filing date of provisional application No. 61/646,795 filed May 14, 2012.
An embodiment of the invention is directed to the design of driver circuitry that is used for driving the gate lines of a display element array, such as an active matrix liquid crystal display (LCD) thin film transistor (TFT) array. Other embodiments are also described.
BACKGROUNDFor many applications, and particularly in consumer electronics devices, the large and heavy cathode ray tube (CRT) has been replaced by a flat panel display type, such as a liquid crystal display (LCD), plasma, and organic light emitting diode (OLED). A flat panel display screen contains an array of display elements. Each display element is to receive a signal that represents the picture element (pixel) value to be displayed at that location of the screen. This pixel signal may be applied using a transistor that is coupled to and integrated with the display element. The transistor may act as a switch element. It has a carrier electrode that receives the pixel signal, and a control electrode that receives a gate signal. The gate signal may serve to modulate or turn on and turn off the transistor so as to selectively apply the pixel signal to the coupled display element.
Typically, thousands or millions of copies of the display element and its associated switch element (e.g., an LCD cell and its associated control transistor) are produced in the form of an array, on a substrate such as a plane of glass or other light transparent material. The array is overlaid with a grid of data lines and gate lines. The data lines serve to deliver the pixel signals to the carrier electrodes of the control transistors, and the gate lines serve to apply the gate signals to the control electrodes of the transistors. In other words, each of the data lines is coupled to a respective group of display elements, typically referred to as a column of display elements, while each of the gate lines is coupled to a respective row of display elements.
Although not shown, each data line is coupled to a data line driver circuit that receives control and pixel signals from a signal generator. The latter translates incoming pixel values (for example, red, green and blue pixel values) into data signals (with appropriate timing). The data line driver then performs the needed voltage level shifting to produce a pixel signal with the needed fan-out (current capability).
As to the gate lines, and as seen in
The array of display elements are, in most cases, driven in a horizontal or line-by-line scanning fashion: the desired pixel signals for a selected row of display elements are provided on the data lines while at the same time a selected row of display elements is “enabled” by a pulse that is asserted on the associated gate line, by the gate driver of that gate line. The approach is to scan line-by-line or row-by-row in a vertical direction, until the entire display element array has been “filled” with the pixel values of a single image frame. This process may need to be repeated many times per second, to refresh the pixel values in the array.
In some active matrix displays, the gate lines are connected to their respective gate drivers in an interlaced manner, i.e. the locations of the gate drivers alternate between the left and right sides of the display element array as shown in
In certain touch screen applications, for example in consumer electronics devices such as a smart phone and a tablet computer, the physical space that is available on a substrate for forming the display element array and touch transducer, and for routing their signal lines, is quite limited. It has been discovered that the lack of space may be particularly acute in the border regions of a touch screen, along the left and right sides between an edge of the display element array and an edge of the light transparent substrate (where the gate drivers are typically located, such as in the case of a gate driver-on-array display structure).
An embodiment of the invention is lower complexity gate driver circuitry that may free up some space on a substrate on which display elements to be controlled by gate driver circuitry are formed. The gate driver circuitry has gate drivers that apply a control pulse to each of a number of gate lines in a scanning sequence, from a previous gate line to a current gate line, during a frame interval in which the display elements are filled with pixel values. Each gate driver has a latch stage followed by an output stage. The output stage is coupled to drive a current gate line. The latch stage is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage. Each hold circuit may be a pull-down, gate line holding transistor, such as a larger single TFT field effect device, that serves to maintain its associated gate line at a certain voltage. In some instances, such an arrangement may eliminate the need for routing a separate blanking control signal from a display controller or display driver integrated circuit, to each pair of pull-down holding transistors.
An embodiment of the invention may also reduce the number of transistors in an output stage of the gate driver circuitry, in one instance by eliminating the separate pull-down transistor that is typically part of the output stage (see
One or both of the above benefits may result in lower complexity gate driver circuitry which in turn reduces the complexity of a) routing signals between the display element array and a touch and/or display controller integrated circuit, and b) circuit layout in the border regions of the display element array. This in turn may lead to an advantageously narrower border region at the edge of the display panel or substrate.
The lower complexity gate driver circuitry may be useful in a touch screen application in which touch detection or touch transducer readout occurs during a touch interval (within the blanking interval). But the gate driver circuitry may also be useful in a display-only application.
The above summary does not include an exhaustive list of all aspects of the present invention. It is contemplated that the invention includes all systems and methods that can be practiced from all suitable combinations of the various aspects summarized above, as well as those disclosed in the Detailed Description below and particularly pointed out in the claims filed with the application. Such combinations have particular advantages not specifically recited in the above summary.
The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one.
Several embodiments of the invention with reference to the appended drawings are now explained. Whenever the shapes, relative positions and other aspects of the parts described in the embodiments are not clearly defined, the scope of the invention is not limited only to the parts shown, which are meant merely for the purpose of illustration. Also, while numerous details are set forth, it is understood that some embodiments of the invention may be practiced without these details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.
Beginning with
For each gate line 18, there is a respective near hold circuit 14 and a respective far hold circuit 16 that is coupled to the gate line. In one embodiment, each hold circuit is a pull-down circuit that can maintain its gate line 18 at a low voltage. The hold circuits 14, 16 are depicted as single field effect transistors, and in particular N-type devices whose drain terminals are directly connected to the gate line 18 and whose source terminals are connected to a voltage source Vhold. As an alternative, a different type of transistor, or other active device, or perhaps a more complicated multi transistor hold circuit is possible. The hold circuit 14, 16 can hold its associated gate line 18 at a voltage that enables the display elements that are coupled to the gate line 18 (not shown) to essentially maintain their existing pixel values. The nomenclature “near” and “far” has been selected to indicate that the near hold circuit 14 is located closer to its associated driver GD1, than the far hold circuit 16. The above arrangement repeats for each gate line as shown.
Here, it should be noted that in some embodiments, there may be no need to have both the near hold circuit 14 and the far hold circuit 16, on each gate line. In one instance, only the near hold circuit 14 is sufficient, while in other instances, only the far hold circuit 16 is sufficient.
Still referring to
A close up view of an example gate driver, in accordance with an embodiment of the invention, is depicted in
The gate driver circuitry depicted in
As a result of this arrangement, it can be seen that the output stage 12 now has at least one fewer transistor, namely the pull-down transistor depicted in
The arrangement in
Turning now to
There may be sufficient parasitic elements such that there is an desired crosstalk signal and/or noise coupling between the touch transducer and the gate lines. For example, when the touch transducer is operating, noise may be induced onto a gate line and that makes its way across the touch transducer, where such noise may disturb readout from the touch transducer. An example of this may be in a capacitive sensing touch transducer that receives a stimulation signal or a sensing signal on its row line or its column line; in such cases, there may be a need to maintain a nearby gate line at a predetermined voltage, by a strong pull-down for instance, to reduce the risk of disturbances when reading the touch transducer. This may be achieved in the gate line driver circuitry, in accordance with an embodiment of the invention, as described below.
It should be noted that while the latch stage 10 may have both an inverting and non-inverting output, and the output stage 12 may be fed from the non-inverting output, while the inverting output may be used to drive the hold circuit_1 (14) and hold circuit_2 (16) of a previous gate line, a different circuit arrangement is possible that renders the same function of driving the hold circuits 14, 16. For instance, the latch stage 10 may actually generate two control signals of slightly different timing, one being routed to drive the hold circuit_1 of the current gate line and the other being routed to drive the hold circuit_2 of a previous gate line. A particularly efficient circuit for the gate driver circuitry, and in particular the output stage 12, is shown in
Referring now to
As seen in the timing diagram of
Turning now to
Still referring to
An example set of waveforms including four clock signals, CLK1-CLK4, that may be needed to drive the clock drive inputs of the output stages 12, of the architecture in
While certain embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that the invention is not limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those of ordinary skill in the art. For example, although most of the transistors depicted in the drawings are N-type field effect devices, the circuitry may be modified to instead use P-type devices in certain situations, e.g. when a CMOS fabrication process is available or required. Also, while the gate line pulses are said to be asserted sequentially, the actual pulses on two adjacent gate lines may have some time overlap. The description is thus to be regarded as illustrative instead of limiting.
Claims
1. An electronic device comprising:
- a plurality of gate lines; and
- a plurality of gate drivers each having a latch stage followed by an output stage, the output stage being coupled to drive a current gate line, and wherein the gate driver is coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage.
2. The electronic device of claim 1 further comprising a plurality of display elements arranged as an array, and the gate drivers are arranged a) from top to bottom of the array in sequential scan order and b) alternating between left and right of the array.
3. The electronic device of claim 2 further comprising:
- a touch transducer that overlays the display element array; and
- a touch controller to generate a stimulation or sensing signal in the touch transducer.
4. The electronic device of claim 2 further comprising a light passing substrate on which the array of display elements, the gate lines and the gate line driver circuitry are formed.
5. The electronic device of any claim 1 wherein constituent transistors of the latch stage, the output stage and the first and second hold circuits are thin film transistors.
6. The electronic device of claim 1 further comprising a buffer coupled between the output stage and the current gate line.
7. The electronic device of claim 1 wherein the output stage comprises a pull-up circuit that can hold the current gate line at a voltage that enables display elements coupled to the current gate line to be updated with new pixel values,
- and wherein the first hold circuit can hold the current gate line at a voltage that enables the display elements that are coupled to the current gate line to essentially maintain existing pixel values.
8. The electronic device of claim 5 wherein each of the first and second hold circuits comprises a pull-down transistor that is larger than every one of the constituent transistors of the output stage and the latch stage.
9. The electronic device of claim 1 wherein each gate driver further comprises another output stage that is controlled by the latch stage and is coupled to drive another gate line.
10. An electronic device comprising:
- a plurality of gate lines, with a respective near hold circuit and a respective far hold circuit coupled to each of the gate lines;
- a first plurality of gate drivers each of the first plurality of gate drivers being coupled to drive an associated odd numbered one of the gate lines, when the gate lines are numbered sequentially; and
- a second plurality of gate drivers each of the second plurality of gate drivers being coupled to drive an associated even numbered one of the gate lines,
- wherein for each gate line, the respective near hold circuit is located closer to an associated gate driver, that is coupled to drive the gate line, than the respective far hold circuit,
- and wherein each of the gate drivers is further coupled to control a) the respective near hold circuit of an associated gate line and b) the respective far hold circuit of a neighbor gate line.
11. The device of claim 10 wherein each of the gate drivers has a latch stage with inverting and non-inverting outputs, and an output stage that is coupled to drive the associated gate line,
- wherein the inverting output of the latch stage is directly connected to drive the respective near hold circuit of the associated gate line and the respective far hold circuit of the neighbor gate line.
12. The device of claim 11 further comprising a buffer coupled between the output stage and the associated gate line.
13. The device of claim 11 wherein the output stage comprises a hold circuit that can hold the associated gate line at a voltage that enables display elements that are coupled to the associated gate line to be updated with new pixel values,
- and wherein the respective near hold circuit can hold the associated gate line at a voltage that enables the display elements that are coupled to the associated gate line to essentially maintain existing pixel values.
14. The device of claim 10 wherein the first plurality of gate drivers are arranged in a column on one side of the gate lines, and the second plurality of gate driers are arranged on another side of the gate lines.
15. The device of claim 10 wherein each of the first plurality of gate drivers has two output stages that are controlled by the same latch stage and that are coupled to drive a respective pair of the associated odd numbered gate lines.
16. The device of claim 15 wherein each of the second plurality of gate drivers has two output stages that are controlled by the same latch stage and that are coupled to drive a respective pair of the associated even numbered gate lines.
17. An electronic device comprising:
- a touchscreen system having
- a plurality of display elements,
- a touch transducer,
- a plurality of gate lines coupled to the display elements,
- a plurality of gate drivers each having a latch stage driving an output stage, the output stage being coupled to drive a current gate line, and the latch stage being coupled to drive a) a first hold circuit that holds the current gate line at a predetermined voltage, and b) a second hold circuit that holds a previous gate line at a predetermined voltage, and
- controller circuitry that is coupled to the touch transducer and the gate drivers, the controller circuitry to generate a) a start pulse that is fed to one of the gate drivers and b) a plurality of clock signals that are fed to each of the gate drivers, when updating the display elements during a frame interval, the controller circuitry to read the touch transducer during a blanking interval.
18. The device of claim 17 wherein the controller circuitry is to read the touch transducer during the blanking interval without using a separate blanking control signal to hold the gate lines at the predetermined voltage.
19. The device of claim 17 wherein the latch stage has inverting and non-inverting outputs, the output stage being fed from the non-inverting output, and the inverting output is to drive the first hold circuit and the second hold circuit.
20. A method for applying a pulse to each of a plurality of gate lines in sequence, from a previous gate line to a current gate line, during a frame interval in which a display element array is filled with pixel values, comprising:
- a) latching a first input value in response to assertion of a load clock;
- b) driving a current gate line to a first state in response to a drive clock and in accordance with the latched first input value;
- c) latching a second input value in response to a subsequent assertion of the load clock; and
- d) holding the current gate line at a second state in accordance with the latched second input value.
21. The method of claim 20 further comprising holding the previous gate line at the second state in accordance with the latched second input value.
22. The method of claim 20 further comprising repeating a)-d) during a subsequent frame interval.
23. The method of claim 20 further comprising:
- driving the previous gate line to the first state in response to another drive clock and in accordance with the latched first input value; and
- then holding the previous gate line at the second state in accordance with the latched second input value.
Type: Application
Filed: Jan 23, 2013
Publication Date: Nov 14, 2013
Patent Grant number: 9317151
Applicant: Apple Inc. (Cupertino, CA)
Inventors: Abbas Jamshidi-Roudbari (Sunnyvale, CA), Cheng-Ho Yu (Cupertino, CA), Shih Chang Chang (Cupertino, CA), Ting-Kuo Chang (Cupertino, CA)
Application Number: 13/747,872