Including Dielectric Isolation Means Patents (Class 257/506)
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Patent number: 12108590Abstract: The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.Type: GrantFiled: March 28, 2022Date of Patent: October 1, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jingwen Lu
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Patent number: 12062539Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.Type: GrantFiled: June 2, 2023Date of Patent: August 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ta Wu, Chia-Ta Hsieh, Kuo Wei Wu, Yu-Chun Chang, Ying Ling Tseng
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Patent number: 12046602Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.Type: GrantFiled: February 5, 2022Date of Patent: July 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Honglin Guo, Frank John Sweeney
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Patent number: 12020940Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a recess along a top surface of a semiconductor substrate. The method includes forming a nitride-based spacer layer extending along a first sidewall of the recess. The method includes forming a field oxide layer in the recess extending along a bottom surface of the recess, while a lateral tip of the field oxide layer is blocked from extending into any portion of the semiconductor substrate other than the recess by the nitride-based spacer layer.Type: GrantFiled: January 26, 2022Date of Patent: June 25, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Ching-Hung Kao
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Patent number: 12002845Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.Type: GrantFiled: January 13, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
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Patent number: 12002719Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.Type: GrantFiled: December 19, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-En Lin, Chi On Chui, Fang-Yi Liao, Chunyao Wang, Yung-Cheng Lu
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Patent number: 11948878Abstract: A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.Type: GrantFiled: September 8, 2022Date of Patent: April 2, 2024Assignee: LITTELFUSE, INC.Inventor: Stefan Steinhoff
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Patent number: 11948840Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.Type: GrantFiled: August 31, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
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Patent number: 11940536Abstract: The present technology relates to a light receiving element and a ranging system to reduce power consumption. A light receiving element includes a pixel which includes an SPAD, a first transistor configured to set a cathode voltage of the SPAD at a first negative voltage, a voltage conversion circuit configured to convert the cathode voltage of the SPAD upon incidence of a photon and output the converted cathode voltage, and an output unit configured to output a detection signal indicating the incidence of the photon on the SPAD on the basis of the converted cathode voltage. The present technology is applicable to a ranging system that detects a range in a depth direction to a subject, for example.Type: GrantFiled: August 16, 2019Date of Patent: March 26, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Tatsuki Nishino
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Patent number: 11903209Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.Type: GrantFiled: June 24, 2022Date of Patent: February 13, 2024Assignee: SK hynix Inc.Inventors: Hye-Hyeon Byeon, Sang-Deok Kim, Il-Young Kwon, Tae-Hong Gwon, Jin-Ho Bin
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Patent number: 11830925Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.Type: GrantFiled: September 17, 2021Date of Patent: November 28, 2023Assignee: Paragraf LimitedInventors: Thomas James Badcock, Robert Wallis, Ivor Guiney, Simon Thomas
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Patent number: 11832433Abstract: The present disclosure includes apparatuses and methods related to array and peripheral area masking. An example method comprises concurrently forming an array active area mask in an array active area and a peripheral component active area. The method further comprises forming a peripheral component active area mask in the peripheral component active area. The method further comprises concurrently forming etch stop spacers using the array active area mask in the array active area and the peripheral component active area. The method further comprises etching a portion of the peripheral component active area to open peripheral component conductive contact vias using the peripheral component active area mask together with the formed etch stop spacers in order to reduce over-etch of an opening to a device well while increasing surface area opening to a peripheral component conductive contact.Type: GrantFiled: November 15, 2021Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventor: Kyuseok Lee
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Patent number: 11791379Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.Type: GrantFiled: December 16, 2021Date of Patent: October 17, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE LTDInventors: Bong Woong Mun, Wanbing Yi, Juan Boon Tan, Jeoung Mo Koo
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Patent number: 11764205Abstract: A semiconductor device includes ānā pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.Type: GrantFiled: June 15, 2021Date of Patent: September 19, 2023Assignee: Infineon Technologies AGInventor: Joost Adriaan Willemen
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Patent number: 11746004Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.Type: GrantFiled: February 9, 2022Date of Patent: September 5, 2023Assignee: Analog Devices, Inc.Inventors: Charles Blackmer, Jeffrey A. Gregory, Nikolay Pokrovskiy, Bradley C. Kaanta
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Patent number: 11729966Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: GrantFiled: April 18, 2022Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Wonseok Yoo, Hokyun An, Kyungwook Park, Dain Lee
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Patent number: 11688626Abstract: Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.Type: GrantFiled: October 8, 2021Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Ruilong Xie, Kangguo Cheng, Julien Frougier
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Patent number: 11682578Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.Type: GrantFiled: April 16, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Hung Cheng, Yu-Chun Chang, Ching I Li, Ru-Liang Lee
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Patent number: 11670700Abstract: A semiconductor memory element is provided. The semiconductor memory element includes a substrate including a memory cell region and a peripheral circuit region, an active region located in the memory cell region, a gate pattern buried in the active region, a conductive line disposed on the gate pattern, a first region including a plurality of peripheral elements placed in the peripheral circuit region, a dummy pattern buried in the peripheral circuit region, and a second region which includes the dummy pattern and does not overlap the first region.Type: GrantFiled: March 24, 2021Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Kwan Kim, Hyuck Joon Kwon, Jae Beom Jeon
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Patent number: 11631735Abstract: The present application discloses a semiconductor device with the flowable layer. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.Type: GrantFiled: February 24, 2022Date of Patent: April 18, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Liang-Pin Chou
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Patent number: 11615952Abstract: A method for forming a foreign oxide or foreign nitride layer (6) on a substrate (1) of a semiconductor comprises providing a semiconductor substrate (1) having an oxidized or nitridized surface layer (3), supplying a foreign element (5) on the oxidized or nitridized surface layer; and keeping the oxidized or nitridized surface layer (3) at an elevated temperature so as to oxidize or nitridize at least partially the foreign element by the oxygen or nitrogen, respectively, initially present in the oxidized or nitridized surface layer (3).Type: GrantFiled: February 17, 2016Date of Patent: March 28, 2023Assignee: TURUN YLIOPISTOInventors: Mikhail Kuzmin, Pekka Laukkanen, Yasir Muhammad, Marjukka Tuominen, Johnny Dahl, Veikko Tuominen, Jaakko Makela, Marko Punkkinen, Kalevi Kokko
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Patent number: 11615980Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, introducing a second reactant to the substrate with a second dose, wherein the first and the second doses overlap in an overlap area where the first and second reactants react and leave an initially substantially unreacted area where the first and the second areas do not overlap; introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant to form deposited material; and etching the deposited material. An apparatus for filling a recess is also disclosed.Type: GrantFiled: December 8, 2021Date of Patent: March 28, 2023Assignee: ASM IP Holding B.V.Inventors: Viljami Pore, Zecheng Liu
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Patent number: 11605648Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.Type: GrantFiled: July 22, 2021Date of Patent: March 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
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Patent number: 11600695Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.Type: GrantFiled: December 10, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
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Patent number: 11594447Abstract: A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.Type: GrantFiled: April 30, 2021Date of Patent: February 28, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chia-Hsiang Hsu
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Patent number: 11594594Abstract: A method for fabricating a semiconductor device includes forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure, exposing the upper structure to a plasma treatment, and exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process.Type: GrantFiled: April 4, 2022Date of Patent: February 28, 2023Assignee: SK hynix Inc.Inventor: Seung-Muk Kim
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Patent number: 11587941Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: GrantFiled: April 16, 2020Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Sae Jun Kwon, Hwal Pyo Kim, Jin Taek Park, Yang Seok Lim, Young Ock Hong
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Patent number: 11557518Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.Type: GrantFiled: March 10, 2021Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-En Lin, Chi On Chui, Fang-Yi Liao, Chunyao Wang, Yung-Cheng Lu
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Patent number: 11532523Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.Type: GrantFiled: March 10, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-En Lin, Chi On Chui, Fang-Yi Liao, Chunyao Wang, Yung-Cheng Lu
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Patent number: 11502087Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor device comprises: a first active region over a substrate; and a first bit line structure intercepting the first active region at a level that is lower than a top-most surface thereof, the first bit line structure including a barrier liner having a U-profile in a width direction thereof in electrical contact with the first active region.Type: GrantFiled: January 21, 2020Date of Patent: November 15, 2022Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.Inventor: Il-Goo Kim
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Patent number: 11495660Abstract: The present disclosure relates to semiconductor structures and, more particularly, to co-integrated high voltage and medium voltage devices with defect prevention structures and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) region and a bulk region integrated in a single substrate; at least one active device in the bulk region; at least one active device in the SOI region; and a defect prevention structure bordering the SOI region.Type: GrantFiled: November 6, 2020Date of Patent: November 8, 2022Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LIMITED LIABILITY COMPANY & CO. KGInventor: Nan Wu
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Patent number: 11482424Abstract: The invention discloses an active region structure and a manufacturing method thereof, which also comprises a edge portion around the active region, so that the stress generated by the shallow trench insulation layer in the peripheral area on the active region can be blocked, and the component unit in the peripheral edge area of the active region can be prevented from being damaged due to stress. In addition, the edge portion includes branches extending into the active region, and the branches extend in at least two different directions, which can compensate the uneven stress at the end between the active lines and avoid the damage of the component unit.Type: GrantFiled: October 13, 2020Date of Patent: October 25, 2022Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.Inventor: Gang-Yi Lin
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Patent number: 11459655Abstract: A plasma processing method executed by a plasma processing apparatus in the present disclosure includes a first step and a second step. In the first step, the plasma processing apparatus forms a first film on the side walls of an opening in the processing target, the first film having different thicknesses along a spacing between pairs of side walls facing each other. In the second step, the plasma processing apparatus forms a second film by performing a film forming cycle once or more times after the first step, the second film having different thicknesses along the spacing between the pairs of side walls facing each other.Type: GrantFiled: July 26, 2019Date of Patent: October 4, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Michiko Nakaya, Toru Hisamatsu, Shinya Ishikawa, Sho Kumakura, Masanobu Honda, Yoshihide Kihara
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Patent number: 11462544Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.Type: GrantFiled: October 16, 2018Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
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Patent number: 11462550Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.Type: GrantFiled: August 17, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
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Patent number: 11443976Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.Type: GrantFiled: October 20, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Lei Chen, Cheng-Hsin Chen, Chung Chieh Ting, Che-Yi Lin, Clark Lee
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Patent number: 11422303Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a waveguide structure with attenuator and methods of manufacture. The structure includes: a waveguide structure including semiconductor material; an attenuator underneath the waveguide structure; an airgap structure vertically aligned with and underneath the waveguide structure and the attenuator; and shallow trench isolation structures on sides of the waveguide structure and merging with the airgap structure.Type: GrantFiled: December 1, 2020Date of Patent: August 23, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Mark D. Levy, Siva P. Adusumilli, Yusheng Bian
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Patent number: 11424240Abstract: A semiconductor device includes an electric circuit configured to include, a transistor, a first pad coupled to a gate or a drain of the transistor, a second pad coupled to the gate or the drain of the transistor, a first wiring that extends from the gate or the drain of the transistor to the first pad, and a second wiring that diverges from the first wiring and extends to the second pad, and a redistribution layer formed over the electric circuit and configured to include a first redistribution coupled to the first pad, and a second redistribution coupled to the second pad to constitute a stub.Type: GrantFiled: October 2, 2019Date of Patent: August 23, 2022Assignee: FUJITSU LIMITEDInventors: Ikuo Soga, Yoichi Kawano
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Patent number: 11387147Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.Type: GrantFiled: August 10, 2020Date of Patent: July 12, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Cyrille Le Royer, Fabrice Nemouchi
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Patent number: 11374087Abstract: A method for fabricating a semiconductor device includes forming an upper structure in which a bottom electrode, a dielectric layer, a top electrode and a plasma protection layer are sequentially stacked on a lower structure, exposing the upper structure to a plasma treatment, and exposing the plasma-treated upper structure and the lower structure to a hydrogen passivation process.Type: GrantFiled: August 7, 2019Date of Patent: June 28, 2022Assignee: SK hynix Inc.Inventor: Seung-Muk Kim
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Patent number: 11348917Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.Type: GrantFiled: April 30, 2020Date of Patent: May 31, 2022Inventors: Chieh-Ping Wang, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui
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Patent number: 11342378Abstract: The present disclosure provides a semiconductor structure, including a magnetic tunneling junction (MTJ), a top electrode over a top surface of the MTJ, a first dielectric layer surrounding the top electrode, wherein a bottom surface of the first dielectric contacts with a top surface of the MTJ, and a second dielectric layer surrounding the first dielectric layer and the MTJ.Type: GrantFiled: April 25, 2019Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chern-Yow Hsu
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Patent number: 11335689Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.Type: GrantFiled: April 1, 2020Date of Patent: May 17, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoongoo Kang, Wonseok Yoo, Hokyun An, Kyungwook Park, Dain Lee
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Patent number: 11335770Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.Type: GrantFiled: May 28, 2020Date of Patent: May 17, 2022Assignee: Winbond Electronics Corp.Inventors: Yoshinori Tanaka, Wei-Che Chang
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Patent number: 11302781Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. A transistor structure is formed is the semiconductor body. A trench structure extends from the first surface into the semiconductor body. An electrostatic discharge protection structure is accommodated in the trench structure. The electrostatic discharge protection structure includes a first terminal region and a second terminal region. A source contact structure at the first surface is electrically connected to source regions of the transistor structure and to the first terminal region. A gate contact structure at the first surface is electrically connected to a gate electrode of the transistor structure and to the second terminal region.Type: GrantFiled: April 12, 2018Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Joachim Weyers, Stefan Gamerith, Franz Hirler, Anton Mauder
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Patent number: 11282739Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.Type: GrantFiled: October 30, 2020Date of Patent: March 22, 2022Assignee: GlobalWafers Co., Ltd.Inventors: Charles R. Lottes, Shawn George Thomas, Henry Frank Erk
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Patent number: 11264382Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.Type: GrantFiled: July 30, 2020Date of Patent: March 1, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Jiehui Shu, Bharat V. Krishnan
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Patent number: 11264402Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices.Type: GrantFiled: November 26, 2019Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Cheng Wu, Chien-Hung Chang
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Patent number: 11239204Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.Type: GrantFiled: November 25, 2019Date of Patent: February 1, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
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Patent number: 11226696Abstract: A display device includes a display panel that includes a flat part and a protruding part adjacent to one side of the flat part, a touch panel disposed on the display panel, a touch connection circuit board disposed at one side of the touch panel and electrically connected to the touch panel, and a protective layer disposed on one surface of the touch connection circuit board and that overlaps the protruding part. The touch connection circuit board includes a base film, a first dummy pattern disposed on the base film and adjacent to one edge of the base film, a second dummy pattern disposed on the base film and adjacent to an other edge of the base film, and a line pattern section disposed between the first and second dummy patterns. The protective layer covers the line pattern section between the first and second dummy patterns.Type: GrantFiled: March 12, 2020Date of Patent: January 18, 2022Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jihoon Oh, Myoung-Ha Jeon, Youngsoo Kim