Including Dielectric Isolation Means Patents (Class 257/506)
  • Patent number: 11226696
    Abstract: A display device includes a display panel that includes a flat part and a protruding part adjacent to one side of the flat part, a touch panel disposed on the display panel, a touch connection circuit board disposed at one side of the touch panel and electrically connected to the touch panel, and a protective layer disposed on one surface of the touch connection circuit board and that overlaps the protruding part. The touch connection circuit board includes a base film, a first dummy pattern disposed on the base film and adjacent to one edge of the base film, a second dummy pattern disposed on the base film and adjacent to an other edge of the base film, and a line pattern section disposed between the first and second dummy patterns. The protective layer covers the line pattern section between the first and second dummy patterns.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jihoon Oh, Myoung-Ha Jeon, Youngsoo Kim
  • Patent number: 11205708
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
  • Patent number: 11201053
    Abstract: A method for forming a silicon nitride film to cover a stepped portion formed by exposed surfaces of first and second base films in a substrate, includes: forming a nitride film or a seed layer to cover the stepped portion, wherein the nitride film is formed by supplying, to the substrate, a nitrogen-containing base-film nitriding gas for nitriding the base films, exposing the substrate to plasma and nitriding the surface of the stepped portion, and the seed layer is composed of a silicon-containing film formed by supplying a raw material gas of silicon to the substrate and is configured such that the silicon nitride film uniformly grows on the surfaces of the base films; and forming the silicon nitride film on the seed layer by supplying, to the substrate, a second raw material gas of silicon and a silicon-nitriding gas for nitriding silicon.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 14, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Noriaki Fukiage, Takayuki Karakawa, Toyohiro Kamada, Akihiro Kuribayashi, Takeshi Oyama, Jun Ogawa, Kentaro Oshimo, Shimon Otsuki, Hideomi Hane
  • Patent number: 11195746
    Abstract: Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Kangguo Cheng, Julien Frougier
  • Patent number: 11183499
    Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Yoshinori Tanaka, Wei-Che Chang, Kai Jen
  • Patent number: 11161999
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes a preparation process, a block copolymer layer formation process, and a contact process. The preparation process includes preparing a pattern formation material including a block copolymer including a first block and a second block. The first block includes a first main chain and a plurality of first side chains. At least one of the first side chains includes a plurality of carbonyl groups. The block copolymer layer formation process includes forming a block copolymer layer on a first member. The block copolymer layer includes the pattern formation material and includes a first region and a second region. The first region includes the first block. The second region includes the second block. The contact process includes causing the block copolymer layer to contact a metal compound including a metallic element.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Norikatsu Sasao, Koji Asakawa, Tomoaki Sawabe, Shinobu Sugimura
  • Patent number: 11165220
    Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 2, 2021
    Assignees: STMicroelectronics (Crolles 2) SAS, Universite Paris-Saclay, Centre National de la Recherche Scientifique
    Inventors: Anas Elbaz, Moustafa El Kurdi, Abdelhanin Aassime, Philippe Boucaud, Frederic Boeuf
  • Patent number: 11152388
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Cole Smith, Ramey M. Abdelrahaman, Silvia Borsari, Chris M. Carlson, David Daycock, Matthew J. King, Jin Lu
  • Patent number: 11133270
    Abstract: An integrated circuit device includes a substrate, an integrated circuit region on the substrate, a seal ring disposed in a dielectric stack of the integrated circuit region and around a periphery of the integrated circuit region, a trench around the seal ring and exposing a sidewall of the dielectric stack, a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and a passivation layer over the moisture blocking layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 28, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin, Chu-Chun Chang
  • Patent number: 11114303
    Abstract: In a method, a semiconductor substrate is etched to form a trench, such that the trench defines a channel portion. A hard mask layer is deposited over sidewalls of the channel portion. The semiconductor substrate is anisotropically etched to deepen the trench, such that the deepened trench further defines a base portion under the channel portion and the hard mask layer. The hard mask layer is removed from the sidewalls of the channel portion. The deepened trench is filled with an isolation material. The isolation material is recessed to form an isolation structure, in which the channel portion protrudes from the isolation structure.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung-Ying Lee
  • Patent number: 11101342
    Abstract: A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Ye Shao, John K Arch
  • Patent number: 11081556
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 3, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hiroyuki Kamada
  • Patent number: 11063152
    Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang
  • Patent number: 11063022
    Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Hsien-Wei Chen, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 11056382
    Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Steven M. Shank
  • Patent number: 11056394
    Abstract: Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11043492
    Abstract: Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Biswajeet Guha, Tahir Ghani, Christopher N. Kenyon, Leonard P. Guler
  • Patent number: 11024716
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
  • Patent number: 11018138
    Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: May 25, 2021
    Assignee: APPLIED Materials, Inc.
    Inventors: Sony Varghese, Min Gyu Sung
  • Patent number: 11018258
    Abstract: A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 11011549
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 11011609
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first insulating part provided in the first semiconductor region, a first electrode provided in the first semiconductor region, the first insulating part disposed between the first electrode and the first semiconductor region, a second insulating part provided on the first electrode, a gate electrode provided on the second insulating part, a gate insulating part provided between the gate electrode and the second semiconductor region, and a second electrode provided on the second semiconductor region and on the third semiconductor region, and is electrically connected to the second semiconductor region, the third semiconductor region, and the first electrode.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 18, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenya Kobayashi, Tetsuo Matsuda, Yosuke Himori, Toshifumi Nishiguchi
  • Patent number: 10978351
    Abstract: A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Patent number: 10957585
    Abstract: A method is provided. Plural semiconductor fins are formed on a substrate, and plural trenches each of which is formed between two adjacent semiconductor fins. A silicon liner layer is deposited to be conformal to the semiconductor fins and the trenches. The silicon liner layer is deposited by using a silane compound. Then, an oxide layer is deposited on the silicon liner layer to fill the trenches and cover the semiconductor fins, in which depositing the oxide layer forms water in the oxide layer. Next, a surface of the silicon liner layer is reacted with the water, so as to remove the water from the oxide layer.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Hsu, Yu-Yun Peng, An-Di Sheu, Jei-Ming Chen
  • Patent number: 10943993
    Abstract: A method for fabricating semiconductor device includes: forming a fin-shaped structure on a substrate, wherein the fin-shaped structure is extending along a first direction; forming a gate layer on the fin-shaped structure; removing part of the gate layer and part of the fin-shaped structure to form a first trench for dividing the fin-shaped structure into a first portion and a second portion, wherein the first trench is extending along a second direction; forming a patterned mask on the gate layer and into the first trench; removing part of the gate layer and part of the fin-shaped structure to form a second trench, wherein the second trench is extending along the first direction; and filling a dielectric layer in the first trench and the second trench.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10930545
    Abstract: A method for forming a semiconductor structure is disclosed. Among a stack of mask layers, any other layers above the lowermost thin film layer are subsequently removed to expose the lowermost thin film layer and then the lowermost thin film layer is separately removed by a dry etching process. This improves an etching uniformity of the lowermost thin film layer and ameliorates the issue of material residues. Moreover, thanks to the anisotropic characteristic of the dry etching process, lateral etching of side walls of a trench isolation structure can be mitigated.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Nexchip Semiconductor Corporation
    Inventors: Hongbo Zhu, Yi Zhang
  • Patent number: 10930640
    Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee, Li-Wei Chu, Po-Lin Peng
  • Patent number: 10916515
    Abstract: A device is disclosed that includes a wafer/chip, a first layer, a first device, an isolation mold and a second device. The first layer is formed over the chip and has non-isolating characteristics. The first device is formed over the first layer. In one example, it is formed only over the first layer. The isolation mold is formed over the chip. The isolation mold has isolating characteristics. The second device is formed substantially over the isolation mold.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Anton Steltenpohl, Edward Fuergut, Anneliese Mueller
  • Patent number: 10892278
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: January 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 10866330
    Abstract: Disclosed herein is a method for making an apparatus suitable for detecting X-ray, the method comprising: obtaining a wafer and a substrate; wherein the substrate comprises an X-ray absorption layer comprising a first plurality of electrical contacts; wherein the wafer has multiple dies and comprises an electronic layer comprising a second plurality of electrical contacts and an electronic system configured to process or interpret signals generated by X-ray photons incident on the X-ray absorption layer; aligning the first plurality of electrical contacts to the second plurality of electrical contacts; mounting the wafer to the substrate such that the first plurality of electrical contacts are electrically connected to the second plurality of electrical contacts; wherein the substrate further comprises a transmission line electrically bridging at least some of the dies; wherein the second plurality of electrical contacts are configured to feed the signals to the electronic system.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: December 15, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10861694
    Abstract: A method of manufacturing an insulation layer on silicon carbide includes first preparing a surface of the silicon carbide, then forming a first part of the insulation layer on the surface at a temperature lower than 400° Celsius. Finally, a second part of the insulation layer is formed by depositing a dielectric film on the first part. The surface of the silicon carbide is illuminated by a light at a wavelength below and/or equal to 450 nm during and/or after the formation of the first part of the insulation layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 8, 2020
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Yuji Komatsu
  • Patent number: 10804202
    Abstract: A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Akio Nishida
  • Patent number: 10770568
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Bao, Ying Zhang, Qingjun Zhou, YungChen Lin
  • Patent number: 10748817
    Abstract: A fabrication method for a semiconductor device is provided. The method includes: forming a semiconductor substrate including a first region and a second region; forming intrinsic fins protruding from the first region of the semiconductor substrate, and dummy fins protruding from the second region of the semiconductor substrate; forming a first isolation layer to cover a portion of sidewalls of the dummy fins and a portion of sidewalls of the intrinsic fins; forming a protection layer on surfaces of the intrinsic fins, to cover a portion of the intrinsic fins above a surface of the first isolation layer; removing the dummy fins and a portion of the first isolation layer in the second region; and forming a second isolation layer on the second region of the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 18, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Cheng Long Zhang
  • Patent number: 10741393
    Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 11, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yung-chen Lin, Qingjun Zhou, Xinyu Bao, Ying Zhang
  • Patent number: 10734423
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 10714683
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Patent number: 10707198
    Abstract: A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 7, 2020
    Assignee: IMEC VZW
    Inventor: Frederic Lazzarino
  • Patent number: 10700042
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Patent number: 10686077
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10680169
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Patent number: 10643988
    Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee, Li-Wei Chu, Po-Lin Peng
  • Patent number: 10644103
    Abstract: Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xing Wei
  • Patent number: 10643997
    Abstract: A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jia-Rong Wu, Tien-Chen Chan, Yu-Shu Lin, Jyh-Shyang Jenq
  • Patent number: 10622260
    Abstract: A semiconductor structure includes a first fin and a second fin vertically disposed on a substrate. The first fin is adjacent to and parallel to the second fin. A first source/drain is disposed on the substrate, and a first dielectric spacer is disposed on the first source/drain. A gate is disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin. A trench is adjacent to and parallel to the first fin and the second fin. The trench extends through a portion of the substrate and includes a top portion being narrower than a bottom portion. A dielectric material is disposed within the trench and pinches off the top portion of the trench to form an air gap spacer within the trench. The air gap spacer is parallel to and between the first fin and the second fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chanro Park, Kangguo Cheng
  • Patent number: 10586736
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Ruilong Xie, Shesh Mani Pandey, Hui Zang, Garo Jacques Derderian, Scott Beasor
  • Patent number: 10559471
    Abstract: Disclosed is a method of manufacturing a bonded wafer, wherein a terrace forming step is carried out using a chamfering wheel which comprise a low grit number grinding stone and a high grit number grinding stone having a higher grit number than the low grit number grinding stone, and wherein the terrace forming step comprises: a coarse chamfering step of chamfering, after chamfering the active layer wafer, the insulating film from the active layer wafer side and further chamfering the support substrate wafer, using the low grit number grinding stone; and a finish chamfering step of finish chamfering, after the coarse chamfering step, a machined surface obtained from the coarse chamfering step, using the high grit number grinding stone.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 11, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Yasuyuki Morikawa
  • Patent number: 10553474
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 10535564
    Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 14, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
  • Patent number: 10515815
    Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun