Including Dielectric Isolation Means Patents (Class 257/506)
  • Patent number: 10804202
    Abstract: A first semiconductor die is provided, which includes a first substrate, first semiconductor devices, first interconnect-level dielectric material layers, first metal interconnect structures, and first bonding pads. A second semiconductor die is provided, which includes a semiconductor-on-insulator (SOI) substrate, second semiconductor devices, second interconnect-level dielectric material layers, second metal interconnect structures, and second bonding pads. The second bonding pads are bonded to the first bonding pads. A bulk substrate layer of the SOI substrate is removed exposing an insulating material layer of the SOI substrate, which may be retained or also removed. An external bonding pad is electrically connected to a node of the second semiconductor devices.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Akio Nishida
  • Patent number: 10770568
    Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Bao, Ying Zhang, Qingjun Zhou, YungChen Lin
  • Patent number: 10748817
    Abstract: A fabrication method for a semiconductor device is provided. The method includes: forming a semiconductor substrate including a first region and a second region; forming intrinsic fins protruding from the first region of the semiconductor substrate, and dummy fins protruding from the second region of the semiconductor substrate; forming a first isolation layer to cover a portion of sidewalls of the dummy fins and a portion of sidewalls of the intrinsic fins; forming a protection layer on surfaces of the intrinsic fins, to cover a portion of the intrinsic fins above a surface of the first isolation layer; removing the dummy fins and a portion of the first isolation layer in the second region; and forming a second isolation layer on the second region of the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 18, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Cheng Long Zhang
  • Patent number: 10741393
    Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: August 11, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yung-chen Lin, Qingjun Zhou, Xinyu Bao, Ying Zhang
  • Patent number: 10734423
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 10714683
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Patent number: 10707198
    Abstract: A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 7, 2020
    Assignee: IMEC VZW
    Inventor: Frederic Lazzarino
  • Patent number: 10700042
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Patent number: 10686077
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Chang-Yin Chen, Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 10680169
    Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Michael Rizzolo, Daniel C. Edelstein, Theodorus E. Standaert, Kisup Chung, Isabel C. Chu, John C. Arnold
  • Patent number: 10644103
    Abstract: Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xing Wei
  • Patent number: 10643997
    Abstract: A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jia-Rong Wu, Tien-Chen Chan, Yu-Shu Lin, Jyh-Shyang Jenq
  • Patent number: 10643988
    Abstract: The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Feng Chang, Jam-Wem Lee, Li-Wei Chu, Po-Lin Peng
  • Patent number: 10622260
    Abstract: A semiconductor structure includes a first fin and a second fin vertically disposed on a substrate. The first fin is adjacent to and parallel to the second fin. A first source/drain is disposed on the substrate, and a first dielectric spacer is disposed on the first source/drain. A gate is disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin. A trench is adjacent to and parallel to the first fin and the second fin. The trench extends through a portion of the substrate and includes a top portion being narrower than a bottom portion. A dielectric material is disposed within the trench and pinches off the top portion of the trench to form an air gap spacer within the trench. The air gap spacer is parallel to and between the first fin and the second fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chanro Park, Kangguo Cheng
  • Patent number: 10586736
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Ruilong Xie, Shesh Mani Pandey, Hui Zang, Garo Jacques Derderian, Scott Beasor
  • Patent number: 10559471
    Abstract: Disclosed is a method of manufacturing a bonded wafer, wherein a terrace forming step is carried out using a chamfering wheel which comprise a low grit number grinding stone and a high grit number grinding stone having a higher grit number than the low grit number grinding stone, and wherein the terrace forming step comprises: a coarse chamfering step of chamfering, after chamfering the active layer wafer, the insulating film from the active layer wafer side and further chamfering the support substrate wafer, using the low grit number grinding stone; and a finish chamfering step of finish chamfering, after the coarse chamfering step, a machined surface obtained from the coarse chamfering step, using the high grit number grinding stone.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 11, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Yasuyuki Morikawa
  • Patent number: 10553474
    Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuan-Liang Liu, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 10535564
    Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: January 14, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
  • Patent number: 10515815
    Abstract: Methods and apparatuses for passivating a fin field effect transistor (FinFET) semiconductor device and performing a gate etch using integrated atomic layer deposition (ALD) and etch processes are described herein. Methods include performing a partial gate etch, depositing a passivation layer on exposed surfaces of semiconductor fins and a gate layer by ALD, and performing a final gate etch to form one or more gate structures of the FinFET semiconductor device. The etch, deposition, and etch processes are performed in the same plasma chamber. The passivation layer is deposited on sidewalls of the gate layer to maintain a gate profile of the one or more gate structures during etching.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Ganesh Upadhyaya, Yoshie Kimura, Weiye Zhu, Zhaohong Han, Seokhwan Lee, Noel Sun
  • Patent number: 10510739
    Abstract: A method of providing a layout design of an SRAM cell includes: providing a substrate layout comprising a first oxide diffusion area, a second oxide diffusion area, a first polysilicon layout, and a second polysilicon layout, wherein the first polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area, and the second polysilicon layout extends across the first oxide diffusion area and the second oxide diffusion area; forming a first pull-up transistor on the first oxide diffusion area and the first polysilicon layout; forming a first pull-down transistor on the second oxide diffusion area and the first polysilicon layout; forming a second pull-up transistor on the first oxide diffusion area and the second polysilicon layout; and forming a second pull-down transistor on the second oxide diffusion area and second first polysilicon layout.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Tetsu Ohtou, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen
  • Patent number: 10504770
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Patent number: 10497712
    Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
  • Patent number: 10483188
    Abstract: This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE ?1; d) filling the second trenches with a second material having a CTE ?2, and verifying ?2>?0 or ?2<?0 depending on whether the first material verifies ?1>?0 or ?1<?0.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 19, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Abdenacer Ait-Mani, Bertrand Chambion
  • Patent number: 10475695
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Patent number: 10468441
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 10468294
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 5, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Gang Wang, Jeffrey L. Libbert
  • Patent number: 10468385
    Abstract: The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Heng Lin, Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 10444275
    Abstract: There are provided an electric-current sensing device capable of detecting an electric current with high accuracy, a load driving system, and a method for manufacturing the electric-current sensing device. According to one embodiment, the electric-current sensing device includes a sense IGBT through which an electric current proportional to an electric current flowing through a main IGBT flows. Further, a depth of a P type floating region from a lower end of each of a plurality of trench gates provided in the sense IGBT is shallower than a depth of another P type floating region from a lower end of each of a plurality of trench gates provided in the main IGBT.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Kenji Takeuchi
  • Patent number: 10431684
    Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
  • Patent number: 10395996
    Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10395999
    Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hao Yang, En-Chiuan Liou, Hsiao-Lin Hsu, Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen
  • Patent number: 10396094
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 10388720
    Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Teng-Hao Yeh
  • Patent number: 10388651
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Patent number: 10354924
    Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 16, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jeng-Hwa Liao, Zong-Jie Ko, Jung-Yu Shieh, Ling-Wuu Yang
  • Patent number: 10347658
    Abstract: A pixel driving circuit and an OLED display are provided. The pixel driving circuit includes a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor, and an OLED. A gate of the third TFT is coupled to the scanning signal. A source of the third TFT is coupled to a drain of the fourth TFT. A gate of the fourth TFT is coupled to a data signal and a source of the fourth is coupled to a second reference voltage signal. The fourth TFT controls the electric current of the first TFT with the data signal and the second reference signal during the compensation stage of threshold voltage. Further, the compensation voltage of the first TFT is compensated.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yuying Cai
  • Patent number: 10325802
    Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho In Lee, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Wook Jung, Jinwoo Augustin Hong, Je Min Park, Ki Seok Lee, Ju Yeon Jang
  • Patent number: 10317798
    Abstract: A method of forming a pattern of a semiconductor device includes: forming a first mask pattern comprising first mask lines extending in a first direction in a cell region and second mask lines extending in the first direction in a first core region, the first mask pattern covering a second core region; forming, on the first mask pattern, a second mask pattern comprising third mask lines extending in a second direction in the cell region and fourth mask lines extending in the second direction in the second core region, the second mask pattern covering the first core region; and forming a third mask pattern by using the second mask pattern, the third mask pattern comprising island-type masks in the cell region, fifth mask lines extending in the first direction in the first core region, and sixth mask lines extending in the second direction in the second core region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-oh Park, Sang-chul Shin, Chang-hwan Kim, Ji-young Kim
  • Patent number: 10309036
    Abstract: A method for manufacturing a group III nitride semiconductor crystal substrate includes providing, as a seed crystal substrate, a group III nitride single crystal grown by a liquid phase growth method, and homoepitaxially growing a group III nitride single crystal by a vapor phase growth method on a principal surface of the seed crystal substrate. The principal surface of the seed crystal substrate is a +c-plane, and the seed crystal substrate has an atomic oxygen concentration of not more than 1×1017 cm?3 in a crystal near the principal surface over an entire in-plane region thereof.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 4, 2019
    Assignees: OSAKA UNIVERSITY, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Yusuke Mori, Masashi Yoshimura, Mamoru Imade, Masatomo Shibata, Takehiro Yoshida
  • Patent number: 10290739
    Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 10256299
    Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Anton Mauder
  • Patent number: 10256153
    Abstract: A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIIING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hai Zhao
  • Patent number: 10249577
    Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 2, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Choong Man Lee, Yong Min Yoo, Young Jae Kim, Seung Ju Chun, Sun Ja Kim
  • Patent number: 10229909
    Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeo Tokumitsu, Hiroki Fujii
  • Patent number: 10217843
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10218927
    Abstract: An image sensor includes a pixel array including a plurality of pixel blocks, each including a light receiving section including unit pixels which share a floating diffusion; a first driving section disposed at one side of the light receiving section and including a reset transistor; and a second driving section disposed adjacent to the first driving section and including a driver transistor, wherein the pixel blocks include a first pixel block and a second pixel block which is adjacent to the first pixel block, and, with respect to a boundary where the first pixel block and the second pixel adjoin each other, the first driving section of the first pixel block has a shape symmetrical to the first driving section of the second pixel block and the second driving section of the first pixel block has a shape asymmetrical to the second driving section of the second pixel block.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Pyong-Su Kwag, Hye-Won Mun
  • Patent number: 10217658
    Abstract: A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions are on a top surface of the liner layer on the substrate and includes a dielectric layer; and a doped region on the dielectric layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Hao Tang
  • Patent number: 10192956
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 29, 2019
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Patent number: 10191571
    Abstract: A substrate and a display device are provided. The substrate includes a base and a signal line arranged on the base. The signal line includes at least two main film layers and a first additional film layer arranged between every two adjacent main film layers, wherein an electrical conductivity of the main film layer is larger than that of the first additional film layer; and a crystallinity of the main film layer is lower than that of the first additional film layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ting Zeng, Kefeng Li, Taofeng Xie, Tsungchieh Kuo, Shuncheng Zhu
  • Patent number: 10177191
    Abstract: A method for forming an image sensor device is provided. The method includes providing a substrate. The substrate has a front surface and a back surface, and the substrate has a light-receiving region and a device region. The method includes forming a first transistor and a first source/drain structure respectively in the light-receiving region and the device region. The first transistor includes a first gate structure, a light-sensing structure, a second source/drain structure, the first gate structure is over the front surface, the light-sensing structure and the second source/drain structure are formed in the substrate and are respectively located at opposite first sides of the first gate structure, the first source/drain structure is formed in the substrate, and the first source/drain structure is electrically connected to the second source/drain structure. The method includes forming a light-blocking layer over the back surface.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang