Including Dielectric Isolation Means Patents (Class 257/506)
  • Patent number: 10431684
    Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Kummerl, Matthew John Sherbin, Saumya Gandhi
  • Patent number: 10395996
    Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10395999
    Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 27, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hao Yang, En-Chiuan Liou, Hsiao-Lin Hsu, Tang-Chun Weng, Chia-Ching Lin, Yen-Pu Chen
  • Patent number: 10396094
    Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 10388651
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Patent number: 10388720
    Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Teng-Hao Yeh
  • Patent number: 10354924
    Abstract: Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 16, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jeng-Hwa Liao, Zong-Jie Ko, Jung-Yu Shieh, Ling-Wuu Yang
  • Patent number: 10347658
    Abstract: A pixel driving circuit and an OLED display are provided. The pixel driving circuit includes a first TFT, a second TFT, a third TFT, a fourth TFT, a capacitor, and an OLED. A gate of the third TFT is coupled to the scanning signal. A source of the third TFT is coupled to a drain of the fourth TFT. A gate of the fourth TFT is coupled to a data signal and a source of the fourth is coupled to a second reference voltage signal. The fourth TFT controls the electric current of the first TFT with the data signal and the second reference signal during the compensation stage of threshold voltage. Further, the compensation voltage of the first TFT is compensated.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yuying Cai
  • Patent number: 10325802
    Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho In Lee, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Wook Jung, Jinwoo Augustin Hong, Je Min Park, Ki Seok Lee, Ju Yeon Jang
  • Patent number: 10317798
    Abstract: A method of forming a pattern of a semiconductor device includes: forming a first mask pattern comprising first mask lines extending in a first direction in a cell region and second mask lines extending in the first direction in a first core region, the first mask pattern covering a second core region; forming, on the first mask pattern, a second mask pattern comprising third mask lines extending in a second direction in the cell region and fourth mask lines extending in the second direction in the second core region, the second mask pattern covering the first core region; and forming a third mask pattern by using the second mask pattern, the third mask pattern comprising island-type masks in the cell region, fifth mask lines extending in the first direction in the first core region, and sixth mask lines extending in the second direction in the second core region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-oh Park, Sang-chul Shin, Chang-hwan Kim, Ji-young Kim
  • Patent number: 10309036
    Abstract: A method for manufacturing a group III nitride semiconductor crystal substrate includes providing, as a seed crystal substrate, a group III nitride single crystal grown by a liquid phase growth method, and homoepitaxially growing a group III nitride single crystal by a vapor phase growth method on a principal surface of the seed crystal substrate. The principal surface of the seed crystal substrate is a +c-plane, and the seed crystal substrate has an atomic oxygen concentration of not more than 1×1017 cm?3 in a crystal near the principal surface over an entire in-plane region thereof.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: June 4, 2019
    Assignees: OSAKA UNIVERSITY, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Yusuke Mori, Masashi Yoshimura, Mamoru Imade, Masatomo Shibata, Takehiro Yoshida
  • Patent number: 10290739
    Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Patent number: 10256153
    Abstract: A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: April 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIIING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hai Zhao
  • Patent number: 10256299
    Abstract: A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies AG
    Inventors: Alexander Philippou, Anton Mauder
  • Patent number: 10249577
    Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 2, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Choong Man Lee, Yong Min Yoo, Young Jae Kim, Seung Ju Chun, Sun Ja Kim
  • Patent number: 10229909
    Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeo Tokumitsu, Hiroki Fujii
  • Patent number: 10217843
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10218927
    Abstract: An image sensor includes a pixel array including a plurality of pixel blocks, each including a light receiving section including unit pixels which share a floating diffusion; a first driving section disposed at one side of the light receiving section and including a reset transistor; and a second driving section disposed adjacent to the first driving section and including a driver transistor, wherein the pixel blocks include a first pixel block and a second pixel block which is adjacent to the first pixel block, and, with respect to a boundary where the first pixel block and the second pixel adjoin each other, the first driving section of the first pixel block has a shape symmetrical to the first driving section of the second pixel block and the second driving section of the first pixel block has a shape asymmetrical to the second driving section of the second pixel block.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: February 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Pyong-Su Kwag, Hye-Won Mun
  • Patent number: 10217658
    Abstract: A semiconductor device includes a plurality of fins spaced apart from each other on a substrate; a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and a plurality of isolation regions adjacent and between the plurality of fins. The plurality of isolation regions are on a top surface of the liner layer on the substrate and includes a dielectric layer; and a doped region on the dielectric layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Hao Tang
  • Patent number: 10192956
    Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 29, 2019
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Safak Sayan, Min-Soo Kim, Doni Parnell, Roel Gronheid
  • Patent number: 10191571
    Abstract: A substrate and a display device are provided. The substrate includes a base and a signal line arranged on the base. The signal line includes at least two main film layers and a first additional film layer arranged between every two adjacent main film layers, wherein an electrical conductivity of the main film layer is larger than that of the first additional film layer; and a crystallinity of the main film layer is lower than that of the first additional film layer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ting Zeng, Kefeng Li, Taofeng Xie, Tsungchieh Kuo, Shuncheng Zhu
  • Patent number: 10177191
    Abstract: A method for forming an image sensor device is provided. The method includes providing a substrate. The substrate has a front surface and a back surface, and the substrate has a light-receiving region and a device region. The method includes forming a first transistor and a first source/drain structure respectively in the light-receiving region and the device region. The first transistor includes a first gate structure, a light-sensing structure, a second source/drain structure, the first gate structure is over the front surface, the light-sensing structure and the second source/drain structure are formed in the substrate and are respectively located at opposite first sides of the first gate structure, the first source/drain structure is formed in the substrate, and the first source/drain structure is electrically connected to the second source/drain structure. The method includes forming a light-blocking layer over the back surface.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Patent number: 10170610
    Abstract: In certain aspects, a pseudomorphic high electron mobility transistor (pHEMT) comprises a substrate layer, a bottom barrier layer on the substrate layer, a channel layer on the bottom barrier layer, an upper barrier on the channel layer, and a source and a drain on the upper barrier layer. The source and the drain each has a cap layer, an Ohmic contact layer on the cap layer, and a metal contact layer on the Ohmic contact layer. The Ohmic contact layer has a smaller bandgap than the cap layer. The pHEMT further comprises a gate metal stack on the upper barrier layer.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 10163634
    Abstract: Various patterning methods involved with manufacturing semiconductor device structures are disclosed herein. A method for forming a semiconductor device structure (for example, a conductive line) includes forming a first hard mask layer and a second hard mask layer over a dielectric layer. The first hard mask layer has a first opening, and the second hard mask layer has a first trench connected to the first opening. A filling layer is formed in the first opening, where the filling layer has a second opening and a third opening. The first hard mask layer and the dielectric layer are removed through the second opening and the third opening to form a second trench and a third trench in the dielectric layer. The first hard mask layer, the second hard mask layer, and the filling layer can be removed. A conductive layer is formed in the second trench and the third trench.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Sung Yen, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 10163911
    Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Thomas J. Aton, Scott W. Jessen
  • Patent number: 10121890
    Abstract: An embodiment of a structure provides an enhanced performing high voltage device, configured as a lateral diffused MOS (HV LDMOS) formed in a tri-well structure (a small n-well in an extended p-type well inside an n-type well) within the substrate with an anti-punch through layer and a buried layer below the n-type well, which reduces substrate leakage current to almost zero. The drain region is separated into two regions, one within the small n-well and one contacting the outer n-type well such that the substrate is available for electric potential lines during when a high drain voltage is applied.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10115626
    Abstract: A method for forming an isolation block of a semiconductor device includes providing a semiconductor substrate, performing an etching process to form a plurality of trenches which are parallel to each other in the semiconductor substrate, wherein a plurality of strip structures are between the trenches. The strip structures and the trenches occupy a first region in the semiconductor substrate, and the strip structures are arranged staggered with the trenches. The method further includes performing a thermal oxidation process, such that the strip structures are oxidized to form a plurality of oxidized portions, wherein the oxidized portions extended into the trenches and connected to each other to form an isolation block in the semiconductor substrate.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 30, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Li-Che Chen
  • Patent number: 10104785
    Abstract: An electronic assembly is disclosed that includes a flexible insulating film, a semiconductor component that has a thickness of less than 50 micrometers, a conductive interconnect extending through the flexible insulating film, a second patterned metal wiring film adjacent, and a third patterned metal wiring film. The second patterned metal wiring film is electrically coupled with the third patterned metal wiring film through the conductive interconnect. The semiconductor component is coupled to the first patterned metal wiring film and at least one of the second patterned metal wiring film or the third patterned metal wiring film.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 16, 2018
    Assignee: Invensas Corporation
    Inventors: Tomoo Iijima, Yoshitaka Fukuoka
  • Patent number: 10103512
    Abstract: An optoelectronic device includes a semiconductor substrate, having front and back sides and having at least one cavity extending from the back side through the semiconductor substrate into proximity with the front side. At least one optoelectronic emitter is formed on the front side of the semiconductor substrate in proximity with the at least one cavity. A heat-conducting material at least partially fills the at least one cavity and is configured to serve as a heat sink for the at least one optoelectronic emitter.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: October 16, 2018
    Assignee: APPLE INC.
    Inventors: Tongbi T. Jiang, Weiping Li, Xiaofeng Fan
  • Patent number: 10090195
    Abstract: A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Bernd Hintze, Heiko Weber
  • Patent number: 10062666
    Abstract: Various systems, devices and methods are provided for interconnection between wafers and/or chips using catch flexures. In one example, among others, a catch flexure assembly includes a first interconnect affixed to a first wafer. The first interconnect can include a female opening at a distal end of a flexible member that is configured to receive a male extension of a second interconnect affixed to a second wafer when the first wafer is aligned with the second wafer, and retain the male extension during a bonding process of the first and second flexible interconnects. The catch flexure assembly can also include bonding material disposed adjacent to the female opening, which is configured to secure the male extension in the female opening during the bonding process.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 28, 2018
    Assignee: ADVANCED RESEARCH CORPORATION
    Inventors: Matthew Phillip Dugas, Steven Brian Ellison, Gregory Lawrence Wagner
  • Patent number: 10014214
    Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Chung-Hsun Lin, Adam M. Pyzyna
  • Patent number: 10014302
    Abstract: Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10008447
    Abstract: A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 26, 2018
    Assignee: NXP USA, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff
  • Patent number: 9995683
    Abstract: An apparatus for detecting an object capable of emitting light. The apparatus includes a light source and a waveguide. The waveguide includes a core layer and a first cladding layer. At least one nanowell is formed in at least the first cladding layer. The apparatus further includes a light detector. The light detector can detect a light emitted from a single molecule object contained in the at least one nanowell.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: June 12, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Chung-Fan Chiou, Rung-Ywan Tsai, Yu-Tang Li, Chih-Tsung Shih, Ming-Chia Li, Chang-Sheng Chu, Shuang-Chao Chung, Jung-Po Chen, Ying-Chih Pu
  • Patent number: 9972526
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a mask layer over a substrate, forming a material layer over the mask layer, forming a first blocking structure and a second blocking structure in the material layer separated from each other, and forming a first opening and a second opening in the material layer aligned with the first blocking structure. The method further includes forming a first spacer on sidewalls of the first opening and a second spacer on sidewalls of the second opening, forming a third opening and a fourth opening in the material layer aligned with the second blocking structure, etching the mask layer through the first opening, the second opening, the third opening, and the fourth opening.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 15, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hsin Tai, Chih-Ching Cheng, Fang-Yi Wu, Yi-Wei Chiu
  • Patent number: 9946598
    Abstract: Systems, apparatuses and methods may provide for recording, if a non-volatile memory (NVM) location satisfies an open circuit condition, open circuit location information associated with the NVM location. Additionally, a shift of one or more bits may be conducting during a write of a codeword to the NVM location to avoid open circuit in the NVM location. Moreover, an end of a parity portion of the codeword may be punctured by an amount of the shift. In one example, the end of the parity portion includes a last circulant of the codeword.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventor: Ravi H. Motwani
  • Patent number: 9941005
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Rambus Inc.
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 9923050
    Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<×<1.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 20, 2018
    Assignees: SILTRONIC AG, IMEC VZW
    Inventors: Sarad Bahadur Thapa, Ming Zhao, Peter Storck, Norbert Werner
  • Patent number: 9911606
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ya-Ting Chang, Wen-Li Cheng, Nian-Fuh Cheng, Ming-Hui Chih, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 9881944
    Abstract: A method of fabricating an array substrate for a liquid crystal display device can include forming a gate line and a gate electrode, and a gate insulating layer; forming an active layer on the gate insulating layer and an ohmic contact layer on the active layer; forming a data line and source and drain electrodes; forming a passivation layer on the source and drain electrodes; and forming a pixel electrode on the passivation layer, in which the ohmic contact layer covers an entire top surface of the active layer between the source and drain electrodes; forming a metallic layer on the gate insulating layer and the ohmic contact layer; etching the metallic layer to faun the data line, and the source drain electrodes, in which a silicide layer is formed on the ohmic contact layer only in the space between the source and drain electrodes; and removing the silicide layer.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 30, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Cheol-Se Kim, Jae-Hyung Jo, Duk-Keun Yoo
  • Patent number: 9882052
    Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert Judson Holt, Jinping Liu, Jody Fronheiser, Bharat Krishnan, Churamani Gaire, Timothy James McArdle, Murat Kerem Akarvardar
  • Patent number: 9875897
    Abstract: A semiconductor device includes line patterns extending in a first direction, and separated from each other in a second direction perpendicular to the first direction. The plurality of line patterns includes at least two line sets, and each of the line sets includes four line patterns consecutively disposed in the second direction and having a length which varies based on location, and the at least two line sets have substantially an identical length.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Patent number: 9847246
    Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 9831115
    Abstract: A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Jeffrey L. Libbert
  • Patent number: 9824934
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Patent number: 9818662
    Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Thomas Eugene Grebs, Simon John Molloy
  • Patent number: 9817822
    Abstract: Embodiments of the present invention address deficiencies of the art in respect to web page layout and provide a novel and non-obvious system for managing white space in a web page. In one embodiment of the invention, a method for managing white space in a web page includes detecting white space adjacent to a non-rectangular shaped portlet rendered on the web page. The method further includes measuring a non-rectangular shape of the white space and selecting a graphic having a shape congruent with the shape of the white space. The method further includes rendering the graphic that was selected into the white space.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Al Chakra, Adam R. Cook, Jonathan J. Lidaka, Ryan E. Smith
  • Patent number: 9812353
    Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon Ahn, Jong Min Baek, Myung Geun Song, Woo Kyung You, Byung Kwon Cho, Byung Hee Kim, Na Ein Lee
  • Patent number: 9812557
    Abstract: A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Kwan Yu, Dong-Suk Shin, Woon-Ki Shin, Cheol-Woo Park, Ryong Ha, Han-Jin Lim