MULTIPLEX CIRCUIT AND DRIVE UNIT USING THE SAME
A multiplex circuit includes: a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points, the switching points beginning with edges of symbol periods of the plurality of input signals; one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output.
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This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-269493, filed on Dec. 10, 2012, the entire contents of which are incorporated herein by reference.
FIELDThe embodiments discussed herein are related to a multiplex circuit and a drive unit using the multiplex circuit, and for example, related to a drive unit that generates a drive signal that drives a light-emitting element by using a multiplex circuit.
BACKGROUNDWith a high transmission speed and a large capacity in a network, a method of transmitting and receiving a signal using an optical transmission path has been spread in place of existing electrical wiring.
In order to perform optical transmission at a high speed, a light-emitting element such as a vertical cavity surface emitting laser (VCSEL) is driven at a high speed. A high-frequency signal is attenuated at a transmission path and the waveform is deteriorated, so that a pre-emphasis method of compensating for the signal on the transmission side beforehand has been used.
As a pre-emphasis type drive circuit, there has been proposed a circuit that combines a drive signal and the delayed signal and generates a drive waveform of the VCSEL (For example, see
In the above-described multiplex circuit, there is a problem of variation in jitter of input waveforms. The jitter variation is attributed to the occurrence of a crosstalk between inputs of the multiplex circuit and variation in collector potentials because the collector ends of the transistors are connected to the common current source. This is a problem specific to a drive circuit that processes a high-speed signal.
SUMMARYAccording to an aspect of the embodiment, a multiplex circuit includes: a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points, the switching points beginning with edges of symbol periods of the plurality of input signals; one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
First, the technical problem in the drive circuit in the related art, which is found by the inventor is described.
As illustrated in
In addition, as illustrated in
Ideally, each of the waveforms is not to be changed even when the delay times t1 and t2 are changed. However, practically, the appearance of jitter is change. It is conceivable that this is why signals the switching points of which are shifted at the taps are input to the multiplex circuit 1130 (“in1”, “in2”, and “in3”), and a crosstalk occurs between the inputs.
For example, when there is no signal at “in1” and “in3”, and a signal is input at “in2” (for convenience, a positive-phase signal and a negative-phase signal are collectively described), a current signal that flows through the transistor Q2 is converted into a voltage signal by a resistor RL, and the potential of the output end out is shaken. Between the transistors Q1, Q2, and Q3, the collector end (drain end in a case of a field-effect transistor (FET)) and the output end are shared, so that a high-speed component of the voltage signal of the output end out is leaked into “in1” and “in3” through the parasitic capacitance CBC. As a result, current that flows through the transistors Q1 and Q3 is not to be changed, however the potential is shaken by the signal that is input to “in2” undesirably.
In the case of general integer bit delay (see
Therefore, in the embodiments, a configuration is proposed in which the collector (drain) potential of the input transistor is stabilized, that is, a crosstalk between the taps may be avoided without the impact from another input. For example, a common base transistor is arranged between the output end and the collector end of each of the input transistors Q1 to Q3 of the taps to which a drive signal and the delayed signal are input to suppress variation in collector potentials of the input transistors. When an FET is used, a common gate transistor is arranged between the output end and the drain end of each of the input transistors T1 to T3 to suppress variation in drain potentials of the input transistors.
Specific configuration examples of the embodiments are described below with reference to accompanying drawings.
By arranging the common base transistor Qc between the collector end of the input transistor Q and the output end, variation in potentials Vc of the collector ends of the input transistors may be suppressed.
The multiplex circuit 30 includes a first differential amplifier unit 40 that performs differential amplification on a drive signal, a second differential amplifier unit 50 that performs differential amplification on the first delayed signal, and a third differential amplifier unit 60 that performs differential amplification on the second delayed signal.
From a pre-emphasis generation circuit that is described later, a positive-phase signal of a drive signal is input to the input transistor Q1p of the first differential amplifier unit 40 (in1p), and a negative-phase signal of the drive signal is input to the input transistor Q1n of the first differential amplifier unit 40 (in1n). The emitter of the input transistor Q1p and the emitter of the input transistor Q1n are connected to a current source 41. The other end of the current source 41 is grounded. The collector of the input transistor Q1p is connected to the emitter of the cascode transistor (common base transistor) Qc1p, and the collector of the input transistor Q1n is connected to the emitter of the cascode transistor (common base transistor) Qc1p. The collector of the common base transistor Qc1p is connected to a resistor RLp and the output end out. The collector of the common base transistor Qc1n is connected to a resistor RLn and the output end outx.
A positive-phase signal of the first delayed signal that is obtained by delaying the drive signal by a time t1 is input to the input transistor Q2p of the second differential amplifier unit 50 (in2p), and a negative-phase signal of the first delayed signal is input to the input transistor Q2n of the second differential amplifier unit 50 (in2n). The emitter of the input transistor Q2p and the emitter of the input transistor Q2n are connected to a current source 51. The other end of the current source 51 is grounded. The collector of the input transistor Q2p is connected to the emitter of the cascode transistor (common base transistor) Qc2, and the collector of the input transistor Q2n is connected to the emitter of the cascode transistor (common base transistor) Qc2p. The collector of the common base transistor Qc2p is connected to the resistor RLp and the output end out. The collector of the common base transistor Qc2n is connected to the resistor RLn and the output end outx.
A positive-phase signal of the second delayed signal that is obtained by delaying the drive signal by a time t2 is input to the input transistor Q3p of the third differential amplifier unit 60 (in3p), and a negative-phase signal of the second delayed signal is input to the input transistor Q3n of the third differential amplifier unit 60 (in3n). The emitter of the input transistor Q3p and the emitter of the input transistor Q3n are connected to a current source 61. The other end of the current source 61 is grounded. The collector of the input transistor Q3p is connected to the emitter of the cascode transistor (common base transistor) Qc3p, and the collector of the input transistor Q3n is connected to the emitter of the cascode transistor (common base transistor) Qc3p. The collector of the common base transistor Qc3p is connected to the resistor RLp and the output end out. The collector of the common base transistor Qc2n is connected to the resistor RLn and the output end outx.
When a base-emitter potential difference of the common base transistor Qc is represented as “VBE”, a collector potential Vc of the input transistor is represented by “Vc=Vb−VBE”. “Vb” is invariable, and base-emitter voltage VBE of each of the common base transistor Qc is also substantially invariable, so that the collector potential Vc of the input transistor is stabilized.
A cascode stage 70A is inserted between an output end and the collectors of input transistors Q of the multiplex circuit 30A. The collectors of common base transistors Qc1p, Qc2p, and Qc3p of the cascode stage 70A are connected to the output end out in common, and connected to a bias current source 91 through a resistor RLp and an inductor L1p. The collectors of common base transistors Qc1n, Qc2n, and Qc3n are connected to the dummy load 80 in common, and connected to a bias current source 93 through a resistor RLn and an inductor L1n.
A resistor R4 is connected to a node between the resistor RLp and the inductor L1p, a resistor R3 is connected to a node between the resistor RLn and the inductor L1n, and the resistor R3 and the resistor R4 are connected to each other in series. A node between the resistors R3 and R4 is connected to a bias current source 92. The bias current source 92 changes bias current and controls current that flows through the VCSEL and the dummy load. The dummy load 80 has a characteristic that is similar to that of the VCSEL, and a connection point between the resistors R3 and R4 may be regarded as a virtual ground point, so that, by using the resistors R3 and R4, and the resistors RLn and RLp, output impedance of the drive unit 10A is matched with input impedance of the VCSEL and input impedance of the dummy load 80.
The pre-emphasis generation circuit 20 includes a first delay circuit 21, a second delay circuit 22, a first amplifier 23, a second amplifier 24, and a third amplifier 25. The first delay circuit 21 delays an input drive signal by “t1” and outputs the first delayed signal. The second delay circuit 22 further delays the output first delay circuit 21 and outputs the second delayed signal that includes the delay amount t2.
The first amplifier 23 generates differential signals on the basis of the input drive signal and inputs differential signals in1p and in1n to the input transistors Q1p and Q1n of the first differential amplifier unit 40A of the multiplex circuit 30A, respectively. The second amplifier 24 generates differential signals on the basis of the first delayed signal and inputs differential signals in2p and in2n to the input transistors Q2p and Q2n of the second differential amplifier unit 50A, respectively. The third amplifier 25 generates differential signals on the basis of the second delayed signal and inputs differential signals in3p and in3n to the input transistors Q3p and Q3n of the third differential amplifier unit 60A, respectively.
When the signals to which the delay differences are given in the pre-emphasis generation circuit 20 are combined in the multiplex circuit 30A, output of a VCSEL drive signal is performed in a state in which the rise and fall of the drive signal are corrected (emphasized or suppressed) beforehand.
In the drive unit 10A, by arranging the common base transistor between the output end and the collector of the input transistor Q of the multiplex circuit 30A, variation in collector potentials of the input transistors Q is reduced.
In the multiplex circuit 30B according to the second embodiment, a cascode stage 70B that is used in common is arranged between the collector ends and the output ends of input transistors Q1, Q2, and Q3.
The collectors of the input transistors Q1p, Q2p, and Q3p are connected to the emitter of a common base transistor Qcp in common. The collectors of the input transistors Q1n, Q2n, and Q3n are connected to the emitter of the common base transistor Qcn in common.
The emitter of the common base transistor (cascode transistor) Qc is shared among the plurality of taps, so that the sizes of the common base transistors Qcp and Qcn that are connected to the output ends may be reduced. The parasitic capacitance when viewed from the output end becomes small, thereby being advantageous to a high-speed operation.
The multiplex circuit 30C according to the third embodiment uses an FET instead of a bipolar transistor. The multiplex circuit 30C includes a first differential amplifier unit 40C, a second differential amplifier unit 50C, and a third differential amplifier unit 60C. A differential signal of an input drive signal is input to the first differential amplifier unit 40C (in1p and in1n). A differential signal of the first delayed signal is input to the second differential amplifier unit 50C (in2p and in2n). A differential signal of the second delayed signal is input to the third differential amplifier unit 60C (in3p and in3n).
The multiplex circuit 30C includes a cascode stage 70C that is inserted between the output ends out/outx and the collector ends of input transistors T1n, T1p, T1n, T2p, T2n, T3p, and T3n (hereinafter collectively referred to as “input transistor T” or “input transistors T1, T2, and T3”). In the cascode stage 70C, common gate transistors Tc1p, Tc1n, Tc2p, Tc2n, Tc3p, and Tc3n (hereinafter collectively referred to as “common gate transistor Tc”) are respectively connected to the corresponding input transistors T in series. The gates of the common gate transistors Tc are connected to a potential Vg in common. The potential Vg is potential that is desired to pass the same amount of current through the common gate transistors Tc when current flows through the input transistors T.
By connecting the common gate transistor Tc between the drain of the input transistor Q and the output end, variation in potentials VD of the drain ends of the input transistors is suppressed.
When gate-to-source threshold voltage of the common gate transistor Tc is represented as Vth, the drain potential VD of the input transistor may be represented by “VD=Vg−Vth”. “VD” is invariable, and the gate-to-source voltage Vth of each of the common gate transistors Qc is also substantially invariable, so that the drain potential VD of the input transistor is stabilized.
The collectors of input transistors Q1p, Q2p, and Q3p are respectively connected to the emitters of the corresponding common base transistors Qc1p, Qc2p, and Qc3p. The collectors of the common base transistors Qc1p, Qc2p, and Qc3p are connected to one end side of a resistor RLP, and connected to the base of a transistor Q4 in common. The other end of the resistor RLP is connected to a current source 82 and the collector of the transistor Q4.
The collectors of input transistors Q1n, Q2n, and Q3n are respectively connected to the emitters of the corresponding common base transistors Qc1n, Qc2n, and Qc3n. The collectors of common base transistors Qc1n, Qc2n, and Qc3n are connected to one end side of a resistor RLn. The other end of the resistor RLn is connected to the current source 82 and the collector of the transistor Q4.
The collector of the transistor Q4 is connected to a reference potential Vcc through a capacity 81. When a synthetic signal of outputs of the input transistors Q1 to Q3 is input to the base of the transistor Q4, a signal that reflects directly the amplitude of the base is output from the emitter of the transistor Q4. As described above, the transistor Q4 functions as an emitter follower. The emitter output of the transistor Q4 drives the VCSEL that is connected to the output end out.
Such a configuration does not desire a dummy load, so that redundant current (current that flows through the dummy load) does not occur.
The capacity of the current source 82 is not seen from the output end out, thereby being advantageous to the speedup. In the configuration in
In such a configuration, the cascode connection of the common base transistor Qc is performed on the collector of the input transistor Q, so that the collector potentials of the input transistors Q are stabilized.
In the drive unit of the above-described embodiments, even when signals that are obtained by performing analog delay (variable delay adjustment) are combined in order to achieve high-speed drive of the VCSEL, a crosstalk between input signals may be reduced and variation in jitter may be suppressed.
In the first embodiment to the fourth embodiment, the pre-emphasis generation circuit 20 that includes three taps is employed, and the number of taps is not limited as long as the pre-emphasis generation circuit 20 includes a plurality of taps. The light-emitting element is not limited to the VCSEL, and the drive unit may drive any light-emitting element that oscillates at high speed. Any combination of the first embodiment to the fourth embodiment may be performed.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims
1. A multiplex circuit, comprising:
- a plurality of input transistors that correspondingly receive a plurality of input signals of different switching points;
- one of a common base transistor that is connected to a collector of the input transistor and a common gate transistor that is connected to a drain of the input transistor; and
- an output end that is connected to one of the collector of the common base transistor and the drain of the common gate transistor, and to which a signal that is obtained by combining the plurality of input signals is output.
2. The multiplex circuit according to claim 1, wherein the switching points are configured to be edges of one bit times of the plurality of input signals
3. The multiplex circuit according to claim 1, wherein
- one of the common base transistor and the common gate transistor is a common transistor that is shared among the plurality of input transistors, and
- the collector of each of the plurality of input transistors is connected to an emitter of the common base transistor or the drain of each of the plurality of input transistors is connected to an emitter of the common gate transistor.
4. The multiplex circuit according to claim 1, wherein
- one of the common base transistor and the common gate transistor is arranged so as to correspond to each of the plurality of input transistors, and
- the collector of each of the plurality of input transistors is connected, in series, to an emitter of the corresponding common base transistor or the drain of each of the plurality of input transistors is connected, in series, to an emitter of the corresponding common gate transistor.
5. The multiplex circuit according to claim 1, wherein
- one of the plurality of input transistors receives a waveform signal that corresponds to an input drive signal, and another one of the plurality of input transistors receives a delayed signal that is obtained by performing analog delay adjustment on the input drive signal.
6. The multiplex circuit according to claim 1 further comprising:
- a plurality of second input transistors each of which forms a differential pair with each of the plurality of input transistors; and
- one of a second common base transistor that is connected, in series, to a collector of each of the plurality of second input transistors and a second common gate transistor that is connected, in series, to a drain of each of the plurality of second input transistors.
7. The multiplex circuit according to claim 1, wherein
- one of the collector of the common base transistor and the drain of the common gate transistor is connected to a power source through a load resistor.
8. The multiplex circuit according to claim 1, wherein
- one of the collector of the common base transistor and the drain of the common gate transistor is connected to a power source through a direct current source.
9. A drive unit, comprising:
- a pre-emphasis generation circuit that generates a plurality of signal waveforms of different switching points, the switching points being configured to be set as sedges of one bit times of the plurality of input signals; and
- a multiplex circuit that generates a drive signal by combining the plurality of signal waveforms that are output from the pre-emphasis generation circuit, and wherein
- the multiplex circuit includes:
- a plurality of input transistors that uses the plurality of signal waveforms as inputs;
- one of a common base transistor that is connected to a collector of the input transistor, and a common gate transistor that is connected to a drain of the input transistor; and
- an output end that is connected to one of a collector of the common base transistor and a drain of the common gate transistor, and to which a drive signal that drives an external light-emitting element is output.
10. The drive unit according to claim 9 further comprising:
- one of a common collector transistor a base of which is connected to the collector of the common base transistor and an emitter of which is connected to the output end, and a common drain transistor a gate of which is connected to the drain of the common gate transistor and a source of which is connected to the output end.
11. The drive unit according to claim 9, wherein
- the multiplex circuit further includes:
- a plurality of second input transistors each of which forms a differential pair with each of the plurality of input transistors, and
- one of a second common base transistor that is connected, in series, to a collector of each of the plurality of second input transistors and a second common gate transistor that is connected, in series, to a drain of each of the plurality of second input transistors, and
- the drive unit further includes:
- a dummy load that is connected to one of a collector of the second common base transistor and a drain of the second common gate transistor, and
- the drain of one of the second common base transistor and the second common gate transistor is, in series, connected to a resistor, an inductor, and a current source.
12. The drive unit according to claim 10, wherein
- the dummy load has a characteristic similar to the light-emitting element.
Type: Application
Filed: Oct 28, 2013
Publication Date: Jun 12, 2014
Patent Grant number: 9350343
Applicant: FUJITSU LIMITED (Kawasahi-shi)
Inventor: Mariko KASE (Isehara)
Application Number: 14/064,825
International Classification: H03K 17/16 (20060101);