FLIP-CHIP WAFER LEVEL PACKAGE AND METHODS THEREOF
An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
This application is a divisional of U.S. patent application Ser. No. 13/731,123 filed Dec. 31, 2012, which is incorporated herein by reference in its entirety.
FIELD OF THE DISCLOSUREThis disclosure relates to devices and methods of manufacturing electronics, and more particularly, to electronic packages and manufacturing methods thereof.
BACKGROUNDIn manufacturing integrated circuits (ICs), the ICs, called chips or dies, are generally packaged prior to distribution and integration with other electronic assemblies. This packaging usually includes encapsulating the chips in a material and providing electrical contacts on the exterior of the package to provide an interface to the chip. Chip packaging, amongst other things, may provide protection from contaminants, provide mechanical support, disperse heat, and reduce thermo-mechanical stresses.
Because of the relation between IC fabrication and IC packaging, IC packaging also must generally progress with the rapid advancements in the semiconductor industry. In particular, there is an ongoing to desire to package ICs and other electronics to make them smaller, faster, and more reliable.
SUMMARYIn a first aspect of this disclosure, an electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
In another aspect of this disclosure, a method for manufacturing an electronic package is provided. The method includes providing a flip-chip component having a first die coupled to a flip-chip substrate, adhering the first die to a second die, forming an encapsulation compound around the first die and the second die, drilling a set of through encapsulant vias (TEVs) from a first side of the electronic package to the flip-chip substrate located on a second side of the electronic package, filling the set of TEVs with an electrically conductive material, and applying a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
In a further aspect of this disclosure, a memory device includes a flip-chip component having a first die coupled to a flip-chip substrate, a second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package. The first die and/or the second die includes a memory function.
In yet another aspect of this disclosure, an electronic package includes a first electronic package, and a second electronic package. The second electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, a second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package. The first electronic package is stacked together with the second electronic package to form a package-on-package (PoP) electronic package.
To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
Reference will now be made to figures wherein like structures will be provided with like reference designations. It is understood that the drawings are diagrammatic and schematic representations of exemplary embodiments of the invention, and are not limiting of the present invention nor are they necessarily drawn to scale.
Chips (alternatively referred to herein as dies) are generally packaged prior to distribution and integration with other electronic assemblies. This packaging usually includes encapsulating the chips in a material and providing electrical contacts on the exterior of the package to provide an interface to the chip. Chip packaging, amongst other things, may provide protection from contaminants, provide mechanical support, disperse heat, and reduce thermo-mechanical stresses.
Stacking multiple chips within a single chip package is an increasingly common packaging requirement in order to reduce, for example, overall assembly size, functional circuit speed, and overall costs.
While flip-chip wire-bond package 10, and other wire bond packaging, provides a means for package production, ongoing advancements in the industry have pushed towards lower package profiles and increased electrical performance.
Through Silicon Vias (TSVs) provide a connection through the semiconductor wafer for stacking purposes. TSVs may provide better electrical performance and a lower profile. Costs and reliable supply chain management, however, may generally limit widespread TSV usage within industry.
Die 1′ is arranged on top of die 3′, and encapsulation compound 7′ is formed around die 1′ and die 3′. Die 1′ may be adhered to die 3 prior to forming encapsulation compound 7′ by applying an adhesive 15 such as a die attach film (DAF) between dies 1′ and 3′. Adhesive 15 may be applied, for example, through laminating, printing, or dispensing the adhesive onto one of the dies and then placing the remaining die onto the adhesive prior to curing.
A set of through encapsulant vias (TEVs) 19 provide electrical connections through the encapsulation compound 7′ of flip-chip wafer-level package 10′. Additionally, a redistribution layer 17 electrically connects TEVs 19 to die 1′. Flip-chip wafer-level package 10′ further includes solder balls 13′ adhered to the flip-chip substrate 11′, and possibly a protection layer 16 covering redistribution layer 17 and the TEVs 19 to protect the otherwise exposed components 16′. Flip-chip wafer-level package 10′ may also include a dielectric layer between the second die and the redistribution layer.
Dies 1′ and 3′ may be fabricated according to standard semiconductor manufacturing processes. That is, generally after an ingot is grown it is sliced into wafers. Areas of the wafer may undergo deposition, removal, patterning, and doping processes. Once the wafer has been processed, the wafer is generally mounted and diced into individual dies. Die 3′, in particular, is further processed and provided as part of the flip-chip component 18. That is, die 3′ is processed using flip-chip technology such that die 3′ is coupled to flip-chip substrate 11′ thereby forming the flip-chip component 18.
Encapsulation compound 7′ is generally composed of a plastic material, but other materials, such as ceramics and metals and silicon or glass, may be used if desired. Thermosetting molding compounds, in particular, are a type of plastic material based on epoxy resins. These types of compounds have historically been used in electronic packaging applications. Thermoplastics, such as a high purity fluoropolymer, are another type of plastic materials which may be used as encapsulation compound 7′.
TEVs 19 are formed by drilling holes through encapsulation compound 7′ and then filling the drilled holes with an electrically conductive material. The drilling of the TEVs holes may be performed, for example, with a mechanical drill, a laser, or through chemical etching.
Contacts on die 1′ may be arranged in a variety of ways. As depicted in
Electronic packages built in accordance with flip-chip wafer-level package 10′ may further include, or be combined with, one or more of the following features. Die 1′ and/or die 3′ may include a memory function. For example, flip-chip wafer-level package 10′ may implement dynamic random access memory (DRAM). An electronic package may include a first electronic package and a second electronic package, at least one of which is built in accordance with flip-chip wafer-level package 10′; the first electronic package may be stacked together with the second electronic package to form a package-on-package (PoP) electronic package. In this way, dies 1′ and 3′ as depicted in
Flip-chip wafer-level package 10′ may include additional dies stacked on die 3′ of the flip-chip component 18. That is, flip-chip wafer-level package 10′, in addition to dies 1′ and 3′, may include more dies, such that the total number of dies in flip-chip wafer-level package 10′ is three or more.
Flip-chip wafer-level package 10′ may be constructed such that the distance between the set of contacts on the second die and a surface of the first side of the electronic package is less than about 20 μm. Such a configuration reduces package size and may reduce overall electronic assembly size.
Further details regarding the manufacturing of wafer-level package 10′ are discussed below with reference in particular to
Referencing
In
In
Method 30 then includes, as shown in
Method 30 further includes, as shown in
In
Method 30 further includes drilling 27, as shown in
Method 30 then includes, as shown in
In
Finally, in
In addition to producing a smaller, more efficient package, flip-chip wafer-level package 10′ allows for separately testing and burning-in flip-chip component 18 between fabrication processes. That is, flip-chip component 18 may be separately fabricated, tested, and burned-in, prior to continuing manufacture of flip-chip wafer-level package 10′ .
Referencing
In
Similar to the process flow heretofore described, in
As shown in
In
In
In
In
In
Finally, in
Additional dies may be configured in accordance with the above description. For example, as shown in
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative, not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
Claims
1. A method for manufacturing an electronic package, the method comprising:
- providing a flip-chip component having a first die coupled to a flip-chip substrate;
- adhering the first die to a second die;
- forming an encapsulation compound around the first die and the second die;
- drilling a set of through encapsulant vias (TEVs) from a first side of the electronic package to the flip-chip substrate located on a second side of the electronic package;
- filling the set of TEVs with an electrically conductive material; and
- applying a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
2. The method of claim 1 further comprising applying a protection layer covering the redistribution layer and the TEVs.
3. The method of claim 1 further comprising adhering solder balls to the flip-chip substrate.
4. The method of claim 1 further comprising separately testing and burning-in the flip-chip component.
5. The method of claim 1 further comprising:
- adhering the second die to a mold carrier with a releasable adhesive; and
- removing the mold carrier from the second die.
6. The method of claim 1 further comprising:
- adhering the flip-chip component to a mold carrier with a releasable adhesive; and
- removing the mold carrier from the flip-chip component.
7. The method of claim 6 further comprising coupling a set of posts onto the set of contacts on the second die.
8. The method of claim 5 wherein the posts comprise copper.
9. The method of claim 6 further comprising:
- forming the encapsulation compound over the second die; and
- exposing the posts.
10. The method of claim 9 wherein exposing the posts comprises grinding the encapsulation compound until the posts are exposed, the encapsulation compound forming a substantially planer surface.
11. The method of claim 9 wherein exposing the posts comprises laser drilling the encapsulation compound.
Type: Application
Filed: Mar 26, 2014
Publication Date: Jul 24, 2014
Inventor: Thorsten Meyer (Regensburg)
Application Number: 14/225,647
International Classification: H01L 23/00 (20060101);