Flip-chip-type Assembly Patents (Class 438/108)
  • Patent number: 11450587
    Abstract: An electronic device includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a plurality of processing components on and/or in the stack, a process control component coupled with at least part of the processing components for transmitting signals and configured for controlling processes executed by the processing components and/or by the process control component, and a heat removal structure on or above which at least one of the process control component and the processing components is arranged.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: September 20, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Marco Gavagnin, Gerald Weis, Markus Leitgeb, Gernot Grober, Young Hy Jung
  • Patent number: 11444042
    Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Andrew James Brown, Ying Wang, Chong Zhang, Lauren Ashley Link, Yikang Deng
  • Patent number: 11421943
    Abstract: A vapor chamber that includes a housing having a first sheet and a second sheet opposing each other and having outer edges bonded to each other along a sealing portion; a working fluid sealed in the housing; and a wick disposed on an internal main surface of the first sheet opposing the second sheet. At least one of the first sheet and the second sheet includes at least one groove between the wick and the sealing portion when viewed in a cross section of the housing taken in a direction perpendicular to a direction in which the first sheet and the second sheet oppose each other.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 23, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takuo Wakaoka
  • Patent number: 11417616
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • Patent number: 11404288
    Abstract: A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel by placing a plurality of semiconductor die on a major side of a carrier substrate and encapsulating with an encapsulant the plurality semiconductor die and the major side of the carrier substrate. A plurality of warpage control features are formed with the encapsulant while encapsulating. The method further includes placing the panel onto a warpage control fixture to substantially flatten the panel. The plurality of warpage control features interlock with mating features of the warpage control fixture.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 2, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Scott M. Hayes, Zhiwei Gong, Vivek Gupta, Richard Te Gan
  • Patent number: 11393771
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 11335827
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 17, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11302537
    Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate including a substrate, a pad, and a polymer layer. The polymer layer is over the substrate and the pad, and the polymer layer has a first opening exposing the pad. The method includes forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with and conformally covers the polymer layer and the pad. The method includes forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method includes bonding a chip to the wiring substrate through a conductive bump. The conductive bump is between the nickel layer and the chip.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Ching Hsu, Yu-Huan Chen, Chen-Shien Chen
  • Patent number: 11289422
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact and a first bonding alignment mark. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact and a second bonding alignment mark. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 29, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Meng Yan, Jia Wen Wang, Si Ping Hu, Shun Hu
  • Patent number: 11289410
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee
  • Patent number: 11270946
    Abstract: The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: March 8, 2022
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yong Chen, David Gani
  • Patent number: 11270990
    Abstract: A contoured package on package joint and a method for making the same are disclosed herein. A method for forming a device comprises providing a substrate having a package land and forming a mounting stud on the package land. A molded underfill is applied to the substrate and in contact with the mounting stud. A contoured stud surface is formed on the mounting stud is contoured and connecting member attached to the contoured stud surface with a second package attached to the connecting member. The connecting member may be solder and have a spherical shape. The contoured stud surface may be etched or mechanically formed to have a hemispherical shape conforming to the connecting member shape.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 11264312
    Abstract: An object of the present invention is to achieve both securing an insulation distance and securing a chip mounting area in a non-insulated power module. A non-insulated power module includes a plurality of die pads, a plurality of semiconductor chips mounted on upper surfaces of the plurality of die pads, and a package sealing the semiconductor chips, in which lower surfaces of the plurality of die pads are exposed from a lower surface of the package, on the lower surface of the package, first grooves are formed in areas between the plurality of die pads, and the plurality of die pads have a trapezoidal cross-sectional shape in the thickness direction, in which an area of an upper surface is larger than an area of the lower surface.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 11244983
    Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wen-Chun You, Hung Cho Wang, Yen-Yu Shih
  • Patent number: 11209799
    Abstract: A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 28, 2021
    Assignee: PRIMO1D
    Inventors: Emmanuel Arene, Robin Lethiecq, Pavina Nguyen, Christopher Mackanic
  • Patent number: 11211333
    Abstract: The present disclosure describes a semiconductor structure includes a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Noor Mohamed Ettuveettil
  • Patent number: 11206739
    Abstract: A method of potting e.g. a stack of printed circuit boards, the method comprising applying a first potting material to selected regions of the circuit to be potted and then applying a second, different, potting material over the circuit to be potted.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 21, 2021
    Assignee: GOODRICH ACTUATION SYSTEMS LIMITED
    Inventors: David Abraham, Stuart Waller
  • Patent number: 11201133
    Abstract: A bonding apparatus and method includes: a stage configured to fix a first electric component; a pressing unit configured to press a conductive adhesive film and a second electric component onto the first electric component; a driver configured to control movement of the pressing unit along a direction; and a plurality of sensors at different positions on the stage and configured to sense a change in capacitance with the pressing unit, wherein the pressing unit includes a flat metal material in first regions facing the plurality of sensors.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 14, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joo Nyung Jang
  • Patent number: 11177156
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Patent number: 11167375
    Abstract: A technique to additively print onto a dissimilar material, especially ceramics and glasses (e.g., semiconductors, graphite, diamond, other metals) is disclosed herein. The technique enables manufacture of heat removal devices and other deposited structures, especially on heat sensitive substrates. It also enables novel composites through additive manufacturing. The process enables rapid bonding, orders-of-magnitude faster than conventional techniques.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: November 9, 2021
    Assignee: The Research Foundation for the State University of New York
    Inventors: Scott N. Schiffres, Arad Azizi
  • Patent number: 11171018
    Abstract: A method of fabricating a semiconductor device with improved quality and an encapsulant are provided. The method may include coating a chip wafer including a plurality of semiconductor chips with an encapsulant, performing a pre-curing process to bring the encapsulant into a B-stage, dicing the chip wafer to divide the chip wafer into a plurality of semiconductor chips, forming a chip stack by stacking the semiconductor chip on the base wafer in such a way that a coupling electrode on the base wafer and a bump electrode of each of the semiconductor chips face each other with a conductive adhesive element interposed therebetween, performing a reflow process on the chip stack under pressurized gas to bond the coupling electrode and the bump electrode to each other with the conductive adhesive element interposed therebetween, and performing a post-curing process on the chip stack under pressurized gas to bring the encapsulant into a C-stage.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Takahiro Tokumiya, Tatsuya Ishimoto
  • Patent number: 11158567
    Abstract: A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 26, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Vivek Kishorechand Arora, Benjamin Allen Samples
  • Patent number: 11145622
    Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 11133275
    Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 28, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yunlong Kong
  • Patent number: 11121051
    Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11094567
    Abstract: A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 17, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda, Tetsuo Takano
  • Patent number: 11094653
    Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 17, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11088116
    Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11075182
    Abstract: A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Wei Chen, An-Jhih Su
  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Patent number: 11043420
    Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 22, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: George Chang, Yusheng Lin, Gordon M. Grivna, Takashi Noma
  • Patent number: 11018104
    Abstract: A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 10971466
    Abstract: A high frequency module includes a transmission power amplifier, a bump electrode connected to the transmission power amplifier, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view of the mounting board, a board main part placed outside the via conductor, and an insulating part placed inside the via conductor, and the bump electrode and the via conductor are connected while at least partially overlapping each other in the foregoing plan view, and the board main part and the insulating part are each composed of an insulating material of the same kind.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuuki Fukuda
  • Patent number: 10971376
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate main body to which external connection terminals are attached, attaching a protective member to the substrate main body to cover the external connection terminals, mounting a semiconductor chip on a surface of the substrate main body that is opposite from the protective member, and removing the protective member from the substrate main body.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Seon Hwang, Hyeong Gi Lee
  • Patent number: 10964657
    Abstract: A radio-frequency module includes: a transmission power amplifier that includes first and second amplification transistors that are cascade connected to each other; and a mounting substrate that has first and second main surface that face each other, the transmission power amplifier being mounted on the first main surface. The first amplification transistor is arranged in a final stage and has a first emitter terminal. The second amplification transistor is arranged in a stage preceding the first amplification transistor and has a second emitter terminal. The mounting substrate has first to fourth ground electrode layers in order of proximity to the first main surface. The first emitter terminal and the second emitter terminal are not electrically connected to each other via an electrode on the first main surface and are not electrically connected to each other via the first ground electrode layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 30, 2021
    Assignee: MURATA MANUFACTURING CO.. LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuki Fukuda
  • Patent number: 10957601
    Abstract: Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Wenyu Xu, Xin Miao
  • Patent number: 10950569
    Abstract: A high frequency module includes a transmission power amplifier, a bump electrode connected to a principal surface of the transmission power amplifier and having an elongated shape in a plan view of the principal surface, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view, the length direction of the bump electrode and the length direction of the via conductor are aligned in the plan view, and the bump electrode and the via conductor are connected in an overlapping area where the bump electrode and the via conductor overlap at least partially in the plan view, and the overlapping area is an area elongated in the length direction.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuki Fukuda
  • Patent number: 10937682
    Abstract: A semiconductor tool and methods of forming semiconductor device assemblies. The semiconductor tool is a bond tip having a vacuum port and a plurality of purge ports with channels coupling the vacuum port with the purge ports. Air may be withdrawn through the vacuum to create a vacuum on the bottom of the bond tip to selectively couple a semiconductor device with the bond tip. The bond tip positions the semiconductor device on top of a stack of semiconductor devices to form a semiconductor device assembly. The assembly may be heated to reflow interconnects between the semiconductor device and the top device of the stack of semiconductor devices. Fluid provided through the purge ports may help to counter warpage of the semiconductor device to help form adequate interconnects between the devices. Fluid may also be provided through the vacuum port to counter the warpage.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Yet Hong Tan
  • Patent number: 10892314
    Abstract: A stretchable display device comprises a lower substrate; a plurality of island substrates spaced apart from each other and disposed on the lower substrate; a plurality of pixels defined on the plurality of island substrates; a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 12, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kihan Kim, Hyokang Lee
  • Patent number: 10854527
    Abstract: A semiconductor device package includes a circuit layer, an electronic component, an electronic component, a first passivation layer and a second passivation layer. The circuit layer has a first surface. The electronic component is disposed on the first surface of the circuit layer. The first passivation layer is disposed on the first surface of the circuit layer. The first passivation layer has a first surface facing away the circuit layer. The second passivation layer is disposed on the first surface of the first passivation layer. The second passivation layer has a second surface facing away the circuit layer. A uniformity of the first surface of the first passivation layer is greater than a uniformity of the second surface of the second passivation layer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10854703
    Abstract: A stretchable display device comprises a lower substrate; a plurality of island substrates spaced apart from each other and disposed on the lower substrate; a plurality of pixels defined on the plurality of island substrates; a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 1, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kihan Kim, Hyokang Lee
  • Patent number: 10840224
    Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 10804177
    Abstract: A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 13, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10790160
    Abstract: This invention relates generally to ID frequency identification (RFID) transponders and receivers. More specifically to the methods, apparatus and systems of the fabrication of the transponders and receivers. In one example embodiment, to methods, apparatus, and systems to form effective barriers for devices having a layer structure, including encapsulating at least a portion of the side of the devices from being degraded due to impurity penetration into a laminate structure of the devices, which can cause corrosion or malfunction of the devices.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: September 29, 2020
    Assignee: SMARTRAC TECHNOLOGY GmbH
    Inventors: Laurence Singleton, Ray Freeman
  • Patent number: 10780531
    Abstract: A solder ball includes 0.1% by mass or more and 10% by mass or less of In and a remainder of Sn. The ball has a yellowness (b*) in an L*a*b* color system of 2.8 or more and 15.0 or less and a lightness (L*) of 60 or more and 100 or less. The ball further includes at least one element selected from a group of 0% by mass or more and 4% by mass or less of Ag, 0% by mass or more and 1.0% by mass or less of Cu, 0% to 3% by mass in total of Bi and/or Sb, and 0% to 0.1% by mass in total of an element selected from a group of Ni, Co, Fe, Ge, and P, excluding a solder ball including 3% by mass of Ag, 0.5% by mass of Cu, 0.2% by mass of In and a remainder of Sn.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyoshi Kawasaki, Yuri Nakamura, Osamu Munekata, Kaichi Tsuruta
  • Patent number: 10777720
    Abstract: A light emitting module includes a first light transmissive insulator, a conductive circuitry layer formed on a surface of the first light transmissive insulator, a second light transmissive insulator disposed so as to face the conductive circuitry layer, a light emitting element disposed between the first light transmissive insulator and the second light transmissive insulator, and connected to the conductive circuitry layer, and a third light transmissive insulator which is disposed between the first light transmissive insulator and the second light transmissive insulator, and which is thermosetting.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10763131
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Patent number: 10763221
    Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 1, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Zhiqiang Niu, Kuang Ming Chang, Lin Chen, Ning Sun, QiHong Huang, Tzu-Hsin Lu
  • Patent number: 10746524
    Abstract: Disclosed is a film thickness detection device, including a common unit (1) and a detection unit (2); the common unit (1) comprises at least one common electrode (11); the detection unit (2) comprises at least one sensor chip (21) and a signal processing unit (23); the sensor chips (21) are opposite to the common unit (1) in a first direction and are arranged at intervals; the spaces between the common unit (1) and the sensor chips (21) form a transport channel for a to-be-tested film; each of the sensor chips (21) comprises at least one row of multiple detection electrodes (211) arranged along a second direction; the second direction is perpendicular to a moving direction of the to-be-tested film; the first direction is perpendicular to a first plane; the first plane is parallel to the second direction; the sensor chips (21) are configured to induce electrical signals on the common electrodes (11) and output the electrical signals; and the signal processing unit (23) is electrically connected with the sensor
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 18, 2020
    Assignee: WEIHAI HAULING OPTO-ELECTRONICS CO., LTD.
    Inventor: Wuchang Qi
  • Patent number: 10741507
    Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 11, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Behrooz Mehr, Fernando Chen, Emmanuel de los Santos, Alex Kungo