Flip-chip-type Assembly Patents (Class 438/108)
  • Patent number: 11145622
    Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 11133275
    Abstract: A method for manufacturing a bond pad structure includes providing a substrate structure including a substrate, a first metal layer on the substrate, and a passivation layer on the first metal layer, the passivation layer having an opening extending to the first metal layer; and filling the opening of the passivation layer with a second metal layer. The bond pad structure has a significantly increased thickness compared with the thickness of the exposed portion of the first metal layer in the opening, thereby ensuring wire bonding reliability and yield.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: September 28, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Yunlong Kong
  • Patent number: 11121051
    Abstract: Semiconductor packages and methods of forming the same are disclosed. a semiconductor package includes a die and an underfill. The die is disposed over a surface and includes a first sidewall. The underfill encapsulates the die. The underfill includes a first underfill fillet on the first sidewall, and in a cross-sectional view, a second sidewall of the first underfill fillet has a turning point.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11094567
    Abstract: A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 17, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda, Tetsuo Takano
  • Patent number: 11094653
    Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 17, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11088116
    Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11075182
    Abstract: A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Wei Chen, An-Jhih Su
  • Patent number: 11063009
    Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Sakata, Toshihiko Akiba, Takuo Funaya, Hideaki Tsuchiya, Yuichi Yoshida
  • Patent number: 11043420
    Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 22, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: George Chang, Yusheng Lin, Gordon M. Grivna, Takashi Noma
  • Patent number: 11018104
    Abstract: A semiconductor structure includes a first substrate, a first dielectric layer disposed over the first substrate, a plurality of first bonding pads disposed in the first dielectric layer, a plurality of second bonding pads disposed in the first dielectric layer, a second substrate, and a second dielectric layer disposed over the second substrate. The first bonding pads have a first width. The second bonding pads have a second width greater than the first width. The second bonding pads are arranged to form a frame pattern surrounding the first bonding pads. A portion of the second dielectric layer is in physical contact with the second bonding pads. The first bonding pads and the second bonding pads are arranged to form a plurality of columns and a plurality of rows. Two of the second bonding pads are disposed at two opposite ends of each column and two opposite ends of each row.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 10971376
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate main body to which external connection terminals are attached, attaching a protective member to the substrate main body to cover the external connection terminals, mounting a semiconductor chip on a surface of the substrate main body that is opposite from the protective member, and removing the protective member from the substrate main body.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Seon Hwang, Hyeong Gi Lee
  • Patent number: 10971466
    Abstract: A high frequency module includes a transmission power amplifier, a bump electrode connected to the transmission power amplifier, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view of the mounting board, a board main part placed outside the via conductor, and an insulating part placed inside the via conductor, and the bump electrode and the via conductor are connected while at least partially overlapping each other in the foregoing plan view, and the board main part and the insulating part are each composed of an insulating material of the same kind.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: April 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuuki Fukuda
  • Patent number: 10964657
    Abstract: A radio-frequency module includes: a transmission power amplifier that includes first and second amplification transistors that are cascade connected to each other; and a mounting substrate that has first and second main surface that face each other, the transmission power amplifier being mounted on the first main surface. The first amplification transistor is arranged in a final stage and has a first emitter terminal. The second amplification transistor is arranged in a stage preceding the first amplification transistor and has a second emitter terminal. The mounting substrate has first to fourth ground electrode layers in order of proximity to the first main surface. The first emitter terminal and the second emitter terminal are not electrically connected to each other via an electrode on the first main surface and are not electrically connected to each other via the first ground electrode layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 30, 2021
    Assignee: MURATA MANUFACTURING CO.. LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuki Fukuda
  • Patent number: 10957601
    Abstract: Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Wenyu Xu, Xin Miao
  • Patent number: 10950569
    Abstract: A high frequency module includes a transmission power amplifier, a bump electrode connected to a principal surface of the transmission power amplifier and having an elongated shape in a plan view of the principal surface, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view, the length direction of the bump electrode and the length direction of the via conductor are aligned in the plan view, and the bump electrode and the via conductor are connected in an overlapping area where the bump electrode and the via conductor overlap at least partially in the plan view, and the overlapping area is an area elongated in the length direction.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsunari Nakazawa, Takanori Uejima, Motoji Tsuda, Yuji Takematsu, Dai Nakagawa, Tetsuro Harada, Masahide Takebe, Naoya Matsumoto, Yoshiaki Sukemori, Mitsunori Samata, Yutaka Sasaki, Yuki Fukuda
  • Patent number: 10937682
    Abstract: A semiconductor tool and methods of forming semiconductor device assemblies. The semiconductor tool is a bond tip having a vacuum port and a plurality of purge ports with channels coupling the vacuum port with the purge ports. Air may be withdrawn through the vacuum to create a vacuum on the bottom of the bond tip to selectively couple a semiconductor device with the bond tip. The bond tip positions the semiconductor device on top of a stack of semiconductor devices to form a semiconductor device assembly. The assembly may be heated to reflow interconnects between the semiconductor device and the top device of the stack of semiconductor devices. Fluid provided through the purge ports may help to counter warpage of the semiconductor device to help form adequate interconnects between the devices. Fluid may also be provided through the vacuum port to counter the warpage.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Yet Hong Tan
  • Patent number: 10892314
    Abstract: A stretchable display device comprises a lower substrate; a plurality of island substrates spaced apart from each other and disposed on the lower substrate; a plurality of pixels defined on the plurality of island substrates; a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 12, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kihan Kim, Hyokang Lee
  • Patent number: 10854527
    Abstract: A semiconductor device package includes a circuit layer, an electronic component, an electronic component, a first passivation layer and a second passivation layer. The circuit layer has a first surface. The electronic component is disposed on the first surface of the circuit layer. The first passivation layer is disposed on the first surface of the circuit layer. The first passivation layer has a first surface facing away the circuit layer. The second passivation layer is disposed on the first surface of the first passivation layer. The second passivation layer has a second surface facing away the circuit layer. A uniformity of the first surface of the first passivation layer is greater than a uniformity of the second surface of the second passivation layer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10854703
    Abstract: A stretchable display device comprises a lower substrate; a plurality of island substrates spaced apart from each other and disposed on the lower substrate; a plurality of pixels defined on the plurality of island substrates; a plurality of base polymers disposed between adjacent island substrates of the plurality of island substrates; and a plurality of conductive particles distributed in the base polymer and electrically connecting a plurality of pads disposed on the adjacent island substrates.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 1, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kihan Kim, Hyokang Lee
  • Patent number: 10840224
    Abstract: Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 10804177
    Abstract: A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 13, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10790160
    Abstract: This invention relates generally to ID frequency identification (RFID) transponders and receivers. More specifically to the methods, apparatus and systems of the fabrication of the transponders and receivers. In one example embodiment, to methods, apparatus, and systems to form effective barriers for devices having a layer structure, including encapsulating at least a portion of the side of the devices from being degraded due to impurity penetration into a laminate structure of the devices, which can cause corrosion or malfunction of the devices.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: September 29, 2020
    Assignee: SMARTRAC TECHNOLOGY GmbH
    Inventors: Laurence Singleton, Ray Freeman
  • Patent number: 10780531
    Abstract: A solder ball includes 0.1% by mass or more and 10% by mass or less of In and a remainder of Sn. The ball has a yellowness (b*) in an L*a*b* color system of 2.8 or more and 15.0 or less and a lightness (L*) of 60 or more and 100 or less. The ball further includes at least one element selected from a group of 0% by mass or more and 4% by mass or less of Ag, 0% by mass or more and 1.0% by mass or less of Cu, 0% to 3% by mass in total of Bi and/or Sb, and 0% to 0.1% by mass in total of an element selected from a group of Ni, Co, Fe, Ge, and P, excluding a solder ball including 3% by mass of Ag, 0.5% by mass of Cu, 0.2% by mass of In and a remainder of Sn.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Hiroyoshi Kawasaki, Yuri Nakamura, Osamu Munekata, Kaichi Tsuruta
  • Patent number: 10777720
    Abstract: A light emitting module includes a first light transmissive insulator, a conductive circuitry layer formed on a surface of the first light transmissive insulator, a second light transmissive insulator disposed so as to face the conductive circuitry layer, a light emitting element disposed between the first light transmissive insulator and the second light transmissive insulator, and connected to the conductive circuitry layer, and a third light transmissive insulator which is disposed between the first light transmissive insulator and the second light transmissive insulator, and which is thermosetting.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10763221
    Abstract: A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 1, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Zhiqiang Niu, Kuang Ming Chang, Lin Chen, Ning Sun, QiHong Huang, Tzu-Hsin Lu
  • Patent number: 10763131
    Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shijian Luo, Jonathan S. Hacker
  • Patent number: 10746524
    Abstract: Disclosed is a film thickness detection device, including a common unit (1) and a detection unit (2); the common unit (1) comprises at least one common electrode (11); the detection unit (2) comprises at least one sensor chip (21) and a signal processing unit (23); the sensor chips (21) are opposite to the common unit (1) in a first direction and are arranged at intervals; the spaces between the common unit (1) and the sensor chips (21) form a transport channel for a to-be-tested film; each of the sensor chips (21) comprises at least one row of multiple detection electrodes (211) arranged along a second direction; the second direction is perpendicular to a moving direction of the to-be-tested film; the first direction is perpendicular to a first plane; the first plane is parallel to the second direction; the sensor chips (21) are configured to induce electrical signals on the common electrodes (11) and output the electrical signals; and the signal processing unit (23) is electrically connected with the sensor
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: August 18, 2020
    Assignee: WEIHAI HAULING OPTO-ELECTRONICS CO., LTD.
    Inventor: Wuchang Qi
  • Patent number: 10741507
    Abstract: Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 11, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Behrooz Mehr, Fernando Chen, Emmanuel de los Santos, Alex Kungo
  • Patent number: 10734347
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 10718643
    Abstract: A suction module for a hand-held power tool includes a motor-driven fan wheel, an intake channel for sucking in dust-laden air, and a collecting container for dust. A flow sensor has a sensor surface, which is formed of plastic and is arranged in the intake channel, an electric field meter facing the sensor surface for determining the electrostatic field strength on the sensor surface, and an evaluating unit for determining a flow rate of dust-laden air on the basis of the determined electrostatic field strength.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 21, 2020
    Assignee: Hilti Aktiengesellschaft
    Inventors: Egon Koenigbauer, Hans Appel
  • Patent number: 10720557
    Abstract: This disclosure discloses a light-emitting device includes a semiconductor light-emitting element having a first electrode and a second electrode, a transparent layer covering the semiconductor light-emitting element, a stretchable electrical connection structure and an electrical contact portion. The stretchable electrical connection structure is formed in the transparent layer and electrically connects the first electrode, and the electrical contact portion is formed on the transparent layer and electrically connects the second electrode.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: July 21, 2020
    Assignee: EPISTAR CORPORATION
    Inventor: Guan-Ru He
  • Patent number: 10665724
    Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 26, 2020
    Assignee: LytEn, Inc.
    Inventors: Katri Pohjonen, Sami Kallioinen, Markku Rouvala
  • Patent number: 10615131
    Abstract: The semiconductor device includes a metal plate, a semiconductor element held on the metal plate, a wiring board connected to a surface electrode of the semiconductor element in a facing manner and a conductor fixed to the wiring board wired to the semiconductor element. The conductor has a plate-like shape. One end of the conductor is arranged to be connectable to an outside. One surface side of another end of the conductor is fixed to a surface of the wiring hoard. The conductor includes at least one protruding step on the one surface of the other end. A top portion of the protruding step includes a contact surface parallel to the surface of the wiring board. The other end of the conductor is fixed to the wiring board by the contact surface and the surface of the wiring board coming into close contact with each other.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasunari Hino
  • Patent number: 10615150
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10593850
    Abstract: A method for manufacturing a light emitting diode package comprises: arranging a first solder and a second solder between a substrate and a light emitting diode; and subjecting the first solder and the second solder to heat treatment to bond the substrate and the light emitting diode. The heat treatment comprises: increasing the temperature of the first and second solders from room temperature to a temperature Tp; maintaining the temperature Tp; and lowering the temperature Tp. The heating step comprises: a first ramping step of increasing a temperature from room temperature to a temperature TA at a constant speed; a pre-heating step of increasing the temperature from the temperature TA to a temperature TB to impart fluidity to the first and second solders; and a second ramping step of increasing the temperature from the TB to TL at a constant speed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 17, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Yeon Cheol Cho, Cun Bok Jeong, Hyoung Jin Lim
  • Patent number: 10573572
    Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chien-Ching Chen
  • Patent number: 10566229
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Patent number: 10566948
    Abstract: An acoustic wave device includes: a first substrate including a terminal located on a lower surface thereof; a second substrate including an acoustic wave element located on a lower surface thereof and mounted on the first substrate so that the element faces the first substrate; first bumps located between the first and second substrates, located between a first side of the first substrate and the element, and not connected to the element and the terminal; second bumps located between the first and second substrates, located between a second side facing the first side and the element, and not connected to the element and/or the terminal; and third bumps located between the first and second substrates, located only in a region located closer to the second side than the first bumps are and closer to the first side than the second bumps are, and connecting the element and the terminal.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Hitoshi Tsukidate
  • Patent number: 10510728
    Abstract: The instant disclosure includes a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator and a method for manufacturing the same. The method includes a leadframe providing step, a chip connecting step and a coil alignment step. The leadframe providing step includes providing a first and a second leadframe each including a chip carrying portion, a coil portion, a plurality of pins and floating pins. The chip connecting step includes disposing at least a first chip and at least a second chip onto the corresponding chip carrying portions for electrically connecting the chips to the pins. The coil alignment step includes arranging the first leadframe above or beneath the second leadframe and applying a first and a second magnetic field to the first and the second leadframes respectively for aligning the coil portions, thereby controlling the coupling effect between two coil portions.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 17, 2019
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Wei-Wen Lai, Pu-Han Lin
  • Patent number: 10472231
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: Invensense, Inc.
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Patent number: 10464510
    Abstract: A power supply device that includes a plurality of electricity storage elements each including lead terminals; a conductive connector connected to the lead terminals; a circuit board including a conductive path; a conductive relay terminal electrically connected to the conductive path, the connector being disposed so as to be in contact with the relay terminal; and a resin holder configured to hold the plurality of electricity storage elements, wherein the holder includes an electricity storage element holder configured to hold the electricity storage elements, a connecting member holder configured to hold the connector, and a fitting groove into which the lead terminals can be fitted, and the connecting member holder is formed so as to traverse the fitting groove.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 5, 2019
    Assignees: SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tatsuya Sumida
  • Patent number: 10453820
    Abstract: Semiconductor assemblies using edge stacking and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise stacked semiconductor packages including a base substrate having a base surface, a side substrate having a side surface orthogonal to the base surface, and a die stack disposed over the base surface and having an outermost die with an outermost surface orthogonal to the side surface. The side substrate can be electrically coupled to the die stack via a plurality of interconnects extending from the side surface of the side substrate to the first surface of the first substrate or the third surface of the outermost die. The semiconductor packages can further comprise a conductive material at an outer surface of the side substrate, thereby allowing the semiconductor packages to be electrically coupled to neighboring semiconductor packages via the conductive material.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10446787
    Abstract: A method for producing a bent organic light-emitting diode and a bent organic light-emitting diode are disclosed. In an embodiment the method includes providing an emitter unit having an organic layer sequence for generating radiation, providing at least one electrical connection piece, bending the at least one connection piece and the emitter unit into a curved shape and subsequently mechanically fixedly and permanently connecting the at least one connection piece to the emitter unit so that the curved shape is permanently maintained.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 15, 2019
    Assignee: OSRAM OLED GmbH
    Inventor: Erwin Lang
  • Patent number: 10440243
    Abstract: An image pickup apparatus includes: an image pickup device including a plurality of convex electrodes disposed on an opposing surface; and a wiring board including a plurality of first edge electrodes on a first main surface and a plurality of second edge electrodes on a second main surface, wherein the wiring board is disposed in an upright state on the opposing surface, the plurality of convex electrodes include first convex electrodes and second convex electrodes, the first convex electrodes are bonded to the first edge electrodes, the second convex electrodes are bonded to the second edge electrodes, and the wiring board is held between the first convex electrodes and the second convex electrodes.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Olympus Corporation
    Inventor: Noriyuki Fujimori
  • Patent number: 10436663
    Abstract: A pressure sensor has a housing, an air lead-in hole, a pressure lead-in hole, an inner cavity, a sensor chip, a lead frame and a cover plate. One end of the air lead-in hole is in communication with the inner cavity of the housing, and the other end of the air lead-in hole is in communication with the air; the pressure lead-in hole is perpendicularly disposed at the center of the upper surface of the housing, two steps are disposed on the upper surface of the inner cavity, and a horizontal surface-mounted device surface is disposed on each of the steps. The center of the sensor chip is aligned with the centers of the pressure lead-in hole, and the lower end of the pressure lead-in holes are in communication with the cavity of the sensor chip.
    Type: Grant
    Filed: September 28, 2014
    Date of Patent: October 8, 2019
    Assignee: WUHAN FINEMEMS INC.
    Inventors: Sheng Liu, Xiaoping Wang, Dengfeng Wu, Fanliang Li, Bin Chen
  • Patent number: 10418298
    Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 10388592
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, provided with a through hole which is surrounded by an inner side surface connecting the first surface to the second surface; a semiconductor element arranged on the first surface side; a wiring layer arranged on the first surface side; a through electrode arranged in the through hole, penetrating the semiconductor substrate, and connected to the wiring layer; and an insulating member arranged between the inner side surface and the through electrode, wherein the insulating member includes a first insulating film arranged between the inner side surface and the through electrode, and includes a second insulating film arranged between the first insulating film and the through electrode, and wherein a crack in the insulating member is in the first insulating film, and the crack is located between the second insulating film and the inner side surface.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 20, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hidemasa Oshige
  • Patent number: 10359613
    Abstract: A method of generating 3D information includes: varying the distance between the sample and an objective lens of the optical microscope at pre-determined steps, capturing an image at each pre-determined step; determining a characteristic value of each pixel in each captured image; determining, for each captured image, the greatest characteristic value across all pixels in the captured image; comparing the greatest characteristic value for each captured image to determine if a surface of the sample is present at each pre-determined step; determining a first captured image that is focused on a first surface of the sample based on the characteristic value of each pixel in each captured image; determining a second captured image that is focused on a second surface of the sample based on the characteristic value of each pixel in each captured image; and determining a first distance between the first surface and the second surface.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 23, 2019
    Assignee: KLA-TENCOR CORPORATION
    Inventors: James Jianguo Xu, Ronny Soetarman, Budi Hartono
  • Patent number: 10305529
    Abstract: Systems and methods may provide for a device including a housing, one or more electronic components positioned within the housing, and a first cured resin composition positioned within the housing, the first cured resin composition including a thermal energy storage material and a first filler material. The device may also include a second cured resin composition positioned within the housing, the second cured resin composition including the thermal energy storage material and a second filler material. The first filler material and the second filler material may be different, wherein the first cured resin composition and the second cured resin composition may encompass at least one of the one or more electronic components. In other examples, the electronic components include a power supply and the device complies with an ATEX equipment directive for explosive atmospheres. Moreover, component underfill and/or assembly overmold processes may be used to fabricate the device.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: David Pidwerbecki, Mark Gallina, Mark Hemmeyer, Steven Lofland, Ponniah Ilavarasan, Michael Stewart, Kevin Byrd
  • Patent number: 10276592
    Abstract: The present disclosure provides a display substrate and a method of fabricating the same, a display panel and a pressure welding device. The display substrate includes a flexible substrate having a first surface and a second surface opposite to each other, and the first surface includes a first area and a second area. The method includes forming thin film transistors and light-emitting elements in the first area, forming a lead for circuit-bonding in the second area, forming a curable material layer on the second surface, and performing a curing process on a part of the curable material layer corresponding to the second area to form a cured layer. The technical solutions of the present disclosure improves the stability of pressure welding during a pressure welding process of circuit component, and lowers the possibility of occurrence of wire defect.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: April 30, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liqiang Chen