Flip-chip-type Assembly Patents (Class 438/108)
  • Patent number: 10665724
    Abstract: A method and apparatus wherein the method comprises: providing at least one electrode within a semiconductor layer wherein the semiconductor layer is provided on a first side of a wafer; thinning the wafer to produce a thinned wafer; providing graphene on a second side of the thinned wafer; attaching the semiconductor layer to an electrical interface on the first side of the thinned wafer; and providing at least one electrical connection from the graphene to the electrical interface so as to form a transistor comprising the at least one electrode and the graphene.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 26, 2020
    Assignee: LytEn, Inc.
    Inventors: Katri Pohjonen, Sami Kallioinen, Markku Rouvala
  • Patent number: 10615150
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 10615131
    Abstract: The semiconductor device includes a metal plate, a semiconductor element held on the metal plate, a wiring board connected to a surface electrode of the semiconductor element in a facing manner and a conductor fixed to the wiring board wired to the semiconductor element. The conductor has a plate-like shape. One end of the conductor is arranged to be connectable to an outside. One surface side of another end of the conductor is fixed to a surface of the wiring hoard. The conductor includes at least one protruding step on the one surface of the other end. A top portion of the protruding step includes a contact surface parallel to the surface of the wiring board. The other end of the conductor is fixed to the wiring board by the contact surface and the surface of the wiring board coming into close contact with each other.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasunari Hino
  • Patent number: 10593850
    Abstract: A method for manufacturing a light emitting diode package comprises: arranging a first solder and a second solder between a substrate and a light emitting diode; and subjecting the first solder and the second solder to heat treatment to bond the substrate and the light emitting diode. The heat treatment comprises: increasing the temperature of the first and second solders from room temperature to a temperature Tp; maintaining the temperature Tp; and lowering the temperature Tp. The heating step comprises: a first ramping step of increasing a temperature from room temperature to a temperature TA at a constant speed; a pre-heating step of increasing the temperature from the temperature TA to a temperature TB to impart fluidity to the first and second solders; and a second ramping step of increasing the temperature from the TB to TL at a constant speed.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 17, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Yeon Cheol Cho, Cun Bok Jeong, Hyoung Jin Lim
  • Patent number: 10573572
    Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chien-Ching Chen
  • Patent number: 10566229
    Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Hsu Chiang, Neng-Tai Shih
  • Patent number: 10566948
    Abstract: An acoustic wave device includes: a first substrate including a terminal located on a lower surface thereof; a second substrate including an acoustic wave element located on a lower surface thereof and mounted on the first substrate so that the element faces the first substrate; first bumps located between the first and second substrates, located between a first side of the first substrate and the element, and not connected to the element and the terminal; second bumps located between the first and second substrates, located between a second side facing the first side and the element, and not connected to the element and/or the terminal; and third bumps located between the first and second substrates, located only in a region located closer to the second side than the first bumps are and closer to the first side than the second bumps are, and connecting the element and the terminal.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Hitoshi Tsukidate
  • Patent number: 10510728
    Abstract: The instant disclosure includes a magnetic coupling package structure with duo leadframes for a magnetically coupled isolator and a method for manufacturing the same. The method includes a leadframe providing step, a chip connecting step and a coil alignment step. The leadframe providing step includes providing a first and a second leadframe each including a chip carrying portion, a coil portion, a plurality of pins and floating pins. The chip connecting step includes disposing at least a first chip and at least a second chip onto the corresponding chip carrying portions for electrically connecting the chips to the pins. The coil alignment step includes arranging the first leadframe above or beneath the second leadframe and applying a first and a second magnetic field to the first and the second leadframes respectively for aligning the coil portions, thereby controlling the coupling effect between two coil portions.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 17, 2019
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Wei-Wen Lai, Pu-Han Lin
  • Patent number: 10472231
    Abstract: A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: Invensense, Inc.
    Inventors: Brian H. Kim, Haijun She, Mozafar Maghsoudnia
  • Patent number: 10464510
    Abstract: A power supply device that includes a plurality of electricity storage elements each including lead terminals; a conductive connector connected to the lead terminals; a circuit board including a conductive path; a conductive relay terminal electrically connected to the conductive path, the connector being disposed so as to be in contact with the relay terminal; and a resin holder configured to hold the plurality of electricity storage elements, wherein the holder includes an electricity storage element holder configured to hold the electricity storage elements, a connecting member holder configured to hold the connector, and a fitting groove into which the lead terminals can be fitted, and the connecting member holder is formed so as to traverse the fitting groove.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 5, 2019
    Assignees: SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tatsuya Sumida
  • Patent number: 10453820
    Abstract: Semiconductor assemblies using edge stacking and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise stacked semiconductor packages including a base substrate having a base surface, a side substrate having a side surface orthogonal to the base surface, and a die stack disposed over the base surface and having an outermost die with an outermost surface orthogonal to the side surface. The side substrate can be electrically coupled to the die stack via a plurality of interconnects extending from the side surface of the side substrate to the first surface of the first substrate or the third surface of the outermost die. The semiconductor packages can further comprise a conductive material at an outer surface of the side substrate, thereby allowing the semiconductor packages to be electrically coupled to neighboring semiconductor packages via the conductive material.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10446787
    Abstract: A method for producing a bent organic light-emitting diode and a bent organic light-emitting diode are disclosed. In an embodiment the method includes providing an emitter unit having an organic layer sequence for generating radiation, providing at least one electrical connection piece, bending the at least one connection piece and the emitter unit into a curved shape and subsequently mechanically fixedly and permanently connecting the at least one connection piece to the emitter unit so that the curved shape is permanently maintained.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 15, 2019
    Assignee: OSRAM OLED GmbH
    Inventor: Erwin Lang
  • Patent number: 10440243
    Abstract: An image pickup apparatus includes: an image pickup device including a plurality of convex electrodes disposed on an opposing surface; and a wiring board including a plurality of first edge electrodes on a first main surface and a plurality of second edge electrodes on a second main surface, wherein the wiring board is disposed in an upright state on the opposing surface, the plurality of convex electrodes include first convex electrodes and second convex electrodes, the first convex electrodes are bonded to the first edge electrodes, the second convex electrodes are bonded to the second edge electrodes, and the wiring board is held between the first convex electrodes and the second convex electrodes.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 8, 2019
    Assignee: Olympus Corporation
    Inventor: Noriyuki Fujimori
  • Patent number: 10436663
    Abstract: A pressure sensor has a housing, an air lead-in hole, a pressure lead-in hole, an inner cavity, a sensor chip, a lead frame and a cover plate. One end of the air lead-in hole is in communication with the inner cavity of the housing, and the other end of the air lead-in hole is in communication with the air; the pressure lead-in hole is perpendicularly disposed at the center of the upper surface of the housing, two steps are disposed on the upper surface of the inner cavity, and a horizontal surface-mounted device surface is disposed on each of the steps. The center of the sensor chip is aligned with the centers of the pressure lead-in hole, and the lower end of the pressure lead-in holes are in communication with the cavity of the sensor chip.
    Type: Grant
    Filed: September 28, 2014
    Date of Patent: October 8, 2019
    Assignee: WUHAN FINEMEMS INC.
    Inventors: Sheng Liu, Xiaoping Wang, Dengfeng Wu, Fanliang Li, Bin Chen
  • Patent number: 10418298
    Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 10388592
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, provided with a through hole which is surrounded by an inner side surface connecting the first surface to the second surface; a semiconductor element arranged on the first surface side; a wiring layer arranged on the first surface side; a through electrode arranged in the through hole, penetrating the semiconductor substrate, and connected to the wiring layer; and an insulating member arranged between the inner side surface and the through electrode, wherein the insulating member includes a first insulating film arranged between the inner side surface and the through electrode, and includes a second insulating film arranged between the first insulating film and the through electrode, and wherein a crack in the insulating member is in the first insulating film, and the crack is located between the second insulating film and the inner side surface.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 20, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hidemasa Oshige
  • Patent number: 10359613
    Abstract: A method of generating 3D information includes: varying the distance between the sample and an objective lens of the optical microscope at pre-determined steps, capturing an image at each pre-determined step; determining a characteristic value of each pixel in each captured image; determining, for each captured image, the greatest characteristic value across all pixels in the captured image; comparing the greatest characteristic value for each captured image to determine if a surface of the sample is present at each pre-determined step; determining a first captured image that is focused on a first surface of the sample based on the characteristic value of each pixel in each captured image; determining a second captured image that is focused on a second surface of the sample based on the characteristic value of each pixel in each captured image; and determining a first distance between the first surface and the second surface.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 23, 2019
    Assignee: KLA-TENCOR CORPORATION
    Inventors: James Jianguo Xu, Ronny Soetarman, Budi Hartono
  • Patent number: 10305529
    Abstract: Systems and methods may provide for a device including a housing, one or more electronic components positioned within the housing, and a first cured resin composition positioned within the housing, the first cured resin composition including a thermal energy storage material and a first filler material. The device may also include a second cured resin composition positioned within the housing, the second cured resin composition including the thermal energy storage material and a second filler material. The first filler material and the second filler material may be different, wherein the first cured resin composition and the second cured resin composition may encompass at least one of the one or more electronic components. In other examples, the electronic components include a power supply and the device complies with an ATEX equipment directive for explosive atmospheres. Moreover, component underfill and/or assembly overmold processes may be used to fabricate the device.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: David Pidwerbecki, Mark Gallina, Mark Hemmeyer, Steven Lofland, Ponniah Ilavarasan, Michael Stewart, Kevin Byrd
  • Patent number: 10276592
    Abstract: The present disclosure provides a display substrate and a method of fabricating the same, a display panel and a pressure welding device. The display substrate includes a flexible substrate having a first surface and a second surface opposite to each other, and the first surface includes a first area and a second area. The method includes forming thin film transistors and light-emitting elements in the first area, forming a lead for circuit-bonding in the second area, forming a curable material layer on the second surface, and performing a curing process on a part of the curable material layer corresponding to the second area to form a cured layer. The technical solutions of the present disclosure improves the stability of pressure welding during a pressure welding process of circuit component, and lowers the possibility of occurrence of wire defect.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: April 30, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Liqiang Chen
  • Patent number: 10249560
    Abstract: The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor device includes a semiconductor integrated circuit and a substrate. The semiconductor integrated circuit is, for example, a semiconductor chip. The coefficient of thermal expansion is different between the semiconductor integrated circuit and the substrate. The substrate includes a plurality of soldering balls on the opposite surface to the surface where the semiconductor integrated circuit is mounted. The substrate does not have the soldering balls at a position corresponding to at least one side of the fringe of the semiconductor integrated circuit.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takafumi Betsui
  • Patent number: 10217685
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Ning Chen
  • Patent number: 10212300
    Abstract: Magnetic keys having a plurality of magnetic plates are disclosed. The location and orientation of the magnetic plates are controlled to generate magnetic fields that are of sufficient strength to be reliably read and sufficient complexity to be difficult to counterfeit. The magnetic keys are located on imaging-device supply items along with non-volatile memory devices containing measurements of the magnetic fields that are digitally signed. These supply items are difficult to counterfeit. Other devices are disclosed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: February 19, 2019
    Assignee: Lexmark International, Inc.
    Inventors: Roger Steven Cannon, Gary Allen Denton, Graydon Randall Dodson, Keith Bryan Hardin
  • Patent number: 10192858
    Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: January 29, 2019
    Assignee: Apple Inc.
    Inventors: John A. Higginson, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 10168524
    Abstract: A method of generating 3D information including: varying the distance between the sample and an objective lens of the optical microscope at pre-determined steps; capturing an image at each pre-determined step; determining a characteristic value of each pixel in each captured image; determining, for each captured image, the greatest characteristic value across a first portion of pixels in the captured image; comparing the greatest characteristic value for each captured image to determine if a surface of the sample is present at each pre-determined step; determining a first captured image that is focused on an apex of a bump of the sample; determining a second captured image that is focused on a first surface of the sample based on the characteristic value of each pixel in each captured image; and determining a first distance between the apex of the bump and the first surface.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 1, 2019
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Ronny Soetarman, James Jianguo Xu
  • Patent number: 10163847
    Abstract: A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 25, 2018
    Assignee: TDK CORPORATION
    Inventors: Makoto Orikasa, Hideyuki Seike, Yuhei Horikawa, Hisayuki Abe
  • Patent number: 10163802
    Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 10134689
    Abstract: A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 20, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vivek S. Sridharan, Amit S. Kelkar, Sriram Muthukumar
  • Patent number: 10109409
    Abstract: A chip electronic component may include a magnetic material body including an insulating substrate and coil conductor patterns formed on at least one surface of the insulating substrate, and external electrodes disposed on both end portions of the magnetic material body so as to be connected to end portions of the coil conductor patterns, respectively. In a cross section of the magnetic material body in a length direction, a thickness of an innermost loop/section of the coil conductor patterns may be smaller than a thickness of the remaining loops/sections of the coil conductor pattern.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Hwan Lee, Chan Yoon, Hye Yeon Cha, Jin Woo Han
  • Patent number: 10103495
    Abstract: Methods and apparatus for providing adaptive grounding in mixed-signal electronic dies, circuits, modules, or other devices. In one example a module in which adaptive grounding is implemented includes a substrate having disposed thereon a plurality of signal contacts and a ground connection, and a mixed-signal die disposed on the substrate and including a signal section and a control section, the signal section having a plurality of radio frequency components each connected to a respective one of the plurality of signal contacts on the substrate by a corresponding signal connector, and the control section having at least two ground paths that selectively connect the control section to the ground connection on the substrate and which are physically spaced apart from one another, the mixed-signal die further including at least two switches, each operable to selectively connect one of the ground paths to the ground connection.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: October 16, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Guillaume Alexandre Blin
  • Patent number: 10076801
    Abstract: A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-woo Song, Sung-il Cho, Se-gi Byun, Jin Yu
  • Patent number: 10049970
    Abstract: A method of manufacturing a semiconductor package according to the present inventive concepts comprises preparing a printed circuit board (PCB) including a protected layer, exposing a portion of the protected layer from the insulating layer, forming a solder ball land by processing the exposed surface of the protected layer, forming a solder ball on the solder ball land, and mounting a semiconductor chip on the solder ball formed on the PCB. The solder balls include copper of about 0.01 wt % to about 0.5 wt %.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hai Liu
  • Patent number: 10020289
    Abstract: Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory cell arrays arranged in line in a first direction in the substrate; a first set of through electrodes arranged between the first and second memory cell arrays, each of the first set of through electrodes penetrating through the substrate, the first set of through electrodes including first and second through electrodes; and a second set of through electrodes arranged between the second and third memory cell arrays, each of the second set of through electrodes penetrating through the substrate, the second set of through electrodes including third and fourth through electrodes.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kayoko Shibata
  • Patent number: 10008395
    Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, William R. Stephenson
  • Patent number: 9953958
    Abstract: An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component, a first underfill resin filled between the first electronic component and the second electronic component, the first underfill resin having a base part arranged around the second electronic component and a convex portion formed on an upper surface of the base part, a third electronic component disposed on and connected to the second electronic component with being in contact with the convex portion of the base part at a peripheral edge portion thereof, and a second underfill resin filled between the second electronic component and the third electronic component.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 24, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Shota Miki
  • Patent number: 9935029
    Abstract: A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the first insulating layer, a second insulating layer formed on first surface side of the first insulating layer, electrodes formed in through holes of the first insulating layer respectively such that the electrodes electrically connect to the conductor pattern and have exposed surfaces exposed from second surface of the first insulating layer, first pads formed on the second insulating layer and positioned to connect an IC chip in center portion of the second insulating layer, second pads formed on the second insulating layer and positioned in outer edge portion of the second insulating layer to connect a second printed wiring board, and via conductors formed in the second insulating layer such that the via conductors electrically connect the first and second pads to the conductor pattern.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 3, 2018
    Assignee: IBIDEN CO., LTD.
    Inventors: Takashi Kariya, Shigeru Yamada, Masatoshi Kunieda
  • Patent number: 9928400
    Abstract: A wiring board for a fingerprint sensor includes a core insulating layer having a thickness of 30 ?m to 100 ?m, an inner buildup insulating layer having a thickness of 17 ?m to 35 ?m, an outer buildup insulating layer having a thickness of 7 ?m to 25 ?m, a plurality of fingerprint reading outer strip-shaped electrodes, a plurality of fingerprint reading inner strip-shaped electrodes, and an upper solder resist layer covering the outer strip-shaped electrodes by a thickness of 3 ?m to 15 ?m.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 27, 2018
    Assignee: KYOCERA CORPORATION
    Inventor: Kohichi Ohsumi
  • Patent number: 9922915
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. [The fusible portion melts at a temperature which avoids damage to the substrate during reflow.] The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 20, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9922891
    Abstract: A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soyoung Lim, JaeMin Jung, Jeong-Kyu Ha, Donghan Kim
  • Patent number: 9911904
    Abstract: A composite board is provided with a board and a covering member. The board includes a base made of ceramics, first wiring provided on an upper surface of the base, and second wiring provided on a lower surface of the base and electrically connected to the first wiring. The covering member covers the base such that the first wiring and the second wiring are exposed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 6, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Tadao Hayashi
  • Patent number: 9899337
    Abstract: A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gun-ho Chang, Tae-je Cho, Jong-bo Shim
  • Patent number: 9886614
    Abstract: A wiring board for a fingerprint sensor includes an insulating board including a plurality of laminated insulating layers, a plurality of fingerprint reading outer strip-shaped electrodes, a plurality of fingerprint reading inner strip-shaped electrodes, and a projection electrode formed on the inner strip-shaped electrode and projecting toward a space between the outer strip-shaped electrodes, in which a horizontal distance between the projection electrode and the outer strip-shaped electrode is 5 ?m to 20 ?m, and an upper surface of the projection electrode is covered with the uppermost insulating layer by a thickness of 1 ?m to 10 ?m.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: February 6, 2018
    Assignee: KYOCERA CORPORATION
    Inventor: Sumiko Noguchi
  • Patent number: 9887173
    Abstract: A method for producing a sinter layer connection between a substrate and a chip resulting in an electric and thermal connection therebetween and in reduced mechanical tensions within the chip. The method produces a sinter layer by applying a multitude of sinter elements of a base material forming the sinter layer in structured manner on a contact area of a main surface of a substrate; placing a chip to be joined to the substrate on the sinter elements; and heating and compressing the sinter elements to produce a structured sinter layer connecting the substrate and chip and extending within the contact area, the surface coverage density of the sinter elements on the substrate in a center region of the contact area being greater than the surface coverage density of the sinter elements in an edge region of the contact area, and at least one through channel, extending laterally as to the substrate's main surface being provided towards the contact area's edge.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: February 6, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Michael Guyenot, Michael Guenther, Thomas Herboth
  • Patent number: 9847234
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 9847298
    Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 19, 2017
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yasuhiro Kawase, Makoto Ikemoto, Hideki Kiritani
  • Patent number: 9832882
    Abstract: Provided herein is a conductive pattern making method and conductive pattern, the method including forming a groove such that its width in an inlet area is bigger than its width in an inner area; filling the groove with a conductive ink composition; and drying the conductive ink composition so that a solvent contained in the conductive ink composition inside the groove is volatilized to reduce the volume of the conductive ink composition.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 28, 2017
    Assignee: INKTEC CO., LTD.
    Inventors: Kwang-Choon Chung, Ji Hoon Yoo, Joonki Seong, Dae Sang Han, Nam-Boo Cho
  • Patent number: 9825008
    Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Ju Chen, Jie Chen, Hsien-Wei Chen
  • Patent number: 9806034
    Abstract: A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 31, 2017
    Assignee: Nexperia B.V.
    Inventors: Hans-Juergen Funke, Tobias Sprogies, Rolf Brenner, Rüdiger Weber, Wolfgang Schnitt, Frank Burmeister
  • Patent number: 9786573
    Abstract: An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the first resin layer and the second resin layer; and an electronic component disposed in the cavity, wherein a thickness of the first resin layer is different from a thickness of the second resin layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong-Rip Kim, Doo-Hwan Lee, Jong-Myeon Lee
  • Patent number: 9748194
    Abstract: An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed therebetween, and a sealing member that seals the first and second electronic components on the mount board. A thickness of the first electronic component is larger than a thickness of the second electronic component, and a height of the bump bonded to the first electronic component is smaller than a height of the bump bonded to the second electronic component.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 29, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yuji Toyota
  • Patent number: 9721900
    Abstract: Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 1, 2017
    Assignee: J-Devices Corporation
    Inventor: Naoki Hayashi